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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Qualcomm SM8650 based HDK (Hardware Development Kit). Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 66beaac60e1d..fc0649da74b9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1007,6 +1007,7 @@ properties: =20 - items: - enum: + - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd - const: qcom,sm8650 --=20 2.34.1 From nobody Mon Feb 9 03:17:07 2026 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E4691A702 for ; Fri, 23 Feb 2024 08:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The SM8650-HDK is an embedded development platforms for the Snapdragon 8 Gen 3 SoC aka SM8650, with the following features: - Qualcomm SM8650 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 1259 +++++++++++++++++++++++++++= ++++ 2 files changed, 1260 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 7d40ec5e7d21..4f48c98451de 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-sony-xperia-nagara-= pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8650-hdk.dts new file mode 100644 index 000000000000..cb1e0f569483 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -0,0 +1,1259 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SM8650 HDK"; + compatible =3D "qcom,sm8650-hdk", "qcom,sm8650"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart15; + serial1 =3D &uart14; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint =3D <<9611_out>; + }; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_BLUETOOTH; + color =3D ; + gpios =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "bluetooth-power"; + default-state =3D "off"; + }; + + led-1 { + function =3D LED_FUNCTION_INDICATOR; + color =3D ; + gpios =3D <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + panic-indicator; + }; + + led-2 { + function =3D LED_FUNCTION_WLAN; + color =3D ; + gpios =3D <&pm8550b_gpios 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "phy0tx"; + default-state =3D "off"; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "LT9611_1V2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + vin-supply =3D <&vph_pwr>; + gpio =3D <&tlmm 79 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "LT9611_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + vin-supply =3D <&vreg_bob_3v3>; + gpio =3D <&tlmm 78 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + sound { + compatible =3D "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model =3D "SM8650-HDK"; + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT3", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai =3D <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacr= o 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_bob_3v3: regulator-vreg-bob-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_BOB_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + vin-supply =3D <&vph_pwr>; + }; + + wcd939x: audio-codec { + compatible =3D "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + + #sound-dai-cells =3D <1>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s1c_1p2>; + vdd-l12-supply =3D <&vreg_s6c_1p8>; + vdd-l15-supply =3D <&vreg_s6c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + qcom,pmic-id =3D "b"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1c_1p2>; + vdd-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "c"; + + vreg_s1c_1p2: smps1 { + regulator-name =3D "vreg_s1c_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1348000>; + regulator-initial-mode =3D ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name =3D "vreg_s2c_0p8"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <1036000>; + regulator-initial-mode =3D ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name =3D "vreg_s3c_0p9"; + regulator-min-microvolt =3D <976000>; + regulator-max-microvolt =3D <1064000>; + regulator-initial-mode =3D ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name =3D "vreg_s4c_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1280000>; + regulator-initial-mode =3D ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name =3D "vreg_s5c_0p7"; + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <900000>; + regulator-initial-mode =3D ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name =3D "vreg_s6c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name =3D "vreg_l3c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name =3D "vreg_l3e_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name =3D "vreg_l1g_0p91"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name =3D "vreg_l3g_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l2-supply =3D <&vreg_s3c_0p9>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s4-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "i"; + + vreg_s4i_0p85: smps4 { + regulator-name =3D "vreg_s4i_0p85"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name =3D "vreg_l1i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name =3D "vreg_l2i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name =3D "vreg_l3i_0p91"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "m"; + + vdd-l1-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-l4-supply =3D <&vreg_bob2>; + vdd-l5-supply =3D <&vreg_s6c_1p8>; + vdd-l6-supply =3D <&vreg_bob1>; + vdd-l7-supply =3D <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name =3D "vreg_l1m_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name =3D "vreg_l2m_1p056"; + regulator-min-microvolt =3D <1056000>; + regulator-max-microvolt =3D <1056000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name =3D "vreg_l4m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name =3D "vreg_l5m_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name =3D "vreg_l6m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name =3D "vreg_l7m_2p96"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "n"; + + vdd-l1-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-l4-supply =3D <&vreg_s6c_1p8>; + vdd-l5-supply =3D <&vreg_bob2>; + vdd-l6-supply =3D <&vreg_bob2>; + vdd-l7-supply =3D <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name =3D "vreg_l1n_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name =3D "vreg_l2n_1p056"; + regulator-min-microvolt =3D <1056000>; + regulator-max-microvolt =3D <1056000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name =3D "vreg_l3n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name =3D "vreg_l4n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name =3D "vreg_l5n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name =3D "vreg_l6n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name =3D "vreg_l7n_3p3"; + regulator-min-microvolt =3D <3304000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&i2c6 { + clock-frequency =3D <400000>; + status =3D "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible =3D "lontium,lt9611uxc"; + reg =3D <0x2b>; + + interrupts-extended =3D <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 28 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <<9611_1v2>; + vcc-supply =3D <<9611_3v3>; + + pinctrl-0 =3D <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lt9611_a: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg =3D <2>; + + lt9611_out: endpoint { + remote-endpoint =3D <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&i2c3 { + status =3D "okay"; + + wcd_usbss: typec-mux@e { + compatible =3D "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg =3D <0xe>; + + vdd-supply =3D <&vreg_l15b_1p8>; + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader =3D "self"; + memory-region =3D <&ipa_fw_mem>; + firmware-name =3D "qcom/sm8650/ipa_fws.mbn"; + status =3D "okay"; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <<9611_a>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1i_0p88>; + + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; +}; + +&mdss_mdp { + status =3D "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency =3D <1000>; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1i_0p88>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3e_0p9>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + vdda-qref-supply =3D <&vreg_l1i_0p88>; + + status =3D "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source =3D <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + bias-pull-up; + input-enable; + power-source =3D <1>; + }; +}; + +/* The RGB signals are routed to 3 separate LEDs on the HDK8650 */ +&pm8550_pwm { + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "okay"; + + led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + default-state =3D "off"; + }; + + led@2 { + reg =3D <2>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + default-state =3D "off"; + }; + + led@3 { + reg =3D <3>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + default-state =3D "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pmk8550_rtc { + status =3D "okay"; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up =3D <2200>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8650/adsp.mbn", + "qcom/sm8650/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8650/cdsp.mbn", + "qcom/sm8650/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/sm8650/modem.mbn", + "qcom/sm8650/modem_dtb.mbn"; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&swr0 { + status =3D "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + pinctrl-0 =3D <&spkr_1_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lpass_tlmm 21 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l3c_1p2>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + pinctrl-0 =3D <&spkr_2_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l3c_1p2>; + }; +}; + +&swr1 { + status =3D "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010e00"; + reg =3D <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=3D> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=3D> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=3D> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=3D> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=3D> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=3D> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping =3D <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010e00"; + reg =3D <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=3D> SWR2 Port 3 (TX SWR_INPU= T 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=3D> SWR2 Port 4 (TX SWR_INPU= T 8,9,10,11) + */ + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges =3D <32 8>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio17"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio18"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins =3D "gpio85"; + function =3D "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins =3D "gpio28"; + function =3D "gpio"; + output-high; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins =3D "gpio77"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio107"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddio-supply =3D <&vreg_l3c_1p2>; + vddaon-supply =3D <&vreg_l15b_1p8>; + vdddig-supply =3D <&vreg_s3c_0p9>; + vddrfa0p8-supply =3D <&vreg_s3c_0p9>; + vddrfa1p2-supply =3D <&vreg_s1c_1p2>; + vddrfa1p9-supply =3D <&vreg_s6c_1p8>; + + max-speed =3D <3200000>; + + enable-gpios =3D <&tlmm 17 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&bt_default>; + pinctrl-names =3D "default"; + }; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1c_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> USB-C + */ + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1i_0p88>; + vdda12-supply =3D <&vreg_l3i_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3i_1p2>; + vdda-pll-supply =3D <&vreg_l3g_0p91>; + + orientation-switch; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint =3D <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint =3D <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.34.1 From nobody Mon Feb 9 03:17:07 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C054B1AAD8 for ; Fri, 23 Feb 2024 08:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 23 Feb 2024 00:52:16 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 11-20020a056000156b00b0033d1b760125sm2028168wrz.92.2024.02.23.00.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Feb 2024 00:52:15 -0800 (PST) From: Neil Armstrong Date: Fri, 23 Feb 2024 09:52:09 +0100 Subject: [PATCH 3/3] arch: arm64: dts: sm8650-hdk: add support for the Display Card overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240223-topic-sm8650-upstream-hdk-v1-3-ccca645cd901@linaro.org> References: <20240223-topic-sm8650-upstream-hdk-v1-0-ccca645cd901@linaro.org> In-Reply-To: <20240223-topic-sm8650-upstream-hdk-v1-0-ccca645cd901@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE With the SM8650-HDK, a Display Card kit can be connected to provide a VTDR6130 display with Goodix Berlin Touch controller. In order to route the DSI lanes to the connector for the Display Card kit, a switch must be changed on the board. The HDMI nodes are disabled since the DSI lanes are shared with the DSI to HDMI transceiver. Add support for this card as an overlay and apply it it at build-time to the sm8650-hdk dtb. Signed-off-by: Neil Armstrong Reviewed-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/sm8650-hdk-display-card.dtso | 151 +++++++++++++++++= ++++ 2 files changed, 155 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4f48c98451de..566997db4b37 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -241,6 +241,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8450-sony-xperia-nagara= -pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-qrd.dtb + +sm8650-hdk-display-card-dtbs :=3D sm8650-hdk.dtb sm8650-hdk-display-card.d= tbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/a= rm64/boot/dts/qcom/sm8650-hdk-display-card.dtso new file mode 100644 index 000000000000..b9de6c9ce10e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/* + * Display Card kit overlay + * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the d= isplay panel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&i2c6 { + status =3D "disabled"; +}; + +<9611_1v2 { + status =3D "disabled"; +}; + +<9611_3v3 { + status =3D "disabled"; +}; + +&vreg_bob_3v3 { + status =3D "disabled"; +}; + +<9611_codec { + status =3D "disabled"; +}; + +&mdss_dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "visionox,vtdr6130"; + reg =3D <0>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply =3D <&vreg_l12b_1p8>; + vci-supply =3D <&vreg_l13b_3p0>; + vdd-supply =3D <&vreg_l11b_1p2>; + + pinctrl-0 =3D <&disp0_reset_n_active>, <&mdp_vsync_active>; + pinctrl-1 =3D <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>; + pinctrl-names =3D "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; + + /* + * DTC requires to have both endpoints when compiling the overlay + * and also requires the #address/size-cells + reg properties + */ + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + }; + }; + }; +}; + +&spi4 { + /* DTC requires the #address/size-cells to compile DTBO */ + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "okay"; + + touchscreen@0 { + compatible =3D "goodix,gt9916"; + reg =3D <0>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <162 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios =3D <&tlmm 161 GPIO_ACTIVE_LOW>; + + avdd-supply =3D <&vreg_l14b_3p2>; + + spi-max-frequency =3D <1000000>; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <2400>; + + pinctrl-0 =3D <&ts_irq>, <&ts_reset>; + pinctrl-names =3D "default"; + }; +}; + +&tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + mdp_vsync_active: mdp-vsync-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + mdp_vsync_suspend: mdp-vsync-suspend-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins =3D "gpio161"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins =3D "gpio162"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; +}; --=20 2.34.1