From nobody Sun Feb 8 15:57:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E2F6823AE; Fri, 23 Feb 2024 13:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708695525; cv=none; b=pTPsrx8VIZaSJ6AN9tjcp1IMu/4aTbA8iiNmxM11zBaEqfInDMgItrZdqHIzivmC90uwt2m9VspZRF+vT308pb92S2q0SOKSJIDyhZv9Mi/54Vh8wCGW/xMNHBpVnusBPifrLu6s3qCbHkV4DwYjj6E0VairnTCkBtw4bkAR7b8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708695525; c=relaxed/simple; bh=n7EJGb6r/9uWhXBTxysKjx17Y2iaQNTqlPUbVd030hI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rxERmYSxqCzqbm5LOvrItHeLk1lMJRWMeL7z+m6e0VGNECKG9urm4i+GtostmpWZ/0Me4sOku11MwW/oRowz2DUAGtGDzNdqm7Bpy6+mX3C297Eo7eXx9XIvjZfFogTVRwPF4Et6LpKBdLNu871aFJ6/leM250Acds/saPY7ITw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YnagCjM0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YnagCjM0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D0BAC43399; Fri, 23 Feb 2024 13:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708695525; bh=n7EJGb6r/9uWhXBTxysKjx17Y2iaQNTqlPUbVd030hI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YnagCjM0KBRU4knIa5ukmyCLbIBQ79mVq8ZFaUsG4bPoq3W2BaAfbzZvmZXqEfMtQ YYmdDI6hwLjWm88p8iugiOesjBI7iZxep5trLFczsqllK4hpZ/qXJGzNeDR4h2fg+J XfR4Xs48Ge1PZ8kmw6IVM1ETX8+ykApcfKU7+kbEl0YfhUTmIh/6bCoD6J+79yZO55 2jPbKdE3fhQQWwIKWFQ8ZJSH78wyHoY0ZMjuiBRZb+ZZ9dEoc78qmnj6RZKr3Vlpot L6eYVy1EjkbMwlLCm3iCTXf2YQDgGfCqRjRbPBj0PCbYI0ErS8EEwSqwMYIiQ5hXi8 6QYi5pY8GEQnA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Nathan Chancellor , Nick Desaulniers , Tom Rix , rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev Subject: [PATCH v2 3/3] RISC-V: enable building 64-bit kernels with rust support Date: Fri, 23 Feb 2024 13:38:05 +0000 Message-ID: <20240223-palatable-quintuple-ed221a517407@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223-leverage-walmart-5424542cd8bd@spud> References: <20240223-leverage-walmart-5424542cd8bd@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2571; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=dXiTCnXsPq6szb52W4FfTLrkIWRphwTLGk/WpEPIpxA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKk35u+R+n7i+OwT39IUWaQPMGd9WVleuj/N9dhv5lkZX 950bXrd0VHKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJeL1nZNg/wWKXZM7OpDYn 8zeiOy94+N68+CslNMT1aGxkUqdO6GWGP1wisa+2BoUt0/q+ds2FPTL/DtavLuPzr4z/Oe/D15q /ZWwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Miguel Ojeda The rust modules work on 64-bit RISC-V, with no twiddling required. Select HAVE_RUST and provide the required flags to kbuild so that the modules can be used. The Makefile and Kconfig changes are lifted from work done by Miguel in the Rust-for-Linux tree, hence his authorship. Following the rabbit hole, the Makefile changes originated in a script, created based on config files originally added by Gary, hence his co-authorship. 32-bit is broken in core rust code, so support is limited to 64-bit: ld.lld: error: undefined symbol: __udivdi3 As 64-bit RISC-V is now supported, add it to the arch support table, taking the opportunity to sort the table in alphabetical order. Co-developed-by: Gary Guo Signed-off-by: Gary Guo Signed-off-by: Miguel Ojeda Signed-off-by: Conor Dooley --- Documentation/rust/arch-support.rst | 1 + arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 2 ++ 3 files changed, 4 insertions(+) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index 73203ba1e901..9e18a81fc2ef 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -16,6 +16,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`= ` file. Architecture Level of support Constraints =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D ``loongarch`` Maintained - +``riscv`` Maintained ``riscv64`` only. ``um`` Maintained ``x86_64`` only. ``x86`` Maintained ``x86_64`` only. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5c59e00405e3..3eaae08e1d5c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -142,6 +142,7 @@ config RISCV select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RETHOOK if !XIP_KERNEL select HAVE_RSEQ + select HAVE_RUST if 64BIT select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index ebbe02628a27..22fdb1e83744 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -34,6 +34,8 @@ ifeq ($(CONFIG_ARCH_RV64I),y) KBUILD_AFLAGS +=3D -mabi=3Dlp64 =20 KBUILD_LDFLAGS +=3D -melf64lriscv + + KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dgeneric-rv64 else BITS :=3D 32 UTS_MACHINE :=3D riscv32 --=20 2.43.0