From nobody Fri Dec 19 19:18:16 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1BB573F1D for ; Thu, 22 Feb 2024 18:39:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708627183; cv=none; b=rn2PcW9aPL5qF8sxyGVMTKaqYYUVNm8/GOyXmeAF/GXPDUwzDTtMfRWES5arqP6FHC175LsH0FxNtmUGDBKS3/Z8DMlQJmRtlGk1T4FktBgXfnj7VLXre0AyQ8gpOSxSfFp+iIQcQmlTsnrgh8kdKmJ378Ezh+Tol7xfpgyF78U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708627183; c=relaxed/simple; bh=h76VDu0EROS/tTcoE66OS4rO/lFWal4QuWjQ1nU8EXg=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=n00zM+Ke8KAd2W/djeOR7hpf2bmi6JsnjRf9UK9iRdFcTDwjAyreQ6GnsZyqguE+JFQWZYPd27dsPTSroPEhlSJ9upxL12c/wqaS0CYkU01xMyp+Inuio81EXuSKpF6XNJXT2kNCc7HNfXyFfaq2LN0NC42RLvbSemKduVV4rho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BqgdZSss; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BqgdZSss" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708627182; x=1740163182; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=h76VDu0EROS/tTcoE66OS4rO/lFWal4QuWjQ1nU8EXg=; b=BqgdZSssjo8NRgp7GKU4Z5tsL2FqiXpsrb9DYzPJeVWdQwirNSOfnJrP vKHwPP1MMNd4kXbeOTPJiG5LODCPiBo7GafhDqQZqWdZf3yaYAW/yKNXM rKhRRbbmIw5OQv6Sxzs6I8LQ7twzHmkcHZBHOy0mj3yMB8moS06khJufg 2/yFzE87FntB8zr7EAoifwyQysDFxN73ESVTD6ZMVachcZBBX8m996ynu cCI97TtK59GN+4swqkldRIPD2gIJjHbeVmUVfxcV06gx8COSP3gRDc0Ge J9oEvNyMxBmZ7f9aGYve+xord5WKaq6FQRphK95b5ouuYrpB4W4S3sDmX A==; X-IronPort-AV: E=McAfee;i="6600,9927,10992"; a="3031768" X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="3031768" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2024 10:39:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="5975484" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa008.jf.intel.com with ESMTP; 22 Feb 2024 10:39:42 -0800 Subject: [RFC][PATCH 11/34] x86/cpu/intel: Prepare MKTME for "address configuration" infrastructure To: linux-kernel@vger.kernel.org Cc: kirill.shutemov@linux.intel.com,pbonzini@redhat.com,tglx@linutronix.de,x86@kernel.org,bp@alien8.de,Dave Hansen From: Dave Hansen Date: Thu, 22 Feb 2024 10:39:41 -0800 References: <20240222183926.517AFCD2@davehans-spike.ostc.intel.com> In-Reply-To: <20240222183926.517AFCD2@davehans-spike.ostc.intel.com> Message-Id: <20240222183941.7CB634A5@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Intel also does memory encryption and also fiddles with the physical address bits. This is currently called for *each* CPU, but practically only done on the boot CPU because of 'mktme_status'. Move it from the "each CPU" ->c_init() function to ->c_bsp_init() where the whole thing only gets called once ever. This also necessitates moving detect_tme() and its entourage around in the file. Signed-off-by: Dave Hansen Reviewed-by: Kai Huang --- b/arch/x86/kernel/cpu/intel.c | 174 +++++++++++++++++++++----------------= ----- 1 file changed, 87 insertions(+), 87 deletions(-) diff -puN arch/x86/kernel/cpu/intel.c~intel-move-TME-detection arch/x86/ker= nel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~intel-move-TME-detection 2024-02-22 10:08= :53.820663775 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:53.824663932 -0800 @@ -324,9 +324,96 @@ static void early_init_intel(struct cpui detect_ht_early(c); } =20 +#define MSR_IA32_TME_ACTIVATE 0x982 + +/* Helpers to access TME_ACTIVATE MSR */ +#define TME_ACTIVATE_LOCKED(x) (x & 0x1) +#define TME_ACTIVATE_ENABLED(x) (x & 0x2) + +#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ +#define TME_ACTIVATE_POLICY_AES_XTS_128 0 + +#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ + +#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ +#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 + +/* Values for mktme_status (SW only construct) */ +#define MKTME_ENABLED 0 +#define MKTME_DISABLED 1 +#define MKTME_UNINITIALIZED 2 +static int mktme_status =3D MKTME_UNINITIALIZED; + +static void detect_tme(struct cpuinfo_x86 *c) +{ + u64 tme_activate, tme_policy, tme_crypto_algs; + int keyid_bits =3D 0, nr_keyids =3D 0; + static u64 tme_activate_cpu0 =3D 0; + + rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); + + if (mktme_status !=3D MKTME_UNINITIALIZED) { + if (tme_activate !=3D tme_activate_cpu0) { + /* Broken BIOS? */ + pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); + pr_err_once("x86/tme: MKTME is not usable\n"); + mktme_status =3D MKTME_DISABLED; + + /* Proceed. We may need to exclude bits from x86_phys_bits. */ + } + } else { + tme_activate_cpu0 =3D tme_activate; + } + + if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activ= ate)) { + pr_info_once("x86/tme: not enabled by BIOS\n"); + mktme_status =3D MKTME_DISABLED; + return; + } + + if (mktme_status !=3D MKTME_UNINITIALIZED) + goto detect_keyid_bits; + + pr_info("x86/tme: enabled by BIOS\n"); + + tme_policy =3D TME_ACTIVATE_POLICY(tme_activate); + if (tme_policy !=3D TME_ACTIVATE_POLICY_AES_XTS_128) + pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); + + tme_crypto_algs =3D TME_ACTIVATE_CRYPTO_ALGS(tme_activate); + if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { + pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", + tme_crypto_algs); + mktme_status =3D MKTME_DISABLED; + } +detect_keyid_bits: + keyid_bits =3D TME_ACTIVATE_KEYID_BITS(tme_activate); + nr_keyids =3D (1UL << keyid_bits) - 1; + if (nr_keyids) { + pr_info_once("x86/mktme: enabled by BIOS\n"); + pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); + } else { + pr_info_once("x86/mktme: disabled by BIOS\n"); + } + + if (mktme_status =3D=3D MKTME_UNINITIALIZED) { + /* MKTME is usable */ + mktme_status =3D MKTME_ENABLED; + } + + /* + * KeyID bits effectively lower the number of physical address + * bits. Update cpuinfo_x86::x86_phys_bits accordingly. + */ + c->x86_phys_bits -=3D keyid_bits; +} + static void bsp_init_intel(struct cpuinfo_x86 *c) { resctrl_cpu_detect(c); + + if (cpu_has(c, X86_FEATURE_TME)) + detect_tme(c); } =20 #ifdef CONFIG_X86_32 @@ -482,90 +569,6 @@ static void srat_detect_node(struct cpui #endif } =20 -#define MSR_IA32_TME_ACTIVATE 0x982 - -/* Helpers to access TME_ACTIVATE MSR */ -#define TME_ACTIVATE_LOCKED(x) (x & 0x1) -#define TME_ACTIVATE_ENABLED(x) (x & 0x2) - -#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ -#define TME_ACTIVATE_POLICY_AES_XTS_128 0 - -#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ - -#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ -#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 - -/* Values for mktme_status (SW only construct) */ -#define MKTME_ENABLED 0 -#define MKTME_DISABLED 1 -#define MKTME_UNINITIALIZED 2 -static int mktme_status =3D MKTME_UNINITIALIZED; - -static void detect_tme(struct cpuinfo_x86 *c) -{ - u64 tme_activate, tme_policy, tme_crypto_algs; - int keyid_bits =3D 0, nr_keyids =3D 0; - static u64 tme_activate_cpu0 =3D 0; - - rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); - - if (mktme_status !=3D MKTME_UNINITIALIZED) { - if (tme_activate !=3D tme_activate_cpu0) { - /* Broken BIOS? */ - pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); - pr_err_once("x86/tme: MKTME is not usable\n"); - mktme_status =3D MKTME_DISABLED; - - /* Proceed. We may need to exclude bits from x86_phys_bits. */ - } - } else { - tme_activate_cpu0 =3D tme_activate; - } - - if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activ= ate)) { - pr_info_once("x86/tme: not enabled by BIOS\n"); - mktme_status =3D MKTME_DISABLED; - return; - } - - if (mktme_status !=3D MKTME_UNINITIALIZED) - goto detect_keyid_bits; - - pr_info("x86/tme: enabled by BIOS\n"); - - tme_policy =3D TME_ACTIVATE_POLICY(tme_activate); - if (tme_policy !=3D TME_ACTIVATE_POLICY_AES_XTS_128) - pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); - - tme_crypto_algs =3D TME_ACTIVATE_CRYPTO_ALGS(tme_activate); - if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { - pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", - tme_crypto_algs); - mktme_status =3D MKTME_DISABLED; - } -detect_keyid_bits: - keyid_bits =3D TME_ACTIVATE_KEYID_BITS(tme_activate); - nr_keyids =3D (1UL << keyid_bits) - 1; - if (nr_keyids) { - pr_info_once("x86/mktme: enabled by BIOS\n"); - pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); - } else { - pr_info_once("x86/mktme: disabled by BIOS\n"); - } - - if (mktme_status =3D=3D MKTME_UNINITIALIZED) { - /* MKTME is usable */ - mktme_status =3D MKTME_ENABLED; - } - - /* - * KeyID bits effectively lower the number of physical address - * bits. Update cpuinfo_x86::x86_phys_bits accordingly. - */ - c->x86_phys_bits -=3D keyid_bits; -} - static void init_cpuid_fault(struct cpuinfo_x86 *c) { u64 msr; @@ -702,9 +705,6 @@ static void init_intel(struct cpuinfo_x8 =20 init_ia32_feat_ctl(c); =20 - if (cpu_has(c, X86_FEATURE_TME)) - detect_tme(c); - init_intel_misc_features(c); =20 split_lock_init(); _