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AJvYcCUVDPzq+Qe4ooN4G0Lyq+ElXwxD0ioxVCaKDSPhW6XsCpJHt4wHdECdUoNrcEfUBor2mRUSYBFhqL/GJLhpu4gvWzxQsp8iqfWk9LsS X-Gm-Message-State: AOJu0YzlXhsJG0upWoGuE3gHEKHaz6sG4Dcx9ug3phWLfRJrTdZYyv2J igDMfeW0hbpxALD656z/0PJ7JweuyNPRAbq5hI3MI2RpURs4En/YX0yJIm7istc= X-Google-Smtp-Source: AGHT+IEOb1Yx2hf7SfgFjAX4PLImkj9wNrlWxC26sYi3FIjcQ1SGd91HFyROaXeS/Zjiup30flFeDw== X-Received: by 2002:a05:6808:d47:b0:3c1:8039:f8b9 with SMTP id w7-20020a0568080d4700b003c18039f8b9mr408375oik.21.1708594880741; Thu, 22 Feb 2024 01:41:20 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n15-20020a05680803af00b003c17c2b8d09sm130699oie.31.2024.02.22.01.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 01:41:20 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v14 08/18] irqchip/riscv-intc: Add support for RISC-V AIA Date: Thu, 22 Feb 2024 15:09:56 +0530 Message-Id: <20240222094006.1030709-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240222094006.1030709-1-apatel@ventanamicro.com> References: <20240222094006.1030709-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller Add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index e8d01b14ccdd..8997f6986f89 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -30,6 +31,14 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) generic_handle_domain_irq(intc_domain, cause); } =20 +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi =3D csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +48,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *r= egs) =20 static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +130,18 @@ static struct fwnode_handle *riscv_intc_hwnode(void) =20 static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs =3D riscv_isa_extension_available(NULL, SxAIA) ? 64 : BIT= S_PER_LONG; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain =3D irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_= ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } =20 - rc =3D set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc =3D set_handle_irq(&riscv_intc_aia_irq); + else + rc =3D set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +149,8 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", nr_irqs, + riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : ""); =20 return 0; } --=20 2.34.1