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AJvYcCUxkeg5sEp0r1uNLmZkR1LYzI81Gu+ZIgEEFq3YVwNjoYyb/5BXkhYmTtNxJ5D/6BPfyLxqvUj3qEr+6VLjbQ19MH7RSDS3WbqtgFH3 X-Gm-Message-State: AOJu0YyYS95OEeb6ClG9Bd4t3+FMki/RuMKBEO23WAfvT/L3gTohHJhW OabErHENFimLbX0l6c4pFUf5lVnQObIZiUfG0Cr1OORUpK+UxxG8343szRI8d4Q= X-Google-Smtp-Source: AGHT+IGT29HtRoxTfhVvish182aY0aMpJ/2Uit/NlU+Lw0THPvmpBIMgrKBSZWm+oKAJD2qN/cmTKA== X-Received: by 2002:a05:6808:1291:b0:3c1:377a:4641 with SMTP id a17-20020a056808129100b003c1377a4641mr28333878oiw.24.1708594857974; Thu, 22 Feb 2024 01:40:57 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n15-20020a05680803af00b003c17c2b8d09sm130699oie.31.2024.02.22.01.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 01:40:57 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v14 05/18] irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure Date: Thu, 22 Feb 2024 15:09:53 +0530 Message-Id: <20240222094006.1030709-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240222094006.1030709-1-apatel@ventanamicro.com> References: <20240222094006.1030709-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SiFive PLIC contexts should not be left dangling if irqdomain creation fails because plic_starting_cpu() can crash accessing unmapped registers. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 20 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 615498071b6e..f0df5d0cb76e 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -416,17 +416,45 @@ static const struct of_device_id plic_match[] =3D { {} }; =20 +static int plic_parse_context_parent(struct platform_device *pdev, u32 con= text, + u32 *parent_hwirq, int *parent_cpu) +{ + struct device *dev =3D &pdev->dev; + struct of_phandle_args parent; + unsigned long hartid; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, &hartid); + if (rc) + return rc; + + *parent_hwirq =3D parent.args[0]; + *parent_cpu =3D riscv_hartid_to_cpuid(hartid); + return 0; +} + static int plic_probe(struct platform_device *pdev) { - int error =3D 0, nr_contexts, nr_handlers =3D 0, i; + int error =3D 0, nr_contexts, nr_handlers =3D 0, cpu, i; struct device *dev =3D &pdev->dev; unsigned long plic_quirks =3D 0; struct plic_handler *handler; + u32 nr_irqs, parent_hwirq; struct irq_domain *domain; struct plic_priv *priv; + irq_hw_number_t hwirq; bool cpuhp_setup; - unsigned int cpu; - u32 nr_irqs; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -462,13 +490,9 @@ static int plic_probe(struct platform_device *pdev) return -EINVAL; =20 for (i =3D 0; i < nr_contexts; i++) { - struct of_phandle_args parent; - irq_hw_number_t hwirq; - int cpu; - unsigned long hartid; - - if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) { - dev_err(dev, "failed to parse parent for context %d.\n", i); + error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu); + if (error) { + dev_warn(dev, "hwirq for context%d not found\n", i); continue; } =20 @@ -476,7 +500,7 @@ static int plic_probe(struct platform_device *pdev) * Skip contexts other than external interrupts for our * privilege level. */ - if (parent.args[0] !=3D RV_IRQ_EXT) { + if (parent_hwirq !=3D RV_IRQ_EXT) { /* Disable S-mode enable bits if running in M-mode. */ if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { void __iomem *enable_base =3D priv->regs + @@ -489,13 +513,6 @@ static int plic_probe(struct platform_device *pdev) continue; } =20 - error =3D riscv_of_parent_hartid(parent.np, &hartid); - if (error < 0) { - dev_warn(dev, "failed to parse hart ID for context %d.\n", i); - continue; - } - - cpu =3D riscv_hartid_to_cpuid(hartid); if (cpu < 0) { dev_warn(dev, "Invalid cpuid for context %d\n", i); continue; @@ -534,7 +551,7 @@ static int plic_probe(struct platform_device *pdev) handler->enable_save =3D devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32), sizeof(*handler->enable_save), GFP_KERNEL); if (!handler->enable_save) - return -ENOMEM; + goto fail_cleanup_contexts; done: for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -547,7 +564,7 @@ static int plic_probe(struct platform_device *pdev) priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) - return -ENOMEM; + goto fail_cleanup_contexts; =20 /* * We can have multiple PLIC instances so setup cpuhp state @@ -575,6 +592,22 @@ static int plic_probe(struct platform_device *pdev) dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; + +fail_cleanup_contexts: + for (i =3D 0; i < nr_contexts; i++) { + if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu)) + continue; + if (parent_hwirq !=3D RV_IRQ_EXT || cpu < 0) + continue; + + handler =3D per_cpu_ptr(&plic_handlers, cpu); + handler->present =3D false; + handler->hart_base =3D NULL; + handler->enable_base =3D NULL; + handler->enable_save =3D NULL; + handler->priv =3D NULL; + } + return -ENOMEM; } =20 static struct platform_driver plic_driver =3D { --=20 2.34.1