From nobody Thu Dec 18 01:38:08 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA74A249FC; Thu, 22 Feb 2024 08:41:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708591302; cv=none; b=UTtu4eQ5Poj7khLHsKb8JJAo4U7ePdvzcD0nmGh5dxG0pN2ttujF9tZ/7nhB8VxSAiqS3UJVSw6V7h6kXWiFsJaS62486ePx084vFun3/4aq/F+2o8vAWeWj6NzwRw4ywycviUYcxm9nm/MQyMV2cOmCfPihLtbZEbU+IQmc6z8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708591302; c=relaxed/simple; bh=s9wVCn0sjz6CCae2C21O07UOEuCBgVO11hjttgMotig=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NDUfG0tbLY6u4ar1uPr7UlZeeXrWt9XhTvgfLPpLvGkssIAhfGjbbU2mkNBGjbRuGHkeJel1TmF8O6tBmMJuibNP7GDqDLUzRb3DrR8u5XxVo6x9sDXfg6VbFiZSJ0vlL/gpg0jnXVXtz8OqGb841CB4aTXn0K/Cg3GQvlP5+Yk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 41M8e8hD074497; Thu, 22 Feb 2024 16:40:08 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 22 Feb 2024 16:40:05 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Randolph Subject: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Date: Thu, 22 Feb 2024 16:39:39 +0800 Message-ID: <20240222083946.3977135-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> References: <20240222083946.3977135-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 41M8e8hD074497 Content-Type: text/plain; charset="utf-8" Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. The base of custom interrupt number is set to 256. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as a private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node to enable the use of custom local interrupt source. e.g., cpu0: cpu@0 { compatible =3D "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells =3D <0x01>; compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Randolph Reviewed-by: Anup Patel Reviewed-by: Thomas Gleixner --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC Changes v3 -> v4: (Suggested by Thomas [1]) - Add comment to andes irq chip function - Refine code flow to share with generic RISC-V INTC and ACPI - Move Andes specific definitions to include/linux/soc/andes/irq.h Changes v4 -> v5: (Suggested by Thomas) - Fix commit message - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of m= ask - Do not set chip_data to the chip itself with irq_domain_set_info() - Follow reverse fir tree order variable declarations Changes v5 -> v6: - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_= IRQ_PMOVI - Initialize the riscv_intc_* global variables for Andes INTC (Suggested = by Anup) - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bi= t registers (32-bit for RV32) Changes v6 -> v7: - No change Changes v7 -> v8: - Include Reviewed-by tags from Anup Changes v8 -> v9: - No functional change [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3= 657156-1-peterlin@andestech.com/ --- drivers/irqchip/irq-riscv-intc.c | 58 ++++++++++++++++++++++++++++---- include/linux/soc/andes/irq.h | 18 ++++++++++ 2 files changed, 69 insertions(+), 7 deletions(-) create mode 100644 include/linux/soc/andes/irq.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 684875c39728..0cd6b48a5dbf 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; static unsigned int riscv_intc_nr_irqs __ro_after_init =3D BITS_PER_LONG; @@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 +static void andes_intc_irq_mask(struct irq_data *d) +{ + /* + * Andes specific S-mode local interrupt causes (hwirq) + * are defined as (256 + n) and controlled by n-th bit + * of SLIE. + */ + unsigned int mask =3D BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask =3D BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip =3D { .irq_eoi =3D riscv_intc_irq_eoi, }; =20 +static struct irq_chip andes_intc_chip =3D { + .name =3D "RISC-V INTC", + .irq_mask =3D andes_intc_irq_mask, + .irq_unmask =3D andes_intc_irq_unmask, + .irq_eoi =3D riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct irq_chip *chip =3D d->host_data; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, + NULL, NULL); =20 return 0; } @@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } =20 -static int __init riscv_intc_init_common(struct fwnode_handle *fn) +static int __init riscv_intc_init_common(struct fwnode_handle *fn, + struct irq_chip *chip) { int rc; =20 - intc_domain =3D irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); + intc_domain =3D irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc; + struct irq_chip *chip =3D &riscv_intc_chip; unsigned long hartid; + int rc; =20 rc =3D riscv_of_parent_hartid(node, &hartid); if (rc < 0) { @@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node = *node, return 0; } =20 - return riscv_intc_init_common(of_node_to_fwnode(node)); + if (of_device_is_compatible(node, "andestech,cpu-intc")) { + riscv_intc_custom_base =3D ANDES_SLI_CAUSE_BASE; + riscv_intc_custom_nr_irqs =3D ANDES_RV_IRQ_LAST; + chip =3D &andes_intc_chip; + } + + return riscv_intc_init_common(of_node_to_fwnode(node), chip); } =20 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); =20 #ifdef CONFIG_ACPI =20 @@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subta= ble_headers *header, return -ENOMEM; } =20 - return riscv_intc_init_common(fn); + return riscv_intc_init_common(fn, &riscv_intc_chip); } =20 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..edc3182d6e66 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMOVI 18 +#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ --=20 2.34.1