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Signed-off-by: Sam Protsenko --- Changes in v2: - Add "for Exynos850" part to the commit title arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index 2ba67c3d0681..0706c8534ceb 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -93,6 +93,8 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0>; enable-method =3D "psci"; + clocks =3D <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; + clock-names =3D "cluster0_clk"; }; cpu1: cpu@1 { device_type =3D "cpu"; @@ -117,6 +119,8 @@ cpu4: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x100>; enable-method =3D "psci"; + clocks =3D <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; + clock-names =3D "cluster1_clk"; }; cpu5: cpu@101 { device_type =3D "cpu"; @@ -254,6 +258,28 @@ cmu_peri: clock-controller@10030000 { "dout_peri_uart", "dout_peri_ip"; }; =20 + cmu_cpucl1: clock-controller@10800000 { + compatible =3D "samsung,exynos850-cmu-cpucl1"; + reg =3D <0x10800000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL1_DBG>; + clock-names =3D "oscclk", "dout_cpucl1_switch", + "dout_cpucl1_dbg"; + }; + + cmu_cpucl0: clock-controller@10900000 { + compatible =3D "samsung,exynos850-cmu-cpucl0"; + reg =3D <0x10900000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL0_DBG>; + clock-names =3D "oscclk", "dout_cpucl0_switch", + "dout_cpucl0_dbg"; + }; + cmu_g3d: clock-controller@11400000 { compatible =3D "samsung,exynos850-cmu-g3d"; reg =3D <0x11400000 0x8000>; --=20 2.39.2