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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240222-b4-camss-sc8280xp-v6-1-0e0e6a2f8962@linaro.org> References: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-4e032 Add bindings for qcom,sc8280xp-camss in order to support the camera subsystem for sc8280xp as found in the Lenovo x13s Laptop. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/qcom,sc8280xp-camss.yaml | 512 +++++++++++++++++= ++++ 1 file changed, 512 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.ya= ml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml new file mode 100644 index 000000000000..c0bc31709873 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml @@ -0,0 +1,512 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sc8280xp-camss + + clocks: + maxItems: 40 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe3_axi + - const: vfe3 + - const: vfe3_cphy_rx + - const: vfe3_csid + - const: vfe_lite0 + - const: vfe_lite0_cphy_rx + - const: vfe_lite0_csid + - const: vfe_lite1 + - const: vfe_lite1_cphy_rx + - const: vfe_lite1_csid + - const: vfe_lite2 + - const: vfe_lite2_cphy_rx + - const: vfe_lite2_csid + - const: vfe_lite3 + - const: vfe_lite3_cphy_rx + - const: vfe_lite3_csid + - const: gcc_axi_hf + - const: gcc_axi_sf + + interrupts: + maxItems: 20 + + interrupt-names: + items: + - const: csid1_lite + - const: vfe_lite1 + - const: csiphy3 + - const: csid0 + - const: vfe0 + - const: csid1 + - const: vfe1 + - const: csid0_lite + - const: vfe_lite0 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csid2 + - const: vfe2 + - const: csid3_lite + - const: csid2_lite + - const: vfe_lite3 + - const: vfe_lite2 + - const: csid3 + - const: vfe3 + + iommus: + maxItems: 16 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_mnoc + - const: cam_sf_icp_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE3 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed = Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: ife3 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + maxItems: 20 + + reg-names: + items: + - const: csiphy2 + - const: csiphy3 + - const: csiphy0 + - const: csiphy1 + - const: vfe0 + - const: csid0 + - const: vfe1 + - const: csid1 + - const: vfe2 + - const: csid2 + - const: vfe_lite0 + - const: csid0_lite + - const: vfe_lite1 + - const: csid1_lite + - const: vfe_lite2 + - const: csid2_lite + - const: vfe_lite3 + - const: csid3_lite + - const: vfe3 + - const: csid3 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + camss: camss@ac5a000 { + compatible =3D "qcom,sc8280xp-camss"; + + reg =3D <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + + reg-names =3D "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains =3D <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names =3D "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>; + + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe3_axi", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf"; + + + iommus =3D <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC 0 &config_noc SL= AVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_E= BI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt 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<20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 Add a PHY configuration sequence for the sc8280xp which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports two-phase D-PHY mode. Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 85 ++++++++++++++++++= ++++ 1 file changed, 85 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index f50e2235c37f..66ff48aeab64 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -148,6 +148,91 @@ csiphy_reg_t lane_regs_sdm845[5][14] =3D { }, }; =20 +/* GEN2 1.1 2PH */ +static const struct +csiphy_reg_t lane_regs_sc8280xp[5][14] =3D { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240222-b4-camss-sc8280xp-v6-3-0e0e6a2f8962@linaro.org> References: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 Adds a CAMSS SoC identifier for the SC8280XP. Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index a0c2dcc779f0..ac15fe23a702 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -77,6 +77,7 @@ enum camss_version { CAMSS_660, CAMSS_845, CAMSS_8250, + CAMSS_8280XP, }; =20 enum icc_count { --=20 2.43.0 From nobody Mon Feb 9 10:45:36 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E68F4157E72 for ; Thu, 22 Feb 2024 17:17:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708622236; cv=none; b=Ns6LvmBqnq+wpw767b3Oo6o6UjBEImPRyOZ3nKEfSCZBS6l0td7knuBMMW2QMcuA8voHuW2DjaHOmeUjxDXBzeo8EbaYz0zFWCZpGVEDvnvNd6dcRzhCyBVuFM/0DVjQX6bCk7y5g0TMsc8dbeSU93iQwjM8BARJzcqzlbr0M0U= ARC-Message-Signature: i=1; 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Thu, 22 Feb 2024 09:17:11 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 22 Feb 2024 17:17:02 +0000 Subject: [PATCH v6 4/6] media: qcom: camss: Add sc8280xp resources Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240222-b4-camss-sc8280xp-v6-4-0e0e6a2f8962@linaro.org> References: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 This commit describes the hardware layout for the sc8280xp for the following hardware blocks: - 4 x VFE, 4 RDI per VFE - 4 x VFE Lite, 4 RDI per VFE - 4 x CSID - 4 x CSID Lite - 4 x CSI PHY Signed-off-by: Bryan O'Donoghue --- Depends on: Link: https://lore.kernel.org/linux-arm-msm/20240111-linux-next-24-01-02-sc= 8280xp-camss-core-dtsi-v4-2-cdd5c57ff1dc@linaro.org --- drivers/media/platform/qcom/camss/camss.c | 307 ++++++++++++++++++++++++++= ++++ 1 file changed, 307 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 58f4be660290..1923615f0eea 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -941,6 +941,298 @@ static const struct resources_icc icc_res_sm8250[] = =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_sc8280xp[] =3D { + /* CSIPHY0 */ + { + .regulators =3D {}, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY1 */ + { + .regulators =3D {}, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY2 */ + { + .regulators =3D {}, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY3 */ + { + .regulators =3D {}, + .clock =3D { "csiphy3", "csiphy3_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, +}; + +static const struct camss_subdev_resources csid_res_sc8280xp[] =3D { + /* CSID0 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID1 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID2 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID3 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid3" }, + .interrupt =3D { "csid3" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE0 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid0_lite" }, + .interrupt =3D { "csid0_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE1 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid1_lite" }, + .interrupt =3D { "csid1_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE2 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid2_lite" }, + .interrupt =3D { "csid2_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE3 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" }, + .clock_rate =3D { { 400000000, 480000000, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid3_lite" }, + .interrupt =3D { "csid3_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + } +}; + +static const struct camss_subdev_resources vfe_res_sc8280xp[] =3D { + /* VFE0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0= ", "vfe0_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .pd_name =3D "ife0", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe1= ", "vfe1_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .pd_name =3D "ife1", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE2 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe2= ", "vfe2_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .pd_name =3D "ife2", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE3 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe3= ", "vfe3_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe3" }, + .interrupt =3D { "vfe3" }, + .pd_name =3D "ife3", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE_LITE_0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite0" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE_LITE_1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite1" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE_LITE_2 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite2" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000, }, }, + .reg =3D { "vfe_lite2" }, + .interrupt =3D { "vfe_lite2" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE_LITE_3 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite3" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite3" }, + .interrupt =3D { "vfe_lite3" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, +}; + +static const struct resources_icc icc_res_sc8280xp[] =3D { + { + .name =3D "cam_ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "cam_hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "cam_sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "cam_sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1826,12 +2118,27 @@ static const struct camss_resources sm8250_resource= s =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_8250), }; =20 +static const struct camss_resources sc8280xp_resources =3D { + .version =3D CAMSS_8280XP, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_sc8280xp, + .csid_res =3D csid_res_sc8280xp, + .ispif_res =3D NULL, + .vfe_res =3D vfe_res_sc8280xp, + .icc_res =3D icc_res_sc8280xp, + .icc_path_num =3D ARRAY_SIZE(icc_res_sc8280xp), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_sc8280xp), + .csid_num =3D ARRAY_SIZE(csid_res_sc8280xp), + .vfe_num =3D ARRAY_SIZE(vfe_res_sc8280xp), +}; + static const struct of_device_id camss_dt_match[] =3D { { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8996-camss", .data =3D &msm8996_resources }, { .compatible =3D "qcom,sdm660-camss", .data =3D &sdm660_resources }, { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, + { .compatible =3D "qcom,sc8280xp-camss", .data =3D &sc8280xp_resources }, { } }; =20 --=20 2.43.0 From nobody Mon Feb 9 10:45:36 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F0F9157E9B for ; Thu, 22 Feb 2024 17:17:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708622238; 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Thu, 22 Feb 2024 09:17:13 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.68]) by smtp.gmail.com with ESMTPSA id u7-20020a7bc047000000b0040fe4b733f4sm6656512wmc.26.2024.02.22.09.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 09:17:13 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 22 Feb 2024 17:17:03 +0000 Subject: [PATCH v6 5/6] media: qcom: camss: Add sc8280xp support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240222-b4-camss-sc8280xp-v6-5-0e0e6a2f8962@linaro.org> References: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 Add in functional logic throughout the code to support the sc8280xp. Acked-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 23 +++++++++++++++++-= -- drivers/media/platform/qcom/camss/camss-csiphy.c | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 25 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss-video.c | 1 + 4 files changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 66ff48aeab64..df7e93a5a4f6 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -513,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_dev= ice *csiphy, r =3D &lane_regs_sm8250[0][0]; array_size =3D ARRAY_SIZE(lane_regs_sm8250[0]); break; + case CAMSS_8280XP: + r =3D &lane_regs_sc8280xp[0][0]; + array_size =3D ARRAY_SIZE(lane_regs_sc8280xp[0]); + break; default: WARN(1, "unknown cspi version\n"); return; @@ -548,13 +552,26 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cf= g *lane_cfg) return lane_mask; } =20 +static bool csiphy_is_gen2(u32 version) +{ + bool ret =3D false; + + switch (version) { + case CAMSS_845: + case CAMSS_8250: + case CAMSS_8280XP: + ret =3D true; + break; + } + + return ret; +} + static void csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; - bool is_gen2 =3D (csiphy->camss->res->version =3D=3D CAMSS_845 || - csiphy->camss->res->version =3D=3D CAMSS_8250); u8 settle_cnt; u8 val; int i; @@ -576,7 +593,7 @@ static void csiphy_lanes_enable(struct csiphy_device *c= siphy, val =3D 0x00; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); =20 - if (is_gen2) + if (csiphy_is_gen2(csiphy->camss->res->version)) csiphy_gen2_config_lanes(csiphy, settle_cnt); else csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 264c99efeae8..45b3a8e5dea4 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -578,6 +578,7 @@ int msm_csiphy_subdev_init(struct camss *camss, break; case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: csiphy->formats =3D csiphy_formats_sdm845; csiphy->nformats =3D ARRAY_SIZE(csiphy_formats_sdm845); break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 2062be668f49..d875237cf244 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -225,6 +225,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_660: case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1518,6 +1519,7 @@ int msm_vfe_subdev_init(struct camss *camss, struct v= fe_device *vfe, break; case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: l->formats =3D formats_rdi_845; l->nformats =3D ARRAY_SIZE(formats_rdi_845); break; @@ -1595,6 +1597,23 @@ static const struct media_entity_operations vfe_medi= a_ops =3D { .link_validate =3D v4l2_subdev_link_validate, }; =20 +static int vfe_bpl_align(struct vfe_device *vfe) +{ + int ret =3D 8; + + switch (vfe->camss->res->version) { + case CAMSS_845: + case CAMSS_8250: + case CAMSS_8280XP: + ret =3D 16; + break; + default: + break; + } + + return ret; +} + /* * msm_vfe_register_entities - Register subdev node for VFE module * @vfe: VFE device @@ -1661,11 +1680,7 @@ int msm_vfe_register_entities(struct vfe_device *vfe, } =20 video_out->ops =3D &vfe->video_ops; - if (vfe->camss->res->version =3D=3D CAMSS_845 || - vfe->camss->res->version =3D=3D CAMSS_8250) - video_out->bpl_alignment =3D 16; - else - video_out->bpl_alignment =3D 8; + video_out->bpl_alignment =3D vfe_bpl_align(vfe); video_out->line_based =3D 0; if (i =3D=3D VFE_LINE_PIX) { video_out->bpl_alignment =3D 16; diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/medi= a/platform/qcom/camss/camss-video.c index a89da5ef4710..54cd82f74115 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -1028,6 +1028,7 @@ int msm_video_register(struct camss_video *video, str= uct v4l2_device *v4l2_dev, break; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240222-b4-camss-sc8280xp-v6-6-0e0e6a2f8962@linaro.org> References: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> In-Reply-To: <20240222-b4-camss-sc8280xp-v6-0-0e0e6a2f8962@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 vfe-170 and vfe-175 can be supported in the same file with some minimal indirection to differentiate between the silicon versions. sdm845 uses vfe-170, sc8280xp uses vfe-175-200. Lets rename the file to capture its wider scope than vfe-170 only. Acked-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 2= +- drivers/media/platform/qcom/camss/{camss-vfe-170.c =3D> camss-vfe-17x.c} |= 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 4e2222358973..0d4389ab312d 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -14,7 +14,7 @@ qcom-camss-objs +=3D \ camss-vfe-4-1.o \ camss-vfe-4-7.o \ camss-vfe-4-8.o \ - camss-vfe-170.o \ + camss-vfe-17x.o \ camss-vfe-480.o \ camss-vfe-gen1.o \ camss-vfe.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-170.c b/drivers/me= dia/platform/qcom/camss/camss-vfe-17x.c similarity index 100% rename from drivers/media/platform/qcom/camss/camss-vfe-170.c rename to drivers/media/platform/qcom/camss/camss-vfe-17x.c --=20 2.43.0