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charset="utf-8" s4 has been added to the compatible list while converting the Amlogic PWM binding documentation from txt to yaml. However, on the s4, the clock bindings have different meaning compared to the previous SoCs. On the previous SoCs the clock bindings used to describe which input the PWM channel multiplexer should pick among its possible parents. This is very much tied to the driver implementation, instead of describing the HW for what it is. When support for the Amlogic PWM was first added, how to deal with clocks through DT was not as clear as it nowadays. The Linux driver now ignores this DT setting, but still relies on the hard-coded list of clock sources. On the s4, the input multiplexer is gone. The clock bindings actually describe the clock as it exists, not a setting. The property has a different meaning, even if it is still 2 clocks and it would pass the check when support is actually added. Also the s4 cannot work if the clocks are not provided, so the property is no longer optional. Finally, for once it makes sense to see the input as being numbered somehow. No need to bother with clock-names on the s4 type of PWM. Fixes: 43a1c4ff3977 ("dt-bindings: pwm: Convert Amlogic Meson PWM binding") Reviewed-by: Rob Herring Signed-off-by: Jerome Brunet --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 67 ++++++++++++++++--- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Docum= entation/devicetree/bindings/pwm/pwm-amlogic.yaml index 527864a4d855..a1d382aacb82 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -9,9 +9,6 @@ title: Amlogic PWM maintainers: - Heiner Kallweit =20 -allOf: - - $ref: pwm.yaml# - properties: compatible: oneOf: @@ -43,12 +40,8 @@ properties: maxItems: 2 =20 clock-names: - oneOf: - - items: - - enum: [clkin0, clkin1] - - items: - - const: clkin0 - - const: clkin1 + minItems: 1 + maxItems: 2 =20 "#pwm-cells": const: 3 @@ -57,6 +50,55 @@ required: - compatible - reg =20 +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm + - amlogic,meson8b-pwm + - amlogic,meson-gxbb-pwm + - amlogic,meson-gxbb-ao-pwm + - amlogic,meson-axg-ee-pwm + - amlogic,meson-axg-ao-pwm + - amlogic,meson-g12a-ee-pwm + - amlogic,meson-g12a-ao-pwm-ab + - amlogic,meson-g12a-ao-pwm-cd + then: + # Historic bindings tied to the driver implementation + # The clocks provided here are meant to be matched with the input + # known (hard-coded) in the driver and used to select pwm clock + # source. Currently, the linux driver ignores this. + properties: + clock-names: + oneOf: + - items: + - enum: [clkin0, clkin1] + - items: + - const: clkin0 + - const: clkin1 + + # Newer IP block take a single input per channel, instead of 4 inputs + # for both channels + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks + additionalProperties: false =20 examples: @@ -68,3 +110,10 @@ examples: clock-names =3D "clkin0", "clkin1"; #pwm-cells =3D <3>; }; + - | + pwm@1000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x1000 0x10>; + clocks =3D <&pwm_src_a>, <&pwm_src_b>; + #pwm-cells =3D <3>; + }; --=20 2.43.0 From nobody Wed Dec 17 05:51:49 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8E7580028 for ; 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charset="utf-8" The binding that is used up to now describe which input the PWM channel multiplexer should pick among its possible parents, which are hardcoded in the driver. This isn't a good binding in the sense that it should describe hardware but not usage. Add a new binding deprecating the old one that uses clocks in a better way and how clocks are usually used today: The list of clocks describe the inputs of the PWM block as they are realised in hardware. So deprecate the old bindings and introduce a compatible per SoC family to replace these. Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 50 +++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Docum= entation/devicetree/bindings/pwm/pwm-amlogic.yaml index a1d382aacb82..1d71d4f8f328 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -21,23 +21,36 @@ properties: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-s4-pwm + deprecated: true - items: - const: amlogic,meson-gx-pwm - const: amlogic,meson-gxbb-pwm + deprecated: true - items: - const: amlogic,meson-gx-ao-pwm - const: amlogic,meson-gxbb-ao-pwm + deprecated: true - items: - const: amlogic,meson8-pwm - const: amlogic,meson8b-pwm + deprecated: true + - enum: + - amlogic,meson8-pwm-v2 + - amlogic,meson-s4-pwm + - items: + - enum: + - amlogic,meson8b-pwm-v2 + - amlogic,meson-gxbb-pwm-v2 + - amlogic,meson-axg-pwm-v2 + - amlogic,meson-g12-pwm-v2 + - const: amlogic,meson8-pwm-v2 =20 reg: maxItems: 1 =20 clocks: minItems: 1 - maxItems: 2 + maxItems: 4 =20 clock-names: minItems: 1 @@ -68,11 +81,14 @@ allOf: - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd then: - # Historic bindings tied to the driver implementation + # Obsolete historic bindings tied to the driver implementation # The clocks provided here are meant to be matched with the input # known (hard-coded) in the driver and used to select pwm clock # source. Currently, the linux driver ignores this. + # This is kept to maintain ABI backward compatibility. properties: + clocks: + maxItems: 2 clock-names: oneOf: - items: @@ -81,6 +97,27 @@ allOf: - const: clkin0 - const: clkin1 =20 + # Newer binding where clock describe the actual clock inputs of the pwm + # block. These are necessary but some inputs may be grounded. + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm-v2 + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock 0 of the pwm block + - description: input clock 1 of the pwm block + - description: input clock 2 of the pwm block + - description: input clock 3 of the pwm block + clock-names: false + required: + - clocks + # Newer IP block take a single input per channel, instead of 4 inputs # for both channels - if: @@ -110,6 +147,13 @@ examples: clock-names =3D "clkin0", "clkin1"; #pwm-cells =3D <3>; }; + - | + pwm@2000 { + compatible =3D "amlogic,meson8-pwm-v2"; + reg =3D <0x1000 0x10>; + clocks =3D <&xtal>, <0>, <&fdiv4>, <&fdiv5>; + #pwm-cells =3D <3>; + }; - | pwm@1000 { compatible =3D "amlogic,meson-s4-pwm"; --=20 2.43.0 From nobody Wed Dec 17 05:51:49 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 018EA80034 for ; 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charset="utf-8" Meson8 pwm type always has 4 input clocks. Some inputs may be grounded, like in the AO domain of some SoCs. Drop the parent number parameter and make this is constant. This is also done to make the addition of generic meson8 compatible easier. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 53 +++++++++-------------------------------- 1 file changed, 11 insertions(+), 42 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 40a5b64c26f5..a02fdbc61256 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) =20 #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 =20 static struct meson_pwm_channel_data { u8 reg_offset; @@ -97,8 +97,7 @@ struct meson_pwm_channel { }; =20 struct meson_pwm_data { - const char * const *parent_names; - unsigned int num_parents; + const char *const parent_names[MESON_NUM_MUX_PARENTS]; }; =20 struct meson_pwm { @@ -339,62 +338,32 @@ static const struct pwm_ops meson_pwm_ops =3D { .get_state =3D meson_pwm_get_state, }; =20 -static const char * const pwm_meson8b_parent_names[] =3D { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - static const struct meson_pwm_data pwm_meson8b_data =3D { - .parent_names =3D pwm_meson8b_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_meson8b_parent_names), + .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, }; =20 /* * Only the 2 first inputs of the GXBB AO PWMs are valid * The last 2 are grounded */ -static const char * const pwm_gxbb_ao_parent_names[] =3D { - "xtal", "clk81" -}; - static const struct meson_pwm_data pwm_gxbb_ao_data =3D { - .parent_names =3D pwm_gxbb_ao_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_gxbb_ao_parent_names), -}; - -static const char * const pwm_axg_ee_parent_names[] =3D { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" + .parent_names =3D { "xtal", "clk81", NULL, NULL }, }; =20 static const struct meson_pwm_data pwm_axg_ee_data =3D { - .parent_names =3D pwm_axg_ee_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_axg_ee_parent_names), -}; - -static const char * const pwm_axg_ao_parent_names[] =3D { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names =3D { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, }; =20 static const struct meson_pwm_data pwm_axg_ao_data =3D { - .parent_names =3D pwm_axg_ao_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_axg_ao_parent_names), -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] =3D { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names =3D { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, }; =20 static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { - .parent_names =3D pwm_g12a_ao_ab_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] =3D { - "xtal", "g12a_ao_clk81", + .parent_names =3D { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, }; =20 static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { - .parent_names =3D pwm_g12a_ao_cd_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), + .parent_names =3D { "xtal", "g12a_ao_clk81", NULL, NULL }, }; =20 static const struct of_device_id meson_pwm_matches[] =3D { @@ -437,13 +406,13 @@ MODULE_DEVICE_TABLE(of, meson_pwm_matches); static int meson_pwm_init_channels(struct pwm_chip *chip) { struct meson_pwm *meson =3D to_meson_pwm(chip); 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charset="utf-8" Pointers to the internal clock elements of the PWM are useless after probe. There is no need to carry this around in the device data. Rework the clock registration to let devres deal with it Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 73 ++++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index a02fdbc61256..fe61335d87d0 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -85,14 +85,17 @@ static struct meson_pwm_channel_data { } }; =20 +struct meson8b_pwm_clocks { + struct clk_divider div; + struct clk_gate gate; + struct clk_mux mux; +}; + struct meson_pwm_channel { unsigned long rate; unsigned int hi; unsigned int lo; =20 - struct clk_mux mux; - struct clk_divider div; - struct clk_gate gate; struct clk *clk; }; =20 @@ -419,9 +422,14 @@ static int meson_pwm_init_channels(struct pwm_chip *ch= ip) =20 for (i =3D 0; i < chip->npwm; i++) { struct meson_pwm_channel *channel =3D &meson->channels[i]; - struct clk_parent_data div_parent =3D {}, gate_parent =3D {}; + struct clk_parent_data pdata =3D {}; + struct meson8b_pwm_clocks *clks; struct clk_init_data init =3D {}; =20 + clks =3D devm_kzalloc(dev, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); =20 init.name =3D name; @@ -430,16 +438,15 @@ static int meson_pwm_init_channels(struct pwm_chip *c= hip) init.parent_data =3D mux_parent_data; init.num_parents =3D MESON_NUM_MUX_PARENTS; =20 - channel->mux.reg =3D meson->base + REG_MISC_AB; - channel->mux.shift =3D - meson_pwm_per_channel_data[i].clk_sel_shift; - channel->mux.mask =3D MISC_CLK_SEL_MASK; - channel->mux.flags =3D 0; - channel->mux.lock =3D &meson->lock; - channel->mux.table =3D NULL; - channel->mux.hw.init =3D &init; + clks->mux.reg =3D meson->base + REG_MISC_AB; + clks->mux.shift =3D meson_pwm_per_channel_data[i].clk_sel_shift; + clks->mux.mask =3D MISC_CLK_SEL_MASK; + clks->mux.flags =3D 0; + clks->mux.lock =3D &meson->lock; + clks->mux.table =3D NULL; + clks->mux.hw.init =3D &init; =20 - err =3D devm_clk_hw_register(dev, &channel->mux.hw); + err =3D devm_clk_hw_register(dev, &clks->mux.hw); if (err) return dev_err_probe(dev, err, "failed to register %s\n", name); @@ -449,19 +456,19 @@ static int meson_pwm_init_channels(struct pwm_chip *c= hip) init.name =3D name; init.ops =3D &clk_divider_ops; init.flags =3D CLK_SET_RATE_PARENT; - div_parent.index =3D -1; - div_parent.hw =3D &channel->mux.hw; - init.parent_data =3D &div_parent; + pdata.index =3D -1; + pdata.hw =3D &clks->mux.hw; + init.parent_data =3D &pdata; init.num_parents =3D 1; =20 - channel->div.reg =3D meson->base + REG_MISC_AB; - channel->div.shift =3D meson_pwm_per_channel_data[i].clk_div_shift; - channel->div.width =3D MISC_CLK_DIV_WIDTH; - channel->div.hw.init =3D &init; - channel->div.flags =3D 0; - channel->div.lock =3D &meson->lock; + clks->div.reg =3D meson->base + REG_MISC_AB; + clks->div.shift =3D meson_pwm_per_channel_data[i].clk_div_shift; + clks->div.width =3D MISC_CLK_DIV_WIDTH; + clks->div.hw.init =3D &init; + clks->div.flags =3D 0; + clks->div.lock =3D &meson->lock; =20 - err =3D devm_clk_hw_register(dev, &channel->div.hw); + err =3D devm_clk_hw_register(dev, &clks->div.hw); if (err) return dev_err_probe(dev, err, "failed to register %s\n", name); @@ -471,22 +478,22 @@ static int meson_pwm_init_channels(struct pwm_chip *c= hip) init.name =3D name; init.ops =3D &clk_gate_ops; init.flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; - gate_parent.index =3D -1; - gate_parent.hw =3D &channel->div.hw; - init.parent_data =3D &gate_parent; + pdata.index =3D -1; + pdata.hw =3D &clks->div.hw; + init.parent_data =3D &pdata; init.num_parents =3D 1; =20 - channel->gate.reg =3D meson->base + REG_MISC_AB; - channel->gate.bit_idx =3D meson_pwm_per_channel_data[i].clk_en_shift; - channel->gate.hw.init =3D &init; - channel->gate.flags =3D 0; - channel->gate.lock =3D &meson->lock; + clks->gate.reg =3D meson->base + REG_MISC_AB; + clks->gate.bit_idx =3D meson_pwm_per_channel_data[i].clk_en_shift; + clks->gate.hw.init =3D &init; + clks->gate.flags =3D 0; + clks->gate.lock =3D &meson->lock; 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Wed, 21 Feb 2024 07:12:11 -0800 (PST) From: Jerome Brunet To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao Subject: [PATCH v5 5/5] pwm: meson: add generic compatible for meson8 to sm1 Date: Wed, 21 Feb 2024 16:11:51 +0100 Message-ID: <20240221151154.26452-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240221151154.26452-1-jbrunet@baylibre.com> References: <20240221151154.26452-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a new compatible support in the Amlogic PWM driver. The PWM HW is actually the same for all SoCs supported so far. A specific compatible is needed only because the clock sources of the PWMs are hard-coded in the driver. It is better to have the clock source described in DT but this changes the bindings so a new compatible must be introduced. When all supported platform have migrated to the new compatible, support for the legacy ones may be removed from the driver. The addition of this new compatible makes the old ones obsolete, as described in the DT documentation. Adding a callback to setup the clock will also make it easier to add support for the new PWM HW found in a1, s4, c3 and t7 SoC families. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 195 +++++++++++++++++++++++++--------------- 1 file changed, 121 insertions(+), 74 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index fe61335d87d0..90fc7b349723 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -101,6 +101,7 @@ struct meson_pwm_channel { =20 struct meson_pwm_data { const char *const parent_names[MESON_NUM_MUX_PARENTS]; + int (*channels_init)(struct pwm_chip *chip); }; =20 struct meson_pwm { @@ -341,86 +342,16 @@ static const struct pwm_ops meson_pwm_ops =3D { .get_state =3D meson_pwm_get_state, }; =20 -static const struct meson_pwm_data pwm_meson8b_data =3D { - .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, -}; - -/* - * Only the 2 first inputs of the GXBB AO PWMs are valid - * The last 2 are grounded - */ -static const struct meson_pwm_data pwm_gxbb_ao_data =3D { - .parent_names =3D { "xtal", "clk81", NULL, NULL }, -}; - -static const struct meson_pwm_data pwm_axg_ee_data =3D { - .parent_names =3D { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, -}; - -static const struct meson_pwm_data pwm_axg_ao_data =3D { - .parent_names =3D { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, -}; - -static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { - .parent_names =3D { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, -}; - -static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { - .parent_names =3D { "xtal", "g12a_ao_clk81", NULL, NULL }, -}; - -static const struct of_device_id meson_pwm_matches[] =3D { - { - .compatible =3D "amlogic,meson8b-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-gxbb-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-gxbb-ao-pwm", - .data =3D &pwm_gxbb_ao_data - }, - { - .compatible =3D "amlogic,meson-axg-ee-pwm", - .data =3D &pwm_axg_ee_data - }, - { - .compatible =3D "amlogic,meson-axg-ao-pwm", - .data =3D &pwm_axg_ao_data - }, - { - .compatible =3D "amlogic,meson-g12a-ee-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-g12a-ao-pwm-ab", - .data =3D &pwm_g12a_ao_ab_data - }, - { - .compatible =3D "amlogic,meson-g12a-ao-pwm-cd", - .data =3D &pwm_g12a_ao_cd_data - }, - {}, -}; -MODULE_DEVICE_TABLE(of, meson_pwm_matches); - -static int meson_pwm_init_channels(struct pwm_chip *chip) +static int meson_pwm_init_clocks_meson8b(struct pwm_chip *chip, + struct clk_parent_data *mux_parent_data) { struct meson_pwm *meson =3D to_meson_pwm(chip); - struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; struct device *dev =3D pwmchip_parent(chip); unsigned int i; char name[255]; int err; =20 - for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) { - mux_parent_data[i].index =3D -1; - mux_parent_data[i].name =3D meson->data->parent_names[i]; - } - - for (i =3D 0; i < chip->npwm; i++) { + for (i =3D 0; i < MESON_NUM_PWMS; i++) { struct meson_pwm_channel *channel =3D &meson->channels[i]; struct clk_parent_data pdata =3D {}; struct meson8b_pwm_clocks *clks; @@ -502,6 +433,122 @@ static int meson_pwm_init_channels(struct pwm_chip *c= hip) return 0; } =20 +static int meson_pwm_init_channels_meson8b_legacy(struct pwm_chip *chip) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; + struct meson_pwm *meson =3D to_meson_pwm(chip); + int i; + + dev_warn_once(pwmchip_parent(chip), + "using obsolete compatible, please consider updating dt\n"); + + for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) { + mux_parent_data[i].index =3D -1; + mux_parent_data[i].name =3D meson->data->parent_names[i]; + } + + return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); +} + +static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; + int i; + + /* + * NOTE: Instead of relying on the hard coded names in the driver + * as the legacy version, this relies on DT to provide the list of + * clocks. + * For once, using input numbers actually makes more sense than names. + * Also DT requires clock-names to be explicitly ordered, so there is + * no point bothering with clock names in this case. + */ + for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) + mux_parent_data[i].index =3D i; + + return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); +} + +static const struct meson_pwm_data pwm_meson8b_data =3D { + .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +/* + * Only the 2 first inputs of the GXBB AO PWMs are valid + * The last 2 are grounded + */ +static const struct meson_pwm_data pwm_gxbb_ao_data =3D { + .parent_names =3D { "xtal", "clk81", NULL, NULL }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +static const struct meson_pwm_data pwm_axg_ee_data =3D { + .parent_names =3D { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +static const struct meson_pwm_data pwm_axg_ao_data =3D { + .parent_names =3D { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { + .parent_names =3D { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { + .parent_names =3D { "xtal", "g12a_ao_clk81", NULL, NULL }, + .channels_init =3D meson_pwm_init_channels_meson8b_legacy, +}; + +static const struct meson_pwm_data pwm_meson8_v2_data =3D { + .channels_init =3D meson_pwm_init_channels_meson8b_v2, +}; + +static const struct of_device_id meson_pwm_matches[] =3D { + { + .compatible =3D "amlogic,meson8-pwm-v2", + .data =3D &pwm_meson8_v2_data + }, + /* The following compatibles are obsolete */ + { + .compatible =3D "amlogic,meson8b-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-gxbb-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-gxbb-ao-pwm", + .data =3D &pwm_gxbb_ao_data + }, + { + .compatible =3D "amlogic,meson-axg-ee-pwm", + .data =3D &pwm_axg_ee_data + }, + { + .compatible =3D "amlogic,meson-axg-ao-pwm", + .data =3D &pwm_axg_ao_data + }, + { + .compatible =3D "amlogic,meson-g12a-ee-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-g12a-ao-pwm-ab", + .data =3D &pwm_g12a_ao_ab_data + }, + { + .compatible =3D "amlogic,meson-g12a-ao-pwm-cd", + .data =3D &pwm_g12a_ao_cd_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, meson_pwm_matches); + static int meson_pwm_probe(struct platform_device *pdev) { struct pwm_chip *chip; @@ -522,7 +569,7 @@ static int meson_pwm_probe(struct platform_device *pdev) =20 meson->data =3D of_device_get_match_data(&pdev->dev); =20 - err =3D meson_pwm_init_channels(chip); + err =3D meson->data->channels_init(chip); if (err < 0) return err; =20 --=20 2.43.0