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Wed, 21 Feb 2024 09:19:24 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, krebbel@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, sumanthk@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH] perf list: fix short description for some cache events Date: Wed, 21 Feb 2024 10:19:08 +0100 Message-Id: <20240221091908.1759083-1-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _2h7yHayXacwZJsa2sHXP_Fowggij04B X-Proofpoint-ORIG-GUID: _2h7yHayXacwZJsa2sHXP_Fowggij04B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=994 adultscore=0 phishscore=0 spamscore=0 clxscore=1011 mlxscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402210072 Content-Type: text/plain; charset="utf-8" Correct the short description of the following events: DCW_REQ, DCW_REQ_CHIP_HIT, DCW_REQ_DRAWER_HIT, DCW_REQ_IV, DCW_ON_CHIP, DCW_ON_CHIP_IV, DCW_ON_CHIP_CHIP_HIT, DCW_ON_CHIP_DRAWER_HIT, CW_ON_MODULE, DCW_ON_DRAWER, DCW_OFF_DRAWER, IDCW_ON_MODULE_IV, IDCW_ON_MODULE_CHIP_HIT, IDCW_ON_MODULE_DRAWER_HIT, IDCW_ON_DRAWER_IV, IDCW_ON_DRAWER_CHIP_HIT, IDCW_ON_DRAWER_DRAWER_HIT, IDCW_OFF_DRAWER_IV, IDCW_OFF_DRAWER_CHIP_HIT, IDCW_OFF_DRAWER_DRAWER_HIT, ICW_REQ, ICW_REQ_IV, CW_REQ_CHIP_HIT, ICW_REQ_DRAWER_HIT, ICW_ON_CHIP, ICW_ON_CHIP_IV, ICW_ON_CHIP_CHIP_HIT, ICW_ON_CHIP_DRAWER_HIT, ICW_ON_MODULE and ICW_OFF_DRAWER. The second Cache should be L2-Cache. Output before (display diff of the first four events) # perf list -d DCW_REQ [Directory Write Level 1 Data Cache from Cache. Unit: cpum_cf] DCW_REQ_CHIP_HIT [Directory Write Level 1 Data Cache from Cache with Chip HP \ Hit. Unit: cpum_cf] DCW_REQ_DRAWER_HIT [Directory Write Level 1 Data Cache from Cache with Drawer \ HP Hit. Unit: cpum_cf] DCW_REQ_IV [Directory Write Level 1 Data Cache from Cache with Intervention. \ Unit: cpum_cf] Output after: # perf list -d DCW_REQ [Directory Write Level 1 Data Cache from L2-Cache. Unit: cpum_cf] DCW_REQ_CHIP_HIT [Directory Write Level 1 Data Cache from L2-Cache with Chip HP \ Hit. Unit: cpum_cf] DCW_REQ_DRAWER_HIT [Directory Write Level 1 Data Cache from L2-Cache with Drawer \ HP Hit. Unit: cpum_cf] DCW_REQ_IV [Directory Write Level 1 Data Cache from L2-Cache with \ Intervention. Unit: cpum_cf] Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390") Reported-by: Andreas Krebbel Signed-off-by: Thomas Richter Acked-by: Andreas Krebbel Reviewed-by: Ian Rogers --- .../pmu-events/arch/s390/cf_z16/extended.json | 62 +++++++++---------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/p= erf/pmu-events/arch/s390/cf_z16/extended.json index c2b10ec1c6e0..02cce3a629cb 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json @@ -94,77 +94,77 @@ "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "DCW_REQ", - "BriefDescription": "Directory Write Level 1 Data Cache from Cache", + "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from the requestors Level-2 c= ache." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "DCW_REQ_IV", - "BriefDescription": "Directory Write Level 1 Data Cache from Cache with = Intervention", + "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache wi= th Intervention", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from the requestors Level-2 c= ache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "DCW_REQ_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Data Cache from Cache with = Chip HP Hit", + "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache wi= th Chip HP Hit", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from the requestors Level-2 c= ache after using chip level horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "DCW_REQ_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Data Cache from Cache with = Drawer HP Hit", + "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache wi= th Drawer HP Hit", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from the requestors Level-2 c= ache after using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "149", "EventName": "DCW_ON_CHIP", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cac= he", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-= Cache", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Chip Level-2 cache= ." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "DCW_ON_CHIP_IV", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cac= he with Intervention", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-= Cache with Intervention", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Chip Level-2 cache= with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "151", "EventName": "DCW_ON_CHIP_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cac= he with Chip HP Hit", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-= Cache with Chip HP Hit", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Chip Level-2 cache= after using chip level horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "DCW_ON_CHIP_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cac= he with Drawer HP Hit", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-= Cache with Drawer HP Hit", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Chip Level-2 cache= using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "DCW_ON_MODULE", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Module C= ache", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Module L= 2-Cache", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Module Level-2 cac= he." }, { "Unit": "CPU-M-CF", "EventCode": "154", "EventName": "DCW_ON_DRAWER", - "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer C= ache", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L= 2-Cache", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an On-Drawer Level-2 cac= he." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "DCW_OFF_DRAWER", - "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer = Cache", + "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer = L2-Cache", "PublicDescription": "A directory write to the Level-1 Data cache direct= ory where the returned cache line was sourced from an Off-Drawer Level-2 ca= che." }, { @@ -199,140 +199,140 @@ "Unit": "CPU-M-CF", "EventCode": "160", "EventName": "IDCW_ON_MODULE_IV", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory Cache with Intervention", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory L2-Cache with Intervention", "PublicDescription": "A directory write to the Level-1 Data or Level-1 I= nstruction cache directory where the returned cache line was sourced from a= n On-Module Level-2 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "161", "EventName": "IDCW_ON_MODULE_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory Cache with Chip Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory L2-Cache with Chip Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 I= nstruction cache directory where the returned cache line was sourced from a= n On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "162", "EventName": "IDCW_ON_MODULE_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory Cache with Drawer Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Module Memory L2-Cache with Drawer Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 I= nstruction cache directory where the returned cache line was sourced from a= n On-Module Level-2 cache using drawer level horizontal persistence, Drawer= -HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "163", "EventName": "IDCW_ON_DRAWER_IV", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer Cache with Intervention", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer L2-Cache with Intervention", "PublicDescription": "A directory write to the Level-1 Data or Level-1 I= nstruction cache directory where the returned cache line was sourced from a= n On-Drawer Level-2 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "164", "EventName": "IDCW_ON_DRAWER_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer Cache with Chip Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer L2-Cache with Chip Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 i= nstruction cache directory where the returned cache line was sourced from a= n On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP = hit." }, { "Unit": "CPU-M-CF", "EventCode": "165", "EventName": "IDCW_ON_DRAWER_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer Cache with Drawer Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from On-Drawer L2-Cache with Drawer Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 i= nstruction cache directory where the returned cache line was sourced from a= n On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer= -HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "166", "EventName": "IDCW_OFF_DRAWER_IV", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer Cache with Intervention", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer L2-Cache with Intervention", "PublicDescription": "A directory write to the Level-1 Data or Level-1 i= nstruction cache directory where the returned cache line was sourced from a= n Off-Drawer Level-2 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "167", "EventName": "IDCW_OFF_DRAWER_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer Cache with Chip Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer L2-Cache with Chip Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 i= nstruction cache directory where the returned cache line was sourced from a= n Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP= hit." }, { "Unit": "CPU-M-CF", "EventCode": "168", "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer Cache with Drawer Hit", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache = from Off-Drawer L2-Cache with Drawer Hit", "PublicDescription": "A directory write to the Level-1 Data or Level-1 I= nstruction cache directory where the returned cache line was sourced from a= n Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawe= r-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "169", "EventName": "ICW_REQ", - "BriefDescription": "Directory Write Level 1 Instruction Cache from Cach= e", + "BriefDescription": "Directory Write Level 1 Instruction Cache from L2-C= ache", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced the requestors Level-2= cache." }, { "Unit": "CPU-M-CF", "EventCode": "170", "EventName": "ICW_REQ_IV", - "BriefDescription": "Directory Write Level 1 Instruction Cache from Cach= e with Intervention", + "BriefDescription": "Directory Write Level 1 Instruction Cache from L2-C= ache with Intervention", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from the requestors Le= vel-2 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "171", "EventName": "ICW_REQ_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Instruction Cache from Cach= e with Chip HP Hit", + "BriefDescription": "Directory Write Level 1 Instruction Cache from L2-C= ache with Chip HP Hit", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from the requestors Le= vel-2 cache using chip level horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "172", "EventName": "ICW_REQ_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Instruction Cache from Cach= e with Drawer HP Hit", + "BriefDescription": "Directory Write Level 1 Instruction Cache from L2-C= ache with Drawer HP Hit", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from the requestors Le= vel-2 cache using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "173", "EventName": "ICW_ON_CHIP", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip Cache", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip L2-Cache", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from an On-Chip Level-= 2 cache." }, { "Unit": "CPU-M-CF", "EventCode": "174", "EventName": "ICW_ON_CHIP_IV", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip Cache with Intervention", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip L2-Cache with Intervention", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced an On-Chip Level-2 cac= he with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "175", "EventName": "ICW_ON_CHIP_CHIP_HIT", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip Cache with Chip HP Hit", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip L2-Cache with Chip HP Hit", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from an On-Chip Level-= 2 cache using chip level horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "176", "EventName": "ICW_ON_CHIP_DRAWER_HIT", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip Cache with Drawer HP Hit", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-C= hip L2-Cache with Drawer HP Hit", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from an On-Chip level = 2 cache using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "177", "EventName": "ICW_ON_MODULE", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-M= odule Cache", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-M= odule L2-Cache", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced from an On-Module Leve= l-2 cache." }, { "Unit": "CPU-M-CF", "EventCode": "178", "EventName": "ICW_ON_DRAWER", - "BriefDescription": "Directory Write Level 1 Instruction Cache from On-D= rawer Cache", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-D= rawer L2-Cache", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced an On-Drawer Level-2 c= ache." }, { "Unit": "CPU-M-CF", "EventCode": "179", "EventName": "ICW_OFF_DRAWER", - "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-= Drawer Cache", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-= Drawer L2-Cache", "PublicDescription": "A directory write to the Level-1 Instruction cache= directory where the returned cache line was sourced an Off-Drawer Level-2 = cache." }, { --=20 2.43.0