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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id z3-20020a2e7e03000000b002d0f99a7fc4sm1722330ljc.79.2024.02.20.23.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 23:36:08 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Chen-Yu Tsai , Hsin-Yi Wang , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Linus Walleij , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH 3/4] arm64: dts: mediatek: mt7981: add pinctrl Date: Wed, 21 Feb 2024 08:35:23 +0100 Message-Id: <20240221073524.20947-4-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240221073524.20947-1-zajec5@gmail.com> References: <20240221073524.20947-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki MT7981 contains on-SoC PIN controller that is also a GPIO provider. Signed-off-by: Rafa=C5=82 Mi=C5=82ecki --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7981b.dtsi index 4feff3d1c5f4..fdd5c22cfc9c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,6 +86,43 @@ pwm@10048000 { #pwm-cells =3D <2>; }; =20 + pio: pinctrl@11d00000 { + compatible =3D "mediatek,mt7981-pinctrl"; + reg =3D <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names =3D "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + gpio-ranges =3D <&pio 0 0 56>; + gpio-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + + mdio-pins { + mux { + function =3D "eth"; + groups =3D "smi_mdc_mdio"; + }; + }; + + spi0-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + + }; + clock-controller@15000000 { compatible =3D "mediatek,mt7981-ethsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.35.3