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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240221-phy-qualcomm-edp-x1e80100-v4-2-4e5018877bee@linaro.org> References: <20240221-phy-qualcomm-edp-x1e80100-v4-0-4e5018877bee@linaro.org> In-Reply-To: <20240221-phy-qualcomm-edp-x1e80100-v4-0-4e5018877bee@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar , Dmitry Baryshkov , Johan Hovold , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7664; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=pPwy32FBEjCTleZajGGK/3s+6ji3LhjnGXxgS6LGqWU=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBl1SIuYvHk3M3ZKpm8ujeB81I2mPf2Qy7mQFJnY 8bM1O3tIziJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZdUiLgAKCRAbX0TJAJUV Vs8MD/4nJYaeRVV53c2RhV8IGqB/ttsyM6uyaa3I1cRWluzoA3qyCzu6rWTd+oHiXq/1dt8ardR 8kPhfGzIYas17V3at8fhGYP6bK++tEWk5L2einE7uBbzT65bSChrHiG7r78/AIUYCDp1/NPSamZ 2udvyAjh9gxz6Yc8zrrWjgxyWyVSjtYGXpyD3qOxKxjvgpD93kEDcAngO+HD91EJ7UPwuPt9oko 4YWbU89QyXd0oiw8F2pPpxd3MbgCf5/cY/OFonzqn54BB72NFD4fDZh/S5CL/JgTSHdK4+Hwrlc rrKC9fUPs4gsa9+iU5SLux/7tclHjC3p8Xt4zQuMeY0Oz4rXISHdWOcj78JVJohjx8rXEFdJZwc JVTs4tWDiPCVyg5nTpggIZyqkd7aHXA52eTmqtMkaw0QVsNSDZfB7Z1gx++u+IzEjOYjuhHlb+a Um5cBKQZUDyemPEzaOrM8YSa+iWQ1AyD8KFVVWyJK6p7FcFvpTPmRj6aKhEDOKBq7kdYQT2/uA/ pg1c+1CVYPhvvJO/KVuJhWNVXMKopnUaepPWIoPYDb7NUUDC/mVuOoVSwgq5E9Kvn9U0hncZS8T S6kOTUZUXKNolEOPlswjrl8GSizaUtAAnnCMRdVoh6wqGSlN4H5zJCHgrhtHFNEawxxVstCUEOu wkndSeWCprWUUlA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE In order to support different HW versions move everything specific to v4 into so-called version ops. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-edp.c | 183 +++++++++++++++++++++++---------= ---- 1 file changed, 118 insertions(+), 65 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 621d0453bf76..9bbf977c7b4e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -77,9 +77,20 @@ struct qcom_edp_swing_pre_emph_cfg { const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; }; =20 +struct qcom_edp; + +struct phy_ver_ops { + int (*com_power_on)(const struct qcom_edp *edp); + int (*com_resetsm_cntrl)(const struct qcom_edp *edp); + int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp); + int (*com_configure_pll)(const struct qcom_edp *edp); + int (*com_configure_ssc)(const struct qcom_edp *edp); +}; + struct qcom_edp_phy_cfg { bool is_edp; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; + const struct phy_ver_ops *ver_ops; }; =20 struct qcom_edp { @@ -174,18 +185,6 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_ph= y_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 -static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { -}; - -static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, -}; - -static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { - .is_edp =3D true, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, -}; - static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -204,8 +203,9 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - /* Turn on BIAS current for PHY/PLL */ - writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + ret =3D edp->cfg->ver_ops->com_bias_en_clkbuflr(edp); + if (ret) + return ret; =20 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); msleep(20); @@ -312,6 +312,84 @@ static int qcom_edp_phy_configure(struct phy *phy, uni= on phy_configure_opts *opt } =20 static int qcom_edp_configure_ssc(const struct qcom_edp *edp) +{ + return edp->cfg->ver_ops->com_configure_ssc(edp); +} + +static int qcom_edp_configure_pll(const struct qcom_edp *edp) +{ + return edp->cfg->ver_ops->com_configure_pll(edp); +} + +static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long = *pixel_freq) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 vco_div; + + switch (dp_opts->link_rate) { + case 1620: + vco_div =3D 0x1; + *pixel_freq =3D 1620000000UL / 2; + break; + + case 2700: + vco_div =3D 0x1; + *pixel_freq =3D 2700000000UL / 2; + break; + + case 5400: + vco_div =3D 0x2; + *pixel_freq =3D 5400000000UL / 4; + break; + + case 8100: + vco_div =3D 0x0; + *pixel_freq =3D 8100000000UL / 6; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(vco_div, edp->edp + DP_PHY_VCO_DIV); + + return 0; +} + +static int qcom_edp_phy_power_on_v4(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static int qcom_edp_phy_com_resetsm_cntrl_v4(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + +static int qcom_edp_com_configure_ssc_v4(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; u32 step1; @@ -345,7 +423,7 @@ static int qcom_edp_configure_ssc(const struct qcom_edp= *edp) return 0; } =20 -static int qcom_edp_configure_pll(const struct qcom_edp *edp) +static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; u32 div_frac_start2_mode0; @@ -431,41 +509,28 @@ static int qcom_edp_configure_pll(const struct qcom_e= dp *edp) return 0; } =20 -static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long = *pixel_freq) -{ - const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; - u32 vco_div; - - switch (dp_opts->link_rate) { - case 1620: - vco_div =3D 0x1; - *pixel_freq =3D 1620000000UL / 2; - break; - - case 2700: - vco_div =3D 0x1; - *pixel_freq =3D 2700000000UL / 2; - break; - - case 5400: - vco_div =3D 0x2; - *pixel_freq =3D 5400000000UL / 4; - break; - - case 8100: - vco_div =3D 0x0; - *pixel_freq =3D 8100000000UL / 6; - break; +static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v4, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_configure_pll =3D qcom_edp_com_configure_pll_v4, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, +}; =20 - default: - /* Other link rates aren't supported */ - return -EINVAL; - } +static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 - writel(vco_div, edp->edp + DP_PHY_VCO_DIV); +static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 - return 0; -} +static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { + .is_edp =3D true, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 static int qcom_edp_phy_power_on(struct phy *phy) { @@ -473,22 +538,13 @@ static int qcom_edp_phy_power_on(struct phy *phy) u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; u8 ldo_config =3D 0x0; - int timeout; int ret; u32 val; u8 cfg1; =20 - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - edp->edp + DP_PHY_PD_CTL); - writel(0xfc, edp->edp + DP_PHY_MODE); - - timeout =3D readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, - val, val & BIT(7), 5, 200); - if (timeout) - return timeout; - + ret =3D edp->cfg->ver_ops->com_power_on(edp); + if (ret) + return ret; =20 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) ldo_config =3D 0x1; @@ -535,12 +591,9 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x01, edp->edp + DP_PHY_CFG); writel(0x09, edp->edp + DP_PHY_CFG); =20 - writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); - - timeout =3D readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, - val, val & BIT(0), 500, 10000); - if (timeout) - return timeout; + ret =3D edp->cfg->ver_ops->com_resetsm_cntrl(edp); + if (ret) + return ret; =20 writel(0x19, edp->edp + DP_PHY_CFG); writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); --=20 2.34.1