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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Qualcomm X1E80100 platform has multiple PHYs that can work in both eDP or DP mode, so document their compatible. Signed-off-by: Abel Vesa Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 6566353f1a02..4e15d90d08b0 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy - qcom,sc8280xp-edp-phy + - qcom,x1e80100-dp-phy =20 reg: items: --=20 2.34.1 From nobody Fri Dec 19 07:51:02 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E97152E0B for ; Tue, 20 Feb 2024 22:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE In order to support different HW versions move everything specific to v4 into so-called version ops. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-edp.c | 183 +++++++++++++++++++++++---------= ---- 1 file changed, 118 insertions(+), 65 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 621d0453bf76..9bbf977c7b4e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -77,9 +77,20 @@ struct qcom_edp_swing_pre_emph_cfg { const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; }; =20 +struct qcom_edp; + +struct phy_ver_ops { + int (*com_power_on)(const struct qcom_edp *edp); + int (*com_resetsm_cntrl)(const struct qcom_edp *edp); + int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp); + int (*com_configure_pll)(const struct qcom_edp *edp); + int (*com_configure_ssc)(const struct qcom_edp *edp); +}; + struct qcom_edp_phy_cfg { bool is_edp; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; + const struct phy_ver_ops *ver_ops; }; =20 struct qcom_edp { @@ -174,18 +185,6 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_ph= y_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 -static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { -}; - -static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, -}; - -static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { - .is_edp =3D true, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, -}; - static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -204,8 +203,9 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - /* Turn on BIAS current for PHY/PLL */ - writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + ret =3D edp->cfg->ver_ops->com_bias_en_clkbuflr(edp); + if (ret) + return ret; =20 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); msleep(20); @@ -312,6 +312,84 @@ static int qcom_edp_phy_configure(struct phy *phy, uni= on phy_configure_opts *opt } =20 static int qcom_edp_configure_ssc(const struct qcom_edp *edp) +{ + return edp->cfg->ver_ops->com_configure_ssc(edp); +} + +static int qcom_edp_configure_pll(const struct qcom_edp *edp) +{ + return edp->cfg->ver_ops->com_configure_pll(edp); +} + +static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long = *pixel_freq) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 vco_div; + + switch (dp_opts->link_rate) { + case 1620: + vco_div =3D 0x1; + *pixel_freq =3D 1620000000UL / 2; + break; + + case 2700: + vco_div =3D 0x1; + *pixel_freq =3D 2700000000UL / 2; + break; + + case 5400: + vco_div =3D 0x2; + *pixel_freq =3D 5400000000UL / 4; + break; + + case 8100: + vco_div =3D 0x0; + *pixel_freq =3D 8100000000UL / 6; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(vco_div, edp->edp + DP_PHY_VCO_DIV); + + return 0; +} + +static int qcom_edp_phy_power_on_v4(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static int qcom_edp_phy_com_resetsm_cntrl_v4(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + +static int qcom_edp_com_configure_ssc_v4(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; u32 step1; @@ -345,7 +423,7 @@ static int qcom_edp_configure_ssc(const struct qcom_edp= *edp) return 0; } =20 -static int qcom_edp_configure_pll(const struct qcom_edp *edp) +static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; u32 div_frac_start2_mode0; @@ -431,41 +509,28 @@ static int qcom_edp_configure_pll(const struct qcom_e= dp *edp) return 0; } =20 -static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long = *pixel_freq) -{ - const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; - u32 vco_div; - - switch (dp_opts->link_rate) { - case 1620: - vco_div =3D 0x1; - *pixel_freq =3D 1620000000UL / 2; - break; - - case 2700: - vco_div =3D 0x1; - *pixel_freq =3D 2700000000UL / 2; - break; - - case 5400: - vco_div =3D 0x2; - *pixel_freq =3D 5400000000UL / 4; - break; - - case 8100: - vco_div =3D 0x0; - *pixel_freq =3D 8100000000UL / 6; - break; +static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v4, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_configure_pll =3D qcom_edp_com_configure_pll_v4, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, +}; =20 - default: - /* Other link rates aren't supported */ - return -EINVAL; - } +static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 - writel(vco_div, edp->edp + DP_PHY_VCO_DIV); +static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 - return 0; -} +static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { + .is_edp =3D true, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; =20 static int qcom_edp_phy_power_on(struct phy *phy) { @@ -473,22 +538,13 @@ static int qcom_edp_phy_power_on(struct phy *phy) u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; u8 ldo_config =3D 0x0; - int timeout; int ret; u32 val; u8 cfg1; =20 - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - edp->edp + DP_PHY_PD_CTL); - writel(0xfc, edp->edp + DP_PHY_MODE); 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add v6 HW support by implementing the version ops. Add the X1E80100 compatible and match config as it is v6. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-edp.c | 180 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 180 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 9bbf977c7b4e..da2b32fb5b45 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -24,6 +24,7 @@ =20 #include "phy-qcom-qmp-dp-phy.h" #include "phy-qcom-qmp-qserdes-com-v4.h" +#include "phy-qcom-qmp-qserdes-com-v6.h" =20 /* EDP_PHY registers */ #define DP_PHY_CFG 0x0010 @@ -532,6 +533,184 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy= _cfg =3D { .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 +static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static int qcom_edp_phy_com_resetsm_cntrl_v6(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_bias_en_clkbuflr_v6(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); + + return 0; +} + +static int qcom_edp_com_configure_ssc_v6(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 step1; + u32 step2; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 8100: + step1 =3D 0x92; + step2 =3D 0x01; + break; + + case 5400: + step1 =3D 0x18; + step2 =3D 0x02; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1); + writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1); + writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2); + writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0); + + return 0; +} + +static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 div_frac_start2_mode0; + u32 div_frac_start3_mode0; + u32 dec_start_mode0; + u32 lock_cmp1_mode0; + u32 lock_cmp2_mode0; + u32 code1_mode0; + u32 code2_mode0; + u32 hsclk_sel; + + switch (dp_opts->link_rate) { + case 1620: + hsclk_sel =3D 0x5; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x37; + lock_cmp2_mode0 =3D 0x04; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 2700: + hsclk_sel =3D 0x3; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x07; + lock_cmp2_mode0 =3D 0x07; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 5400: + hsclk_sel =3D 0x1; + dec_start_mode0 =3D 0x46; + div_frac_start2_mode0 =3D 0x00; + div_frac_start3_mode0 =3D 0x05; + lock_cmp1_mode0 =3D 0x0f; + lock_cmp2_mode0 =3D 0x0e; + code1_mode0 =3D 0x97; + code2_mode0 =3D 0x10; + break; + + case 8100: + hsclk_sel =3D 0x0; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x17; + lock_cmp2_mode0 =3D 0x15; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL); + writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1); + writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1); + writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO); + writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0); + writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_M= ODE0); + writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_M= ODE0); + writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1); + writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER); + writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL); + writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); + writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN); + writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0); + writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0); + + writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0); + writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0); + + return 0; +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v6, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v6, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v6, + .com_configure_pll =3D qcom_edp_com_configure_pll_v6, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, +}; + +static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { + .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .ver_ops =3D &qcom_edp_phy_ops_v6, +}; + static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -933,6 +1112,7 @@ static const struct of_device_id qcom_edp_phy_match_ta= ble[] =3D { { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &sc8280xp_edp_phy_cf= g, }, + { .compatible =3D "qcom,x1e80100-dp-phy", .data =3D &x1e80100_phy_cfg, }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); --=20 2.34.1