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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the DPU for Qualcomm X1E80100 platform in the SM8650 schema, as they are similar. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index a01d15a03317..c4087cc5abbd 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sm8650-dpu + enum: + - qcom,sm8650-dpu + - qcom,x1e80100-dpu =20 reg: items: --=20 2.34.1 From nobody Wed Dec 24 03:16:13 2025 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28C406BB3C for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the MDSS hardware found on the Qualcomm X1E80100 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 251 +++++++++++++++++= ++++ 1 file changed, 251 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.= yaml new file mode 100644 index 000000000000..3b01a0e47333 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Display MDSS + +maintainers: + - Abel Vesa + +description: + X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-bloc= ks like + DPU display controller, DP interfaces, etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,x1e80100-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,x1e80100-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DI= SPLAY_CFG 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem", "cpu-cfg"; + + resets =3D <&dispcc_core_bcr>; + + power-domains =3D <&dispcc_gdsc>; + + clocks =3D <&dispcc_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&dispcc_mdp_clk>; + clock-names =3D "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,x1e80100-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc_mdp_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible =3D "qcom,x1e80100-dp"; + reg =3D <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>; + clock-names =3D "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_L= INK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 =3D <&mdss_dp0_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&mdss_intf0_out>; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add support for MDSS on X1E80100. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/gpu/drm/msm/msm_mdss.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 65657230bbff..fab6ad4e5107 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -687,6 +687,18 @@ static const struct msm_mdss_data sm8550_data =3D { .macrotile_mode =3D 1, .reg_bus_bw =3D 57000, }; + +static const struct msm_mdss_data x1e80100_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 1, + /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ + .highest_bank_bit =3D 3, + .macrotile_mode =3D 1, + /* TODO: Add reg_bus_bw with real value */ +}; + static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,mdss" }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, @@ -707,6 +719,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, + { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, {} }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-x1e80100-display-v4-4-971afd9de861@linaro.org> References: <20240220-x1e80100-display-v4-0-971afd9de861@linaro.org> In-Reply-To: <20240220-x1e80100-display-v4-0-971afd9de861@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Rob Herring Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15961; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=SKOBWkgo8TbNdEGb/LuCepLY+kF5J6loUVonl91LkZg=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBl1LQnz9TqFMz72J3AeRbHEzDCz7M4CXfpPOdTY JbGDJk0a5WJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZdS0JwAKCRAbX0TJAJUV VjvYD/9epTHolMvT8DVfXUaRAO1PwcwKhjM3rJ1psxNtNDFGRYMeXDb6l1kxEDCKyLkHTXhXtqh 9YQbMv/kdJqW1F4/at0hCVcj1g8kGrX/Yg/W4F75NsoNlrd4fhLQBT2fol47dOctPm90qkl/l9v 92F7HPAl4uftsSqHftu+L+tg5LH6FfSjhxlcub2SgDrZ6/mAraGaeJxtS8Gt4Q6cpPnJEpRl7PD UDaDxfwuTlEkGNj0/T/JDgNB3QxPrvipPFm+nJgl/W/Yl1mJr3BDQc9J7oywiz63qi7EowVKBxe OvTrD7RVL3u4eORnpvEA34Agk8jnPRevHM2f9kUXaE+/hRW1ikDBhswGxd5b3Rz79fMhPe04+dq NxDRnHDU+TDMilkKEGMtdXmWg1kn4gkCp92mujn71OwikzF5rAAbO5KjgoOv47/ycYx61VHAxgY kOr4E3xehkUe4JB7HSzmBEEXOg2DnHmqpOYqxiJHQLrmeHUZ4f3pi792X3Q1K6sDuflVJDNCfWL qS0wT57lDe7JycjdxhdJSxLiTx4vQEFNX+qLagLkF3bKvAupe5QEtxaob8/Z3lJm+fnOS1A+QQC fNUcjDgqNdxCoBHmnIF93PeyWv3vHyuzYzn8YL6RSWPf32UbYe3eZ+mThu5y3Xw57+b1hnBfPzl WuB7fmhF3e0/9WA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add definitions for the display hardware used on the Qualcomm X1E80100 platform. Co-developed-by: Abhinav Kumar Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 449 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 453 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h new file mode 100644 index 000000000000..9a9f7092c526 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_9_2_X1E80100_H +#define _DPU_9_2_X1E80100_H + +static const struct dpu_caps x1e80100_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 5120, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg x1e80100_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg x1e80100_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_3, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_3, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_3, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_3, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg x1e80100_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, +}; + +static const struct dpu_dspp_cfg x1e80100_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg x1e80100_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x66000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x66400, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, +}; + +static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x8, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x8, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x8, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x66700, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg x1e80100_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SM8250_MASK, + .format_list =3D wb2_formats_rgb, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_intf_cfg x1e80100_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name =3D "intf_4", .id =3D INTF_4, + .base =3D 0x38000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + }, { + .name =3D "intf_5", .id =3D INTF_5, + .base =3D 0x39000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_3, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + }, +}; + +static const struct dpu_perf_cfg x1e80100_perf_data =3D { + .max_bw_low =3D 13600000, + .max_bw_high =3D 18200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version x1e80100_mdss_ver =3D { + .core_major_ver =3D 9, + .core_minor_ver =3D 2, +}; + +const struct dpu_mdss_cfg dpu_x1e80100_cfg =3D { + .mdss_ver =3D &x1e80100_mdss_ver, + .caps =3D &x1e80100_dpu_caps, + .mdp =3D &x1e80100_mdp, + .ctl_count =3D ARRAY_SIZE(x1e80100_ctl), + .ctl =3D x1e80100_ctl, + .sspp_count =3D ARRAY_SIZE(x1e80100_sspp), + .sspp =3D x1e80100_sspp, + .mixer_count =3D ARRAY_SIZE(x1e80100_lm), + .mixer =3D x1e80100_lm, + .dspp_count =3D ARRAY_SIZE(x1e80100_dspp), + .dspp =3D x1e80100_dspp, + .pingpong_count =3D ARRAY_SIZE(x1e80100_pp), + .pingpong =3D x1e80100_pp, + .dsc_count =3D ARRAY_SIZE(x1e80100_dsc), + .dsc =3D x1e80100_dsc, + .merge_3d_count =3D ARRAY_SIZE(x1e80100_merge_3d), + .merge_3d =3D x1e80100_merge_3d, + .wb_count =3D ARRAY_SIZE(x1e80100_wb), + .wb =3D x1e80100_wb, + .intf_count =3D ARRAY_SIZE(x1e80100_intf), + .intf =3D x1e80100_intf, + .vbif_count =3D ARRAY_SIZE(sm8550_vbif), + .vbif =3D sm8550_vbif, + .perf =3D &x1e80100_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index ccbee0f40ad7..f2b6eac7601d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -705,4 +705,6 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_9_0_sm8550.h" =20 +#include "catalog/dpu_9_2_x1e80100.h" + #include "catalog/dpu_10_0_sm8650.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index a54c135e3147..d1aef778340b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -851,5 +851,6 @@ extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 2af62d8fa9a7..d6412395bacc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1398,6 +1398,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8450-dpu", .data =3D &dpu_sm8450_cfg, }, { .compatible =3D "qcom,sm8550-dpu", .data =3D &dpu_sm8550_cfg, }, { .compatible =3D "qcom,sm8650-dpu", .data =3D &dpu_sm8650_cfg, }, + { .compatible =3D "qcom,x1e80100-dpu", .data =3D &dpu_x1e80100_cfg, }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); --=20 2.34.1