From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3459822D795; Wed, 30 Apr 2025 09:27:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; cv=none; b=UISZeAmnF5nxQ5DMxJ/kBDmPmy+CH46+Cv8+Eb7F5dP56T80Iq8ycWumkI9IOeWDFNfKAq66f4NS3qf9AgWtom9mhXZOlewLgQDXP9ph/srMcxc6Kqflm30lYl5uAMb9/PN56qEJICC1m469/pKv/BFCvDMhlkvXjXQhFuJQCCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; c=relaxed/simple; bh=LhjzYTVbEmq8KN4Wgt9+26RV811P+w/qGS6tZIYmKcg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=igAR7NtLAOfVCrh0W22g+yN18H2e+fXjsXic28fKlvPV9UpvAqtK9MMHlPImWhpjz0Uxp9/rNabQxJLLg+MrDzjULNhTDUZypeGRVlcbjtRWoLSaOcIQlfTSgWRUtrOjxB/fcx4c0QzjNYovg4z0/V3jbF2rCGOKuL31E5Q0fYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nFYwVgzv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nFYwVgzv" Received: by smtp.kernel.org (Postfix) with ESMTPS id B26E6C4CEEA; Wed, 30 Apr 2025 09:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746005264; bh=LhjzYTVbEmq8KN4Wgt9+26RV811P+w/qGS6tZIYmKcg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nFYwVgzvxpJM64jAQ8yaHa54+UUO/ooHqpjStYq7wOFcAdB9LT0rBMu1thar7b+kO WDNMOJ4t+7io+PpQqH0uJM406g7vGNhdTNWMWQ5S61rr06y3AvnTLikRI1Ipjj7x4F EOe1Yv8WisBxXiZthWR9GXFFaokT+zwySMyOKUKeJT7RHIjpeS0qnAzaXEiE3CzRDl G9NguwJakyTpo2YGLfud4d9GZWEgMEyLrSyU2uxE131ZhZXvIiWKV/NseZuG/cMN0J 1MoXHqZUAwhUJuyt5/5Q9sUVLEdRPQnWDlrIMcU1P1Ac4YdykzGGwQ2y8xoMjj9USf 0NOQ904GvwPbw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A204AC3ABA9; Wed, 30 Apr 2025 09:27:44 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:50 +0200 Subject: [PATCH v6 01/13] Documentation: admin-guide: media: add rockchip camera interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-1-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=7140; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=lgdL2UknSGLykwZSJIFR4WTJWtgKAnMYvukM6U3+Y4Q=; b=C/k8awCE9Zax42BQaKv/HrCTRwdROkU9HCGFEInBwM1NhCEX/oZoapaOb95p8dujUjN1sUQqZ evrkHhp6G/MA1n+e+WLuN1jU9x+bEMngHEvpFoMn3VG727n2+XyQKdr X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add a document that describes the different variants of the Rockchip Camera Interface (CIF), their hardware layout, as well as their representation in the media controller centric rkcif device driver, which is located under drivers/media/platform/rockchip/rkcif. Signed-off-by: Michael Riesch Reviewed-by: Heiko Stuebner --- .../admin-guide/media/rkcif-rk3568-vicap.dot | 21 ++++++ Documentation/admin-guide/media/rkcif.rst | 83 ++++++++++++++++++= ++++ Documentation/admin-guide/media/v4l-drivers.rst | 1 + MAINTAINERS | 7 ++ 4 files changed, 112 insertions(+) diff --git a/Documentation/admin-guide/media/rkcif-rk3568-vicap.dot b/Docum= entation/admin-guide/media/rkcif-rk3568-vicap.dot new file mode 100644 index 000000000000..4cc6963e681e --- /dev/null +++ b/Documentation/admin-guide/media/rkcif-rk3568-vicap.dot @@ -0,0 +1,21 @@ +digraph board { + rankdir=3DTB + n00000001 [label=3D"{{ 0} | rkcif-dvp0\n/dev/v4l-subdev0 | = { 1}}", shape=3DMrecord, style=3Dfilled, fillcolor=3Dgreen] + n00000001:port1 -> n00000004 + n00000004 [label=3D"rkcif-dvp0-id0\n/dev/video0", shape=3Dbox, sty= le=3Dfilled, fillcolor=3Dyellow] + n0000000d [label=3D"{{} | it6801 2-0048\n/dev/v4l-subdev1 | { 0}}", shape=3DMrecord, style=3Dfilled, fillcolor=3Dgreen] + n0000000d:port0 -> n00000001:port0 + n00000011 [label=3D"{{} | imx415 4-001a\n/dev/v4l-subdev4 | { 0}}", shape=3DMrecord, style=3Dfilled, fillcolor=3Dgreen] + n00000011:port1 -> n00000014 + n00000014 [label=3D"{{ 0} | rockchip-mipi-csi fdfb0000.csi\= n/dev/v4l-subdev3 | { 1}}", shape=3DMrecord, style=3Dfilled, fillcol= or=3Dgreen] + n00000014:port1 -> n0000001d + n0000001d [label=3D"{{ 0} | rkcif-mipi0\n/dev/v4l-subdev2 |= { 1}}", shape=3DMrecord, style=3Dfilled, fillcolor=3Dgreen] + n0000001d:port1 -> n00000021 + n0000001d:port1 -> n00000022 + n0000001d:port1 -> n00000023 + n0000001d:port1 -> n00000024 + n00000021 [label=3D"rkcif-mipi0-id0\n/dev/video1", shape=3Dbox, st= yle=3Dfilled, fillcolor=3Dyellow] + n00000022 [label=3D"rkcif-mipi0-id1\n/dev/video2", shape=3Dbox, st= yle=3Dfilled, fillcolor=3Dyellow] + n00000023 [label=3D"rkcif-mipi0-id2\n/dev/video3", shape=3Dbox, st= yle=3Dfilled, fillcolor=3Dyellow] + n00000024 [label=3D"rkcif-mipi0-id3\n/dev/video4", shape=3Dbox, st= yle=3Dfilled, fillcolor=3Dyellow] +} diff --git a/Documentation/admin-guide/media/rkcif.rst b/Documentation/admi= n-guide/media/rkcif.rst new file mode 100644 index 000000000000..f35f644a54a0 --- /dev/null +++ b/Documentation/admin-guide/media/rkcif.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Rockchip Camera Interface (CIF) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The Rockchip Camera Interface (CIF) is featured in many Rockchip SoCs in +different variants. +The different variants are combinations of common building blocks, such as + +* INTERFACE blocks of different types, namely + + * the Digital Video Port (DVP, a parallel data interface) + * the interface block for the MIPI CSI-2 receiver + +* CROP units + +* MIPI CSI-2 receiver (not available on all variants): This unit is referr= ed + to as MIPI CSI HOST in the Rockchip documentation. + Technically, it is a separate hardware block, but it is strongly coupled= to + the CIF and therefore included here. + +* MUX units (not available on all variants) that pass the video data to an + image signal processor (ISP) + +* SCALE units (not available on all variants) + +* DMA engines that transfer video data into system memory using a + double-buffering mechanism called ping-pong mode + +* Support for four streams per INTERFACE block (not available on all + variants), e.g., for MIPI CSI-2 Virtual Channels (VCs) + +This document describes the different variants of the CIF, their hardware +layout, as well as their representation in the media controller centric rk= cif +device driver, which is located under drivers/media/platform/rockchip/rkci= f. + +Variants +=3D=3D=3D=3D=3D=3D=3D=3D + +Rockchip PX30 Video Input Processor (VIP) +----------------------------------------- + +The PX30 Video Input Processor (VIP) features a digital video port that ac= cepts +parallel video data or BT.656. +Since these protocols do not feature multiple streams, the VIP has one DMA +engine that transfers the input video data into system memory. + +The rkcif driver represents this hardware variant by exposing one V4L2 sub= device +(the DVP INTERFACE/CROP block) and one V4L2 device (the DVP DMA engine). + +Rockchip RK3568 Video Capture (VICAP) +------------------------------------- + +The RK3568 Video Capture (VICAP) unit features a digital video port and a = MIPI +CSI-2 receiver that can receive video data independently. +The DVP accepts parallel video data, BT.656 and BT.1120. +Since the BT.1120 protocol may feature more than one stream, the RK3568 VI= CAP +DVP features four DMA engines that can capture different streams. +Similarly, the RK3568 VICAP MIPI CSI-2 receiver features four DMA engines = to +handle different Virtual Channels (VCs). + +The rkcif driver represents this hardware variant by exposing up to three = V4L2 +subdevices: + +* rkcif-dvp0: INTERFACE/CROP block for the DVP +* rockchip-mipi-csi fdfb0000.csi: MIPI CSI-2 receiver +* rkcif-mipi0: INTERFACE/CROP block for the MIPI CSI-2 receiver + +and up to five V4L2 devices: + +* rkcif-dvp0-id0: The support for multiple streams on the DVP is not yet + implemented, as it is hard to find test hardware. Thus, this video device + represents the first DMA engine of the RK3568 DVP. +* rkcif-mipi0-id[0...3]: The four DMA engines of the RK3568 MIPI CSI-2 + receiver. Each DMA engine can capture a certain MIPI CSI-2 Virtual Chann= el. + +.. kernel-figure:: rkcif-rk3568-vicap.dot + :alt: Topology of the RK3568 Video Capture (VICAP) unit + :align: center diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentatio= n/admin-guide/media/v4l-drivers.rst index e8761561b2fe..f6497541d55b 100644 --- a/Documentation/admin-guide/media/v4l-drivers.rst +++ b/Documentation/admin-guide/media/v4l-drivers.rst @@ -24,6 +24,7 @@ Video4Linux (V4L) driver-specific documentation qcom_camss raspberrypi-pisp-be rcar-fdp1 + rkcif rkisp1 raspberrypi-rp1-cfe saa7134 diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..d1184d571b64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20859,6 +20859,13 @@ S: Maintained F: Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml F: drivers/net/can/rockchip/ =20 +ROCKCHIP CAMERA INTERFACE (RKCIF) DRIVER +M: Mehdi Djait +M: Michael Riesch +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/admin-guide/media/rkcif* + ROCKCHIP CRYPTO DRIVERS M: Corentin Labbe L: linux-crypto@vger.kernel.org --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345F7231839; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-2-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=1010; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=Uz74OJ3MrVHSpMmLIY3bphZ6CO+aAi3TjYd87Bbmoq0=; b=3pezi/eZthEJyZ3VA7cSIbm+xnaBjXhjmQJV5Ym/Xtp5znFGFi9MK4ISbR+kN20nMFWeOfLvW 2w334p2hO0UCtFjNGpw8qa//2wB22i6hvrTR0dWWTqgYmTshGpbmenG X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add defines for the pixel clock sampling modes (rising edge, falling edge, dual edge) for parallel video interfaces. This avoids hardcoded constants in device tree sources. Acked-by: Rob Herring Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- include/dt-bindings/media/video-interfaces.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bind= ings/media/video-interfaces.h index 88b9d05d8075..0b19c9b2e627 100644 --- a/include/dt-bindings/media/video-interfaces.h +++ b/include/dt-bindings/media/video-interfaces.h @@ -20,4 +20,8 @@ #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4 #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5 =20 +#define MEDIA_PCLK_SAMPLE_FALLING_EDGE 0 +#define MEDIA_PCLK_SAMPLE_RISING_EDGE 1 +#define MEDIA_PCLK_SAMPLE_DUAL_EDGE 2 + #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A77F23183D; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; cv=none; b=eQtyn3Q/yoJL7QQE3ARl9xtAhQsbeAdEaTXWyMYwzIUTwElPwkghjdTYLqlGu/+zDsM3J/6rhASruKr7s3eG6dU+shQjX6+QyW7MHC+yTqD7qILkD5DmAJ0ACT4VI8rUnorTcbwxdT1cJoH8ZRzN5jvL2e5N42E57dLtmvqYg9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; c=relaxed/simple; bh=DekLBelCh6fLAeleQSyfWpljaHPSqs05c9605Bt+B5k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Oih0XUceB6l9vNGZqQR1XA7s83KGJzME2ZBiFgHPCVB7Tix7ErbdqSAS5JoJNQe4mahfndLmvYeCso7tQpNksgZiOMVlJi+2R3tY96C2WYt19KBTOUPne7q/wKgPmb1VpejxOxYr/Fs3uLYVu1G0W2Jgyc0xEltLqHKUYydOhKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oCGhQ6gV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oCGhQ6gV" Received: by smtp.kernel.org (Postfix) with ESMTPS id CC95CC4CEF1; Wed, 30 Apr 2025 09:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746005264; bh=DekLBelCh6fLAeleQSyfWpljaHPSqs05c9605Bt+B5k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oCGhQ6gVP5hc8DhJIp8zKFEfGxtpoi9a9alhaihVZorygW0/bvO9E7VVv0m7BbDuW KVTsCHPYRTkvADrYdT3hGfGPLhe0PVZMCmKUpNv6MkooYrUq/g5diRRvI3TBIaC9A3 DeX/IvzUJoL1B7Py7mB+fvws52tdfut+b2+gYSPYuJRn2rBbMql3p+BU7UbyHdsdKG a2+8QFdiewmlFhWHyUEBp2KCMOP/I8iGrInKdML620ahj4yZMdnes1Pg1ZhCduFyQ6 qi5tz8IH2d1XYwL+tSvHPQVFQUvDhEzngTlCoJDBapURI3YLBrha25qG54ipRBzsVL d8DXkFilI3MEw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD7FC369DC; Wed, 30 Apr 2025 09:27:44 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:52 +0200 Subject: [PATCH v6 03/13] media: dt-bindings: add rockchip px30 vip Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-3-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch , Mehdi Djait X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=4307; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=cdNCDiikxDg+nnKV95yyl25F/lYucHK1XCALzDX+u5s=; b=wpGgnLYFoRqLm1BJIu89K6+u9ZCNwTzn2Ei+s50y/YkQknyZvR4AE91tG5rQ3Si1sK/fh3l/m XE1Ceml9OH8CNx/IVLynD6NQHpI5FQ96AsDNoaQX7oviSDp4Q56Y2NP X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Mehdi Djait Add documentation for the Rockchip PX30 Video Input Processor (VIP). Signed-off-by: Mehdi Djait [revised description] Reviewed-by: Rob Herring (Arm) Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- .../bindings/media/rockchip,px30-vip.yaml | 122 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 123 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml= b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml new file mode 100644 index 000000000000..9f7ab6965636 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Video Input Processor (VIP) + +maintainers: + - Mehdi Djait + - Michael Riesch + +description: + The Rockchip PX30 Video Input Processor (VIP) receives the data from a c= amera + sensor or CCIR656 encoder and transfers it into system main memory by AX= I bus. + +properties: + compatible: + const: rockchip,px30-vip + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port on the parallel interface + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [5, 6] + + required: + - bus-type + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + video-capture@ff490000 { + compatible =3D "rockchip,px30-vip"; + reg =3D <0x0 0xff490000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names =3D "aclk", "hclk", "pclk"; + power-domains =3D <&power PX30_PD_VI>; + resets =3D <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CI= F_PCLKIN>; + reset-names =3D "axi", "ahb", "pclkin"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + cif_in: endpoint { + remote-endpoint =3D <&tw9900_out>; + bus-type =3D ; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d1184d571b64..2e24210f4e60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20865,6 +20865,7 @@ M: Michael Riesch L: linux-media@vger.kernel.org S: Maintained F: Documentation/admin-guide/media/rkcif* +F: Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml =20 ROCKCHIP CRYPTO DRIVERS M: Corentin Labbe --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A71B1E991A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-4-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=6124; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=vaCGwkc/S8lWY9FNh8xSi1TWIebW3O3ma9bvl/LOpIU=; b=9CteTKYyZi0E/DfaeA1fIpojYgbD4uFqMoANOwyduGrg1TITh0Mi1ZyMd2V2a5LJUb5cbMaES qikGY32HS+8AKKnUyKepzcURV7XZSwSPPxUfWtWCWhPfpql0pgR7AZS X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add documentation for the Rockchip RK3568 Video Capture (VICAP) unit. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/rockchip,rk3568-vicap.yaml | 170 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 171 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.= yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml new file mode 100644 index 000000000000..99861d236f5e --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3568-vicap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Video Capture (VICAP) + +maintainers: + - Michael Riesch + +description: + The Rockchip RK3568 Video Capture (VICAP) block features a digital video + port (DVP, a parallel video interface) and a MIPI CSI-2 port. It receives + the data from camera sensors, video decoders, or other companion ICs and + transfers it into system main memory by AXI bus. + +properties: + compatible: + const: rockchip,rk3568-vicap + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: DCLK + - description: ICLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: dclk + - const: iclk + + iommus: + maxItems: 1 + + resets: + items: + - description: ARST + - description: HRST + - description: DRST + - description: PRST + - description: IRST + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: prst + - const: irst + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to general register file used for video input blo= ck control. + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: The digital video port (DVP, a parallel video interfa= ce). + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [5, 6] + + rockchip,dvp-clk-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + minimum: 0 + maximum: 127 + description: + Delay the DVP path clock input to align the sampling pha= se, + only valid in dual edge sampling mode. Delay is zero by + default and can be adjusted optionally. + + required: + - bus-type + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + vicap: video-capture@fdfe0000 { + compatible =3D "rockchip,rk3568-vicap"; + reg =3D <0x0 0xfdfe0000 0x0 0x200>; + interrupts =3D ; + assigned-clocks =3D <&cru DCLK_VICAP>; + assigned-clock-rates =3D <300000000>; + clocks =3D <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names =3D "aclk", "hclk", "dclk", "iclk"; + iommus =3D <&vicap_mmu>; + power-domains =3D <&power RK3568_PD_VI>; + resets =3D <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names =3D "arst", "hrst", "drst", "prst", "irst"; + rockchip,grf =3D <&grf>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vicap_dvp: port@0 { + reg =3D <0>; + + vicap_dvp_input: endpoint { + bus-type =3D ; + bus-width =3D <16>; + pclk-sample =3D ; + remote-endpoint =3D <&it6801_output>; + }; + }; + + vicap_mipi: port@1 { + reg =3D <1>; + + vicap_mipi_input: endpoint { + remote-endpoint =3D <&csi_output>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2e24210f4e60..99a29a905cae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20866,6 +20866,7 @@ L: linux-media@vger.kernel.org S: Maintained F: Documentation/admin-guide/media/rkcif* F: Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml +F: Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml =20 ROCKCHIP CRYPTO DRIVERS M: Corentin Labbe --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ECFF235057; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-5-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=3953; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=zyT1eAXmxyVat8/AdLWgnEsFTp49/649sAMCNnvHFJA=; b=lSPcQ5F+ADQ+I0JoC0QUxxfd7DUIWunIiXoeBrjt8CsuYgGbjlB9lV92PyUN5JhKCvtJc0aIm tODuULO0vltARJ6S7UXggy37MqNRxlUNZ+VmgPI4yGR1W9lxEIdU9W2 X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add documentation for the Rockchip RK3568 MIPI CSI-2 Receiver. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- .../bindings/media/rockchip,rk3568-mipi-csi.yaml | 113 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 114 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-c= si.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.= yaml new file mode 100644 index 000000000000..d5004cb288dd --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 MIPI CSI-2 Receiver + +maintainers: + - Michael Riesch + +description: + The Rockchip RK3568 MIPI CSI-2 Receiver is a CSI-2 bridge with one input= port + and one output port. It receives the data with the help of an external + MIPI PHY (C-PHY or D-PHY) and passes it to the Rockchip RK3568 Video Cap= ture + (VICAP) block. + +properties: + compatible: + const: rockchip,rk3568-mipi-csi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + description: MIPI C-PHY or D-PHY. + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port node. Connect to e.g., a MIPI CSI-2 image = sensor. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [1, 4] + + required: + - bus-type + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port connected to a RK3568 VICAP port. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - phys + - phy-names + - ports + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + csi: csi@fdfb0000 { + compatible =3D "rockchip,rk3568-mipi-csi"; + reg =3D <0x0 0xfdfb0000 0x0 0x10000>; + clocks =3D <&cru PCLK_CSI2HOST1>; + phys =3D <&csi_dphy>; + power-domains =3D <&power RK3568_PD_VI>; + resets =3D <&cru SRST_P_CSI2HOST1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi_in: port@0 { + reg =3D <0>; + }; + + csi_out: port@1 { + reg =3D <1>; + + csi_output: endpoint { + remote-endpoint =3D <&vicap_mipi_input>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 99a29a905cae..e993ef6f8771 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20866,6 +20866,7 @@ L: linux-media@vger.kernel.org S: Maintained F: Documentation/admin-guide/media/rkcif* F: Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml +F: Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml F: Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml =20 ROCKCHIP CRYPTO DRIVERS --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ED90235060; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-6-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch , Mehdi Djait X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=85287; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=FJIzHgJ25jfQbKlht/zjyW4HEmHjgOONutTdDb4siEE=; b=2Z1Dy3BZJpF5e+TFXdJUbUXImhbfbVgIMpisNf6r7DPQNYpehMaSqFImYeF7HJ5KtRj0Q/xbn AF1kwBjCXI5DV/lHDWkaIgpmmV8qTumIbfn9gB/Z3HjDdAdIbHLzJW+ X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip Camera Interface (CIF) is featured in many Rockchip SoCs in different variations. For example, the PX30 Video Input Processor (VIP) is able to receive video data via the Digital Video Port (DVP, a parallel data interface) and transfer it into system memory using a double-buffering mechanism called ping-pong mode. The RK3568 Video Capture (VICAP) unit, on the other hand, features a DVP and a MIPI CSI-2 receiver that can receive video data independently (both using the ping-pong scheme). The different variants may have additional features, such as scaling and/or cropping. Finally, the RK3588 VICAP unit constitutes an essential piece of the camera interface with one DVP, six MIPI CSI-2 receivers, scale/crop units, and a data path multiplexer (to scaler units, to ISP, ...). Add a basic media controller centric V4L2 driver for the Rockchip CIF with - support for the PX30 VIP - support for the RK3568 VICAP DVP - abstraction for the ping-pong scheme to allow for future extensions - abstraction for the INTERFACE and CROP parts to allow for future extensions [PX30 VIP support v1-v5] Co-developed-by: Maxime Chevallier Signed-off-by: Maxime Chevallier [PX30 VIP support v6-v13] Co-developed-by: Mehdi Djait Signed-off-by: Mehdi Djait [added RK3568 VICAP DVP support] [refactored to media controller centric driver, added mplane support] Co-developed-by: Gerald Loacker Signed-off-by: Gerald Loacker Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- MAINTAINERS | 1 + drivers/media/platform/rockchip/Kconfig | 1 + drivers/media/platform/rockchip/Makefile | 1 + drivers/media/platform/rockchip/rkcif/Kconfig | 15 + drivers/media/platform/rockchip/rkcif/Makefile | 7 + .../platform/rockchip/rkcif/rkcif-capture-dvp.c | 858 +++++++++++++++++= ++++ .../platform/rockchip/rkcif/rkcif-capture-dvp.h | 24 + .../platform/rockchip/rkcif/rkcif-capture-mipi.c | 27 + .../platform/rockchip/rkcif/rkcif-capture-mipi.h | 20 + .../media/platform/rockchip/rkcif/rkcif-common.h | 220 ++++++ drivers/media/platform/rockchip/rkcif/rkcif-dev.c | 299 +++++++ .../platform/rockchip/rkcif/rkcif-interface.c | 423 ++++++++++ .../platform/rockchip/rkcif/rkcif-interface.h | 30 + drivers/media/platform/rockchip/rkcif/rkcif-regs.h | 132 ++++ .../media/platform/rockchip/rkcif/rkcif-stream.c | 622 +++++++++++++++ .../media/platform/rockchip/rkcif/rkcif-stream.h | 31 + 16 files changed, 2711 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e993ef6f8771..1f67709c2184 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20868,6 +20868,7 @@ F: Documentation/admin-guide/media/rkcif* F: Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml F: Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml F: Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml +F: drivers/media/platform/rockchip/rkcif/ =20 ROCKCHIP CRYPTO DRIVERS M: Corentin Labbe diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platfo= rm/rockchip/Kconfig index b41d3960c1b4..549f4e9f443e 100644 --- a/drivers/media/platform/rockchip/Kconfig +++ b/drivers/media/platform/rockchip/Kconfig @@ -3,4 +3,5 @@ comment "Rockchip media platform drivers" =20 source "drivers/media/platform/rockchip/rga/Kconfig" +source "drivers/media/platform/rockchip/rkcif/Kconfig" source "drivers/media/platform/rockchip/rkisp1/Kconfig" diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platf= orm/rockchip/Makefile index 4f782b876ac9..6aba32c8830c 100644 --- a/drivers/media/platform/rockchip/Makefile +++ b/drivers/media/platform/rockchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D rga/ +obj-y +=3D rkcif/ obj-y +=3D rkisp1/ diff --git a/drivers/media/platform/rockchip/rkcif/Kconfig b/drivers/media/= platform/rockchip/rkcif/Kconfig new file mode 100644 index 000000000000..f53e79a4b42d --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/Kconfig @@ -0,0 +1,15 @@ +config VIDEO_ROCKCHIP_CIF + tristate "Rockchip Camera Interface (CIF)" + depends on VIDEO_DEV + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on V4L_PLATFORM_DRIVERS + depends on PM && COMMON_CLK + select MEDIA_CONTROLLER + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + help + This is a driver for Rockchip Camera Interface (CIF). It is featured + in many Rockchips SoCs in different variations, such as the PX30 + Video Input Processor (VIP, one Digital Video Port (DVP)) or the + RK3568 Video Capture (VICAP, one DVP, one MIPI CSI-2 receiver) unit. diff --git a/drivers/media/platform/rockchip/rkcif/Makefile b/drivers/media= /platform/rockchip/rkcif/Makefile new file mode 100644 index 000000000000..818424972c7b --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_ROCKCHIP_CIF) +=3D rockchip-cif.o +rockchip-cif-objs +=3D rkcif-dev.o \ + rkcif-capture-dvp.o \ + rkcif-capture-mipi.o \ + rkcif-interface.o \ + rkcif-stream.o diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c b/dr= ivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c new file mode 100644 index 000000000000..b1370ee4d900 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c @@ -0,0 +1,858 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2020 Maxime Chevallier + * Copyright (C) 2023 Mehdi Djait + * Copyright (C) 2025 Michael Riesch + */ + +#include +#include +#include +#include + +#include "rkcif-capture-dvp.h" +#include "rkcif-common.h" +#include "rkcif-interface.h" +#include "rkcif-regs.h" +#include "rkcif-stream.h" + +static const struct rkcif_output_fmt dvp_out_fmts[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_NV16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_422 | + RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV16M, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_422 | + RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV61, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_422 | + RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV61M, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_422 | + RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV12, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_420 | + RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV12M, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_420 | + RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV21, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_420 | + RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV21M, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_OUTPUT_420 | + RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU, + .cplanes =3D 2, + }, + { + .fourcc =3D V4L2_PIX_FMT_RGB24, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_RGB565, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_BGR666, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB8, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG8, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG8, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR8, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB10, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG10, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG10, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR10, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB12, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG12, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG12, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR12, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR16, + .cplanes =3D 1, + }, + { + .fourcc =3D V4L2_PIX_FMT_Y16, + .cplanes =3D 1, + }, +}; + +static const struct rkcif_input_fmt px30_dvp_in_fmts[] =3D { + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_RGB888_1X24, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + } +}; + +const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_match_data =3D { + .in_fmts =3D px30_dvp_in_fmts, + .in_fmts_num =3D ARRAY_SIZE(px30_dvp_in_fmts), + .out_fmts =3D dvp_out_fmts, + .out_fmts_num =3D ARRAY_SIZE(dvp_out_fmts), + .has_scaler =3D true, + .regs =3D { + [RKCIF_DVP_CTRL] =3D 0x00, + [RKCIF_DVP_INTEN] =3D 0x04, + [RKCIF_DVP_INTSTAT] =3D 0x08, + [RKCIF_DVP_FOR] =3D 0x0c, + [RKCIF_DVP_LINE_NUM_ADDR] =3D 0x10, + [RKCIF_DVP_FRM0_ADDR_Y] =3D 0x14, + [RKCIF_DVP_FRM0_ADDR_UV] =3D 0x18, + [RKCIF_DVP_FRM1_ADDR_Y] =3D 0x1c, + [RKCIF_DVP_FRM1_ADDR_UV] =3D 0x20, + [RKCIF_DVP_VIR_LINE_WIDTH] =3D 0x24, + [RKCIF_DVP_SET_SIZE] =3D 0x28, + [RKCIF_DVP_SCL_CTRL] =3D 0x48, + [RKCIF_DVP_FRAME_STATUS] =3D 0x60, + [RKCIF_DVP_LAST_LINE] =3D 0x68, + [RKCIF_DVP_LAST_PIX] =3D 0x6c, + }, +}; + +static const struct rkcif_input_fmt rk3568_dvp_in_fmts[] =3D { + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_RGB888_1X24, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, +}; + +static void rk3568_dvp_grf_setup(struct rkcif_device *rkcif) +{ + u32 con1 =3D RK3568_GRF_WRITE_ENABLE(RK3568_GRF_VI_CON1_CIF_DATAPATH | + RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM); + + if (!rkcif->grf) + return; + + con1 |=3D rkcif->interfaces[RKCIF_DVP].dvp.dvp_clk_delay & + RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM; + + if (rkcif->interfaces[RKCIF_DVP].vep.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_DUALEDGE) + con1 |=3D RK3568_GRF_VI_CON1_CIF_DATAPATH; + + regmap_write(rkcif->grf, RK3568_GRF_VI_CON1, con1); +} + +const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data =3D { + .in_fmts =3D rk3568_dvp_in_fmts, + .in_fmts_num =3D ARRAY_SIZE(rk3568_dvp_in_fmts), + .out_fmts =3D dvp_out_fmts, + .out_fmts_num =3D ARRAY_SIZE(dvp_out_fmts), + .setup =3D rk3568_dvp_grf_setup, + .has_scaler =3D false, + .regs =3D { + [RKCIF_DVP_CTRL] =3D 0x00, + [RKCIF_DVP_INTEN] =3D 0x04, + [RKCIF_DVP_INTSTAT] =3D 0x08, + [RKCIF_DVP_FOR] =3D 0x0c, + [RKCIF_DVP_LINE_NUM_ADDR] =3D 0x2c, + [RKCIF_DVP_FRM0_ADDR_Y] =3D 0x14, + [RKCIF_DVP_FRM0_ADDR_UV] =3D 0x18, + [RKCIF_DVP_FRM1_ADDR_Y] =3D 0x1c, + [RKCIF_DVP_FRM1_ADDR_UV] =3D 0x20, + [RKCIF_DVP_VIR_LINE_WIDTH] =3D 0x24, + [RKCIF_DVP_SET_SIZE] =3D 0x28, + [RKCIF_DVP_CROP] =3D 0x34, + [RKCIF_DVP_FRAME_STATUS] =3D 0x3c, + [RKCIF_DVP_LAST_LINE] =3D 0x44, + [RKCIF_DVP_LAST_PIX] =3D 0x48, + }, +}; + +static inline unsigned int cif_dvp_get_addr(struct rkcif_device *rkcif, + unsigned int index) +{ + if (WARN_ON_ONCE(index >=3D RKCIF_DVP_REGISTER_MAX)) + return RKCIF_REGISTER_NOTSUPPORTED; + + return rkcif->match_data->dvp->regs[index]; +} + +static inline __maybe_unused void cif_dvp_write(struct rkcif_device *rkcif, + unsigned int index, u32 val) +{ + unsigned int addr =3D cif_dvp_get_addr(rkcif, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return; + + writel(val, rkcif->base_addr + addr); +} + +static inline __maybe_unused u32 cif_dvp_read(struct rkcif_device *rkcif, + unsigned int index) +{ + unsigned int addr =3D cif_dvp_get_addr(rkcif, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return 0; + + return readl(rkcif->base_addr + addr); +} + +static void cif_dvp_queue_buffer(struct rkcif_stream *stream, + unsigned int index) +{ + struct rkcif_device *rkcif =3D stream->rkcif; + struct rkcif_buffer *buffer =3D stream->buffers[index]; + u32 frm_addr_y, frm_addr_uv; + + frm_addr_y =3D index ? RKCIF_DVP_FRM1_ADDR_Y : RKCIF_DVP_FRM0_ADDR_Y; + frm_addr_uv =3D index ? RKCIF_DVP_FRM1_ADDR_UV : RKCIF_DVP_FRM0_ADDR_UV; + + cif_dvp_write(rkcif, frm_addr_y, buffer->buff_addr[RKCIF_PLANE_Y]); + cif_dvp_write(rkcif, frm_addr_uv, buffer->buff_addr[RKCIF_PLANE_UV]); +} + +static int cif_dvp_start_streaming(struct rkcif_stream *stream) +{ + struct rkcif_device *rkcif =3D stream->rkcif; + struct rkcif_interface *interface =3D stream->interface; + struct v4l2_mbus_config_parallel *parallel; + struct v4l2_mbus_framefmt *source_fmt; + struct v4l2_subdev_state *state; + const struct rkcif_input_fmt *active_in_fmt; + const struct rkcif_output_fmt *active_out_fmt; + u32 val =3D 0; + int ret =3D -EINVAL; + + state =3D v4l2_subdev_lock_and_get_active_state(&interface->sd); + source_fmt =3D v4l2_subdev_state_get_format(state, RKCIF_IF_PAD_SRC, + stream->id); + if (!source_fmt) + goto out; + + active_in_fmt =3D rkcif_interface_find_input_fmt(interface, false, + source_fmt->code); + active_out_fmt =3D rkcif_stream_find_output_fmt(stream, false, + stream->pix.pixelformat); + if (!active_in_fmt || !active_out_fmt) + goto out; + + parallel =3D &interface->vep.bus.parallel; + if (parallel->bus_width =3D=3D 16 && + (parallel->flags & V4L2_MBUS_PCLK_SAMPLE_DUALEDGE)) + val |=3D RKCIF_FORMAT_BT1120_CLOCK_DOUBLE_EDGES; + val |=3D active_in_fmt->dvp_fmt_val; + val |=3D active_out_fmt->dvp_fmt_val; + cif_dvp_write(rkcif, RKCIF_DVP_FOR, val); + + val =3D stream->pix.width; + if (active_in_fmt->fmt_type =3D=3D RKCIF_FMT_TYPE_RAW) + val =3D stream->pix.width * 2; + cif_dvp_write(rkcif, RKCIF_DVP_VIR_LINE_WIDTH, val); + + val =3D RKCIF_XY_COORD(stream->pix.width, stream->pix.height); + cif_dvp_write(rkcif, RKCIF_DVP_SET_SIZE, val); + + cif_dvp_write(rkcif, RKCIF_DVP_FRAME_STATUS, RKCIF_FRAME_STAT_CLS); + cif_dvp_write(rkcif, RKCIF_DVP_INTSTAT, RKCIF_INTSTAT_CLS); + if (rkcif->match_data->dvp->has_scaler) { + val =3D active_in_fmt->fmt_type =3D=3D RKCIF_FMT_TYPE_YUV ? + RKCIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS : + RKCIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS; + cif_dvp_write(rkcif, RKCIF_DVP_SCL_CTRL, val); + } + + cif_dvp_write(rkcif, RKCIF_DVP_INTEN, + RKCIF_INTEN_FRAME_END_EN | + RKCIF_INTEN_PST_INF_FRAME_END_EN); + + cif_dvp_write(rkcif, RKCIF_DVP_CTRL, + RKCIF_CTRL_AXI_BURST_16 | RKCIF_CTRL_MODE_PINGPONG | + RKCIF_CTRL_ENABLE_CAPTURE); + + ret =3D 0; + +out: + v4l2_subdev_unlock_state(state); + return ret; +} + +static void cif_dvp_stop_streaming(struct rkcif_stream *stream) +{ + struct rkcif_device *rkcif =3D stream->rkcif; + u32 val; + + val =3D cif_dvp_read(rkcif, RKCIF_DVP_CTRL); + cif_dvp_write(rkcif, RKCIF_DVP_CTRL, + val & (~RKCIF_CTRL_ENABLE_CAPTURE)); + cif_dvp_write(rkcif, RKCIF_DVP_INTEN, 0x0); + cif_dvp_write(rkcif, RKCIF_DVP_INTSTAT, 0x3ff); + cif_dvp_write(rkcif, RKCIF_DVP_FRAME_STATUS, 0x0); + + stream->stopping =3D false; +} + +static void cif_dvp_reset_stream(struct rkcif_device *rkcif) +{ + u32 ctl =3D cif_dvp_read(rkcif, RKCIF_DVP_CTRL); + + cif_dvp_write(rkcif, RKCIF_DVP_CTRL, + ctl & (~RKCIF_CTRL_ENABLE_CAPTURE)); + cif_dvp_write(rkcif, RKCIF_DVP_CTRL, ctl | RKCIF_CTRL_ENABLE_CAPTURE); +} + +static void rkcif_dvp_set_crop(struct rkcif_stream *stream, u16 left, u16 = top) +{ + struct rkcif_device *rkcif =3D stream->rkcif; + u32 val; + + val =3D RKCIF_XY_COORD(left, top); + cif_dvp_write(rkcif, RKCIF_DVP_CROP, val); +} + +irqreturn_t rkcif_dvp_isr(int irq, void *ctx) +{ + struct device *dev =3D ctx; + struct rkcif_device *rkcif =3D dev_get_drvdata(dev); + struct rkcif_stream *stream; + u32 intstat, lastline, lastpix, cif_frmst; + irqreturn_t ret =3D IRQ_NONE; + + if (!rkcif->match_data->dvp) + return ret; + + intstat =3D cif_dvp_read(rkcif, RKCIF_DVP_INTSTAT); + cif_frmst =3D cif_dvp_read(rkcif, RKCIF_DVP_FRAME_STATUS); + lastline =3D RKCIF_FETCH_Y(cif_dvp_read(rkcif, RKCIF_DVP_LAST_LINE)); + lastpix =3D RKCIF_FETCH_Y(cif_dvp_read(rkcif, RKCIF_DVP_LAST_PIX)); + + if (intstat & RKCIF_INTSTAT_FRAME_END) { + cif_dvp_write(rkcif, RKCIF_DVP_INTSTAT, + RKCIF_INTSTAT_FRAME_END_CLR | + RKCIF_INTSTAT_LINE_END_CLR); + + stream =3D &rkcif->interfaces[RKCIF_DVP].streams[RKCIF_ID0]; + + if (stream->stopping) { + cif_dvp_stop_streaming(stream); + wake_up(&stream->wq_stopped); + return IRQ_HANDLED; + } + + if (lastline !=3D stream->pix.height) { + v4l2_err(&rkcif->v4l2_dev, + "bad frame, irq:%#x frmst:%#x size:%dx%d\n", + intstat, cif_frmst, lastpix, lastline); + + cif_dvp_reset_stream(rkcif); + } + + rkcif_stream_pingpong(stream); + + ret =3D IRQ_HANDLED; + } + + return ret; +} + +int rkcif_dvp_register(struct rkcif_device *rkcif) +{ + struct rkcif_interface *interface; + int ret, i; + + if (!rkcif->match_data->dvp) + return 0; + + interface =3D &rkcif->interfaces[RKCIF_DVP]; + interface->index =3D RKCIF_DVP; + interface->type =3D RKCIF_IF_DVP; + interface->in_fmts =3D rkcif->match_data->dvp->in_fmts; + interface->in_fmts_num =3D rkcif->match_data->dvp->in_fmts_num; + interface->set_crop =3D rkcif_dvp_set_crop; + ret =3D rkcif_interface_register(rkcif, interface); + if (ret) + return 0; + + if (rkcif->match_data->dvp->setup) + rkcif->match_data->dvp->setup(rkcif); + + interface->streams_num =3D rkcif->match_data->dvp->has_ids ? 4 : 1; + for (i =3D 0; i < interface->streams_num; i++) { + struct rkcif_stream *stream =3D &interface->streams[i]; + + stream->id =3D i; + stream->interface =3D interface; + stream->out_fmts =3D rkcif->match_data->dvp->out_fmts; + stream->out_fmts_num =3D rkcif->match_data->dvp->out_fmts_num; + stream->queue_buffer =3D cif_dvp_queue_buffer; + stream->start_streaming =3D cif_dvp_start_streaming; + stream->stop_streaming =3D cif_dvp_stop_streaming; + + ret =3D rkcif_stream_register(rkcif, stream); + if (ret) + goto err_streams_unregister; + } + return 0; + +err_streams_unregister: + for (; i >=3D 0; i--) + rkcif_stream_unregister(&interface->streams[i]); + rkcif_interface_unregister(interface); + + return ret; +} + +void rkcif_dvp_unregister(struct rkcif_device *rkcif) +{ + struct rkcif_interface *interface; + int i; + + if (!rkcif->match_data->dvp) + return; + + interface =3D &rkcif->interfaces[RKCIF_DVP]; + + for (i =3D 0; i < interface->streams_num; i++) + rkcif_stream_unregister(&interface->streams[i]); + rkcif_interface_unregister(interface); +} diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h b/dr= ivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h new file mode 100644 index 000000000000..4bd72d41ec2f --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2023 Mehdi Djait + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_CAPTURE_DVP_H +#define _RKCIF_CAPTURE_DVP_H + +#include "rkcif-common.h" + +extern const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_match_data; +extern const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data; + +int rkcif_dvp_register(struct rkcif_device *rkcif); + +void rkcif_dvp_unregister(struct rkcif_device *rkcif); + +irqreturn_t rkcif_dvp_isr(int irq, void *ctx); + +#endif diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c b/d= rivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c new file mode 100644 index 000000000000..0c3f7b8cfa18 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2025 Michael Riesch + */ + +#include "rkcif-capture-mipi.h" +#include "rkcif-common.h" +#include "rkcif-stream.h" + +irqreturn_t rkcif_mipi_isr(int irq, void *ctx) +{ + irqreturn_t ret =3D IRQ_NONE; + + return ret; +} + +int rkcif_mipi_register(struct rkcif_device *rkcif) +{ + return 0; +} + +void rkcif_mipi_unregister(struct rkcif_device *rkcif) +{ +} diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h b/d= rivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h new file mode 100644 index 000000000000..ee1a50a59505 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_CAPTURE_MIPI_H +#define _RKCIF_CAPTURE_MIPI_H + +#include "rkcif-common.h" + +int rkcif_mipi_register(struct rkcif_device *rkcif); + +void rkcif_mipi_unregister(struct rkcif_device *rkcif); + +irqreturn_t rkcif_mipi_isr(int irq, void *ctx); + +#endif diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-common.h b/drivers= /media/platform/rockchip/rkcif/rkcif-common.h new file mode 100644 index 000000000000..62fb3580eec5 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-common.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2023 Mehdi Djait + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_COMMON_H +#define _RKCIF_COMMON_H + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rkcif-regs.h" + +#define RKCIF_DRIVER_NAME "rockchip-cif" +#define RKCIF_CLK_MAX 4 + +enum rkcif_format_type { + RKCIF_FMT_TYPE_INVALID, + RKCIF_FMT_TYPE_YUV, + RKCIF_FMT_TYPE_RAW, +}; + +enum rkcif_id_index { + RKCIF_ID0, + RKCIF_ID1, + RKCIF_ID2, + RKCIF_ID3, + RKCIF_ID_MAX +}; + +enum rkcif_interface_index { + RKCIF_DVP, + RKCIF_MIPI_BASE, + RKCIF_MIPI1 =3D RKCIF_MIPI_BASE, + RKCIF_MIPI2, + RKCIF_MIPI3, + RKCIF_MIPI4, + RKCIF_MIPI5, + RKCIF_MIPI6, + RKCIF_MIPI_MAX =3D RKCIF_MIPI6, + RKCIF_IF_MAX =3D RKCIF_MIPI_MAX +}; + +enum rkcif_interface_pad_index { + RKCIF_IF_PAD_SINK, + RKCIF_IF_PAD_SRC, + RKCIF_IF_PAD_MAX +}; + +enum rkcif_interface_status { + RKCIF_IF_INACTIVE, + RKCIF_IF_ACTIVE, +}; + +enum rkcif_interface_type { + RKCIF_IF_INVALID, + RKCIF_IF_DVP, + RKCIF_IF_MIPI, +}; + +enum rkcif_plane_index { + RKCIF_PLANE_Y, + RKCIF_PLANE_UV, + RKCIF_PLANE_MAX +}; + +struct rkcif_input_fmt { + u32 mbus_code; + + enum rkcif_format_type fmt_type; + enum v4l2_field field; + + union { + u32 dvp_fmt_val; + }; +}; + +struct rkcif_output_fmt { + u32 fourcc; + u32 mbus_code; + u8 cplanes; + + union { + u32 dvp_fmt_val; + }; +}; + +struct rkcif_buffer { + struct vb2_v4l2_buffer vb; + struct list_head queue; + dma_addr_t buff_addr[VIDEO_MAX_PLANES]; + bool is_dummy; +}; + +struct rkcif_dummy_buffer { + struct rkcif_buffer buffer; + void *vaddr; + u32 size; +}; + +struct rkcif_interface; + +struct rkcif_remote { + struct v4l2_async_connection async_conn; + struct v4l2_subdev *sd; + + struct rkcif_interface *interface; +}; + +struct rkcif_stream { + enum rkcif_id_index id; + struct rkcif_device *rkcif; + struct rkcif_interface *interface; + const struct rkcif_output_fmt *out_fmts; + unsigned int out_fmts_num; + + /* in ping-pong mode, two buffers can be provided to the HW */ + struct rkcif_buffer *buffers[2]; + int frame_idx; + int frame_phase; + + /* in case of no available buffer, HW can write to the dummy buffer */ + struct rkcif_dummy_buffer dummy; + + bool stopping; + wait_queue_head_t wq_stopped; + + /* queue of available buffers plus spinlock that protects it */ + spinlock_t driver_queue_lock; + struct list_head driver_queue; + + /* lock used by the V4L2 core */ + struct mutex vlock; + + struct media_pad pad; + struct media_pipeline pipeline; + struct v4l2_pix_format_mplane pix; + struct vb2_queue buf_queue; + struct video_device vdev; + + void (*queue_buffer)(struct rkcif_stream *stream, unsigned int index); + int (*start_streaming)(struct rkcif_stream *stream); + void (*stop_streaming)(struct rkcif_stream *stream); +}; + +struct rkcif_dvp { + u32 dvp_clk_delay; +}; + +struct rkcif_interface { + enum rkcif_interface_type type; + enum rkcif_interface_status status; + enum rkcif_interface_index index; + struct rkcif_device *rkcif; + struct rkcif_remote *remote; + struct rkcif_stream streams[RKCIF_ID_MAX]; + unsigned int streams_num; + const struct rkcif_input_fmt *in_fmts; + unsigned int in_fmts_num; + + struct media_pad pads[RKCIF_IF_PAD_MAX]; + struct v4l2_fwnode_endpoint vep; + struct v4l2_subdev sd; + + union { + struct rkcif_dvp dvp; + }; + + void (*set_crop)(struct rkcif_stream *stream, u16 left, u16 top); +}; + +struct rkcif_dvp_match_data { + const struct rkcif_input_fmt *in_fmts; + unsigned int in_fmts_num; + const struct rkcif_output_fmt *out_fmts; + unsigned int out_fmts_num; + void (*setup)(struct rkcif_device *rkcif); + bool has_scaler; + bool has_ids; + unsigned int regs[RKCIF_DVP_REGISTER_MAX]; +}; + +struct rkcif_match_data { + const char *const *clks; + unsigned int clks_num; + const struct rkcif_dvp_match_data *dvp; +}; + +struct rkcif_device { + struct device *dev; + + const struct rkcif_match_data *match_data; + struct clk_bulk_data clks[RKCIF_CLK_MAX]; + unsigned int clks_num; + struct regmap *grf; + struct reset_control *reset; + void __iomem *base_addr; + + struct rkcif_interface interfaces[RKCIF_IF_MAX]; + + struct media_device media_dev; + struct v4l2_device v4l2_dev; + struct v4l2_async_notifier notifier; +}; + +#endif diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-dev.c b/drivers/me= dia/platform/rockchip/rkcif/rkcif-dev.c new file mode 100644 index 000000000000..2dcd35771fc9 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-dev.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2020 Maxime Chevallier + * Copyright (C) 2023 Mehdi Djait + * Copyright (C) 2025 Michael Riesch + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "rkcif-capture-dvp.h" +#include "rkcif-capture-mipi.h" +#include "rkcif-common.h" + +static const char *const px30_vip_clks[] =3D { + "aclk", + "hclk", + "pclk", +}; + +static const struct rkcif_match_data px30_vip_match_data =3D { + .clks =3D px30_vip_clks, + .clks_num =3D ARRAY_SIZE(px30_vip_clks), + .dvp =3D &rkcif_px30_vip_dvp_match_data, +}; + +static const char *const rk3568_vicap_clks[] =3D { + "aclk", + "hclk", + "dclk", + "iclk", +}; + +static const struct rkcif_match_data rk3568_vicap_match_data =3D { + .clks =3D rk3568_vicap_clks, + .clks_num =3D ARRAY_SIZE(rk3568_vicap_clks), + .dvp =3D &rkcif_rk3568_vicap_dvp_match_data, +}; + +static const struct of_device_id rkcif_plat_of_match[] =3D { + { + .compatible =3D "rockchip,px30-vip", + .data =3D &px30_vip_match_data, + }, + { + .compatible =3D "rockchip,rk3568-vicap", + .data =3D &rk3568_vicap_match_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, rkcif_plat_of_match); + +static int rkcif_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_connection *asd) +{ + struct rkcif_device *rkcif =3D + container_of(notifier, struct rkcif_device, notifier); + struct rkcif_remote *remote =3D + container_of(asd, struct rkcif_remote, async_conn); + struct media_pad *sink_pad =3D + &remote->interface->pads[RKCIF_IF_PAD_SINK]; + int ret; + + ret =3D v4l2_create_fwnode_links_to_pad(sd, sink_pad, + MEDIA_LNK_FL_ENABLED); + if (ret) { + dev_err(rkcif->dev, "failed to link source pad of %s\n", + sd->name); + return ret; + } + + remote->sd =3D sd; + + return 0; +} + +static int rkcif_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct rkcif_device *rkcif =3D + container_of(notifier, struct rkcif_device, notifier); + + return v4l2_device_register_subdev_nodes(&rkcif->v4l2_dev); +} + +static const struct v4l2_async_notifier_operations rkcif_notifier_ops =3D { + .bound =3D rkcif_notifier_bound, + .complete =3D rkcif_notifier_complete, +}; + +static int rkcif_register(struct rkcif_device *rkcif) +{ + struct v4l2_async_notifier *ntf =3D &rkcif->notifier; + int ret; + + v4l2_async_nf_init(ntf, &rkcif->v4l2_dev); + ntf->ops =3D &rkcif_notifier_ops; + + ret =3D rkcif_dvp_register(rkcif); + if (ret && ret !=3D -ENODEV) + goto err_notifier_cleanup; + + ret =3D rkcif_mipi_register(rkcif); + if (ret && ret !=3D -ENODEV) + goto err_dvp_unregister; + + ret =3D v4l2_async_nf_register(ntf); + if (ret) + goto err_mipi_unregister; + + return 0; + +err_mipi_unregister: + rkcif_mipi_unregister(rkcif); +err_dvp_unregister: + rkcif_dvp_unregister(rkcif); +err_notifier_cleanup: + v4l2_async_nf_cleanup(&rkcif->notifier); + return ret; +} + +static void rkcif_unregister(struct rkcif_device *rkcif) +{ + v4l2_async_nf_unregister(&rkcif->notifier); + rkcif_mipi_unregister(rkcif); + rkcif_dvp_unregister(rkcif); + v4l2_async_nf_cleanup(&rkcif->notifier); +} + +static irqreturn_t rkcif_isr(int irq, void *ctx) +{ + irqreturn_t ret =3D IRQ_NONE; + + if (rkcif_dvp_isr(irq, ctx) =3D=3D IRQ_HANDLED) + ret =3D IRQ_HANDLED; + + if (rkcif_mipi_isr(irq, ctx) =3D=3D IRQ_HANDLED) + ret =3D IRQ_HANDLED; + + return ret; +} + +static int rkcif_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rkcif_device *rkcif; + int ret, irq, i; + + rkcif =3D devm_kzalloc(dev, sizeof(*rkcif), GFP_KERNEL); + if (!rkcif) + return -ENOMEM; + + rkcif->match_data =3D of_device_get_match_data(dev); + if (!rkcif->match_data) + return -ENODEV; + + dev_set_drvdata(dev, rkcif); + rkcif->dev =3D dev; + + rkcif->base_addr =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rkcif->base_addr)) + return PTR_ERR(rkcif->base_addr); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, rkcif_isr, IRQF_SHARED, + dev_driver_string(dev), dev); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + rkcif->clks_num =3D rkcif->match_data->clks_num; + for (i =3D 0; (i < rkcif->clks_num) && (i < RKCIF_CLK_MAX); i++) + rkcif->clks[i].id =3D rkcif->match_data->clks[i]; + ret =3D devm_clk_bulk_get(dev, rkcif->clks_num, rkcif->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get clocks\n"); + + rkcif->reset =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(rkcif->reset)) + return PTR_ERR(rkcif->reset); + + rkcif->grf =3D + syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + if (IS_ERR(rkcif->grf)) + rkcif->grf =3D NULL; + + pm_runtime_enable(&pdev->dev); + + rkcif->media_dev.dev =3D dev; + strscpy(rkcif->media_dev.model, RKCIF_DRIVER_NAME, + sizeof(rkcif->media_dev.model)); + media_device_init(&rkcif->media_dev); + + rkcif->v4l2_dev.mdev =3D &rkcif->media_dev; + ret =3D v4l2_device_register(dev, &rkcif->v4l2_dev); + if (ret) + goto err_media_dev_cleanup; + + ret =3D media_device_register(&rkcif->media_dev); + if (ret < 0) { + dev_err(dev, "failed to register media device: %d\n", ret); + goto err_v4l2_dev_unregister; + } + + ret =3D rkcif_register(rkcif); + if (ret) { + dev_err(dev, "failed to register media entities: %d\n", ret); + goto err_media_dev_unregister; + } + + return 0; + +err_media_dev_unregister: + media_device_unregister(&rkcif->media_dev); +err_v4l2_dev_unregister: + v4l2_device_unregister(&rkcif->v4l2_dev); +err_media_dev_cleanup: + media_device_cleanup(&rkcif->media_dev); + pm_runtime_disable(&pdev->dev); + return ret; +} + +static void rkcif_remove(struct platform_device *pdev) +{ + struct rkcif_device *rkcif =3D platform_get_drvdata(pdev); + + rkcif_unregister(rkcif); + media_device_unregister(&rkcif->media_dev); + v4l2_device_unregister(&rkcif->v4l2_dev); + media_device_cleanup(&rkcif->media_dev); + pm_runtime_disable(&pdev->dev); +} + +static int rkcif_runtime_suspend(struct device *dev) +{ + struct rkcif_device *rkcif =3D dev_get_drvdata(dev); + + /* + * Reset CIF (CRU, DMA, FIFOs) to allow a clean resume. + * Since this resets the IOMMU too, we cannot issue this reset when + * resuming. + */ + reset_control_assert(rkcif->reset); + udelay(5); + reset_control_deassert(rkcif->reset); + + clk_bulk_disable_unprepare(rkcif->clks_num, rkcif->clks); + + return 0; +} + +static int rkcif_runtime_resume(struct device *dev) +{ + struct rkcif_device *rkcif =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(rkcif->clks_num, rkcif->clks); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops rkcif_plat_pm_ops =3D { + .runtime_suspend =3D rkcif_runtime_suspend, + .runtime_resume =3D rkcif_runtime_resume, +}; + +static struct platform_driver rkcif_plat_drv =3D { + .driver =3D { + .name =3D RKCIF_DRIVER_NAME, + .of_match_table =3D rkcif_plat_of_match, + .pm =3D &rkcif_plat_pm_ops, + }, + .probe =3D rkcif_probe, + .remove =3D rkcif_remove, +}; +module_platform_driver(rkcif_plat_drv); + +MODULE_DESCRIPTION("Rockchip Camera Interface (CIF) platform driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-interface.c b/driv= ers/media/platform/rockchip/rkcif/rkcif-interface.c new file mode 100644 index 000000000000..0ec524586594 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-interface.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2025 Michael Riesch + */ + +#include +#include +#include +#include + +#include "rkcif-common.h" +#include "rkcif-interface.h" + +static inline struct rkcif_interface *to_rkcif_interface(struct v4l2_subde= v *sd) +{ + return container_of(sd, struct rkcif_interface, sd); +} + +static const struct media_entity_operations rkcif_interface_media_ops =3D { + .link_validate =3D v4l2_subdev_link_validate, + .has_pad_interdep =3D v4l2_subdev_has_pad_interdep, +}; + +static int rkcif_interface_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *format) +{ + struct rkcif_interface *interface =3D to_rkcif_interface(sd); + const struct rkcif_input_fmt *input; + struct v4l2_mbus_framefmt *sink, *src; + + /* the format on the source pad always matches the sink pad */ + if (format->pad =3D=3D RKCIF_IF_PAD_SRC) + return v4l2_subdev_get_fmt(sd, state, format); + + input =3D rkcif_interface_find_input_fmt(interface, true, + format->format.code); + format->format.code =3D input->mbus_code; + + sink =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); + if (!sink) + return -EINVAL; + + *sink =3D format->format; + + /* propagate the format to the source pad */ + src =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!src) + return -EINVAL; + + *src =3D *sink; + + return 0; +} + +static int rkcif_interface_get_sel(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_mbus_framefmt *sink; + struct v4l2_rect *crop; + int ret =3D 0; + + if (sel->pad !=3D RKCIF_IF_PAD_SRC) + return -EINVAL; + + sink =3D v4l2_subdev_state_get_opposite_stream_format(state, sel->pad, + sel->stream); + if (!sink) + return -EINVAL; + + crop =3D v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); + if (!crop) + return -EINVAL; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.left =3D 0; + sel->r.top =3D 0; + sel->r.width =3D sink->width; + sel->r.height =3D sink->height; + break; + case V4L2_SEL_TGT_CROP: + sel->r =3D *crop; + break; + default: + ret =3D -EINVAL; + } + + return ret; +} + +static int rkcif_interface_set_sel(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_mbus_framefmt *sink, *src; + struct v4l2_rect *crop; + + if (sel->pad !=3D RKCIF_IF_PAD_SRC || sel->target !=3D V4L2_SEL_TGT_CROP) + return -EINVAL; + + sink =3D v4l2_subdev_state_get_opposite_stream_format(state, sel->pad, + sel->stream); + if (!sink) + return -EINVAL; + + src =3D v4l2_subdev_state_get_format(state, sel->pad, sel->stream); + if (!src) + return -EINVAL; + + crop =3D v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); + if (!crop) + return -EINVAL; + + /* only starting point of crop can be specified */ + sel->r.height =3D sink->height - sel->r.top; + sel->r.width =3D sink->width - sel->r.left; + *crop =3D sel->r; + + src->height =3D sel->r.height; + src->width =3D sel->r.width; + + return 0; +} + +static int rkcif_interface_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + int ret; + + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < routing->num_routes; i++) { + const struct v4l2_subdev_route *route =3D &routing->routes[i]; + + if (route->source_stream >=3D RKCIF_ID_MAX) + return -EINVAL; + } + + ret =3D v4l2_subdev_set_routing(sd, state, routing); + + return ret; +} + +static int rkcif_interface_apply_crop(struct rkcif_stream *stream, + struct v4l2_subdev_state *state) +{ + struct rkcif_interface *interface =3D stream->interface; + struct v4l2_rect *crop; + + crop =3D v4l2_subdev_state_get_crop(state, RKCIF_IF_PAD_SRC, stream->id); + if (!crop) + return -EINVAL; + + if (interface->set_crop) + interface->set_crop(stream, crop->left, crop->top); + + return 0; +} + +static int rkcif_interface_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct rkcif_interface *interface =3D to_rkcif_interface(sd); + struct rkcif_stream *stream; + struct v4l2_subdev_route *route; + struct v4l2_subdev *remote_sd; + struct media_pad *remote_pad; + u64 mask; + + remote_pad =3D + media_pad_remote_pad_first(&sd->entity.pads[RKCIF_IF_PAD_SINK]); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + /* DVP has one crop setting for all IDs */ + if (interface->type =3D=3D RKCIF_IF_DVP) { + stream =3D &interface->streams[RKCIF_ID0]; + rkcif_interface_apply_crop(stream, state); + } else { + /* TODO implement for MIPI */ + } + + mask =3D v4l2_subdev_state_xlate_streams(state, RKCIF_IF_PAD_SINK, + RKCIF_IF_PAD_SRC, &streams_mask); + + return v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); +} + +static int rkcif_interface_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct v4l2_subdev *remote_sd; + struct media_pad *remote_pad; + u64 mask; + + remote_pad =3D + media_pad_remote_pad_first(&sd->entity.pads[RKCIF_IF_PAD_SINK]); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + mask =3D v4l2_subdev_state_xlate_streams(state, RKCIF_IF_PAD_SINK, + RKCIF_IF_PAD_SRC, &streams_mask); + + return v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); +} + +static const struct v4l2_subdev_pad_ops rkcif_interface_pad_ops =3D { + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D rkcif_interface_set_fmt, + .get_selection =3D rkcif_interface_get_sel, + .set_selection =3D rkcif_interface_set_sel, + .set_routing =3D rkcif_interface_set_routing, + .enable_streams =3D rkcif_interface_enable_streams, + .disable_streams =3D rkcif_interface_disable_streams, +}; + +static const struct v4l2_subdev_ops rkcif_interface_ops =3D { + .pad =3D &rkcif_interface_pad_ops, +}; + +static int rkcif_interface_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct rkcif_interface *interface =3D to_rkcif_interface(sd); + struct v4l2_subdev_route routes[] =3D { + { + .sink_pad =3D RKCIF_IF_PAD_SINK, + .sink_stream =3D 0, + .source_pad =3D RKCIF_IF_PAD_SRC, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + }, + }; + struct v4l2_subdev_krouting routing =3D { + .len_routes =3D ARRAY_SIZE(routes), + .num_routes =3D ARRAY_SIZE(routes), + .routes =3D routes, + }; + const struct v4l2_mbus_framefmt dvp_default_format =3D { + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_REC709, + .ycbcr_enc =3D V4L2_YCBCR_ENC_709, + .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_NONE, + }; + const struct v4l2_mbus_framefmt mipi_default_format =3D { + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_RAW, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_FULL_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_NONE, + }; + const struct v4l2_mbus_framefmt *default_format; + int ret; + + default_format =3D (interface->type =3D=3D RKCIF_IF_DVP) ? + &dvp_default_format : + &mipi_default_format; + + ret =3D v4l2_subdev_set_routing_with_fmt(sd, state, &routing, + default_format); + + return ret; +} + +static const struct v4l2_subdev_internal_ops rkcif_interface_internal_ops = =3D { + .init_state =3D rkcif_interface_init_state, +}; + +static int rkcif_interface_add(struct rkcif_interface *interface) +{ + struct rkcif_device *rkcif =3D interface->rkcif; + struct rkcif_remote *remote; + struct v4l2_async_notifier *ntf =3D &rkcif->notifier; + struct v4l2_fwnode_endpoint *vep =3D &interface->vep; + struct device *dev =3D rkcif->dev; + struct fwnode_handle *ep; + u32 dvp_clk_delay =3D 0; + int ret; + + ep =3D fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), interface->index, + 0, 0); + if (!ep) + return -ENODEV; + + vep->bus_type =3D V4L2_MBUS_UNKNOWN; + ret =3D v4l2_fwnode_endpoint_parse(ep, vep); + if (ret) + goto complete; + + if (interface->type =3D=3D RKCIF_IF_DVP) { + if (vep->bus_type !=3D V4L2_MBUS_BT656 && + vep->bus_type !=3D V4L2_MBUS_PARALLEL) { + ret =3D dev_err_probe(dev, -EINVAL, + "unsupported bus type\n"); + goto complete; + } + + fwnode_property_read_u32(ep, "rockchip,dvp-clk-delay", + &dvp_clk_delay); + interface->dvp.dvp_clk_delay =3D dvp_clk_delay; + } + + remote =3D v4l2_async_nf_add_fwnode_remote(ntf, ep, struct rkcif_remote); + if (IS_ERR(remote)) { + ret =3D PTR_ERR(remote); + goto complete; + } + + remote->interface =3D interface; + interface->remote =3D remote; + interface->status =3D RKCIF_IF_ACTIVE; + ret =3D 0; + +complete: + fwnode_handle_put(ep); + + return ret; +} + +int rkcif_interface_register(struct rkcif_device *rkcif, + struct rkcif_interface *interface) +{ + struct media_pad *pads =3D interface->pads; + struct v4l2_subdev *sd =3D &interface->sd; + int ret; + + interface->rkcif =3D rkcif; + + v4l2_subdev_init(sd, &rkcif_interface_ops); + sd->dev =3D rkcif->dev; + sd->entity.ops =3D &rkcif_interface_media_ops; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; + sd->internal_ops =3D &rkcif_interface_internal_ops; + sd->owner =3D THIS_MODULE; + + if (interface->type =3D=3D RKCIF_IF_DVP) + snprintf(sd->name, sizeof(sd->name), "rkcif-dvp0"); + else if (interface->type =3D=3D RKCIF_IF_MIPI) + snprintf(sd->name, sizeof(sd->name), "rkcif-mipi%d", + interface->index - RKCIF_MIPI_BASE); + + pads[RKCIF_IF_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + pads[RKCIF_IF_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + ret =3D media_entity_pads_init(&sd->entity, RKCIF_IF_PAD_MAX, pads); + if (ret) + goto err; + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto err_entity_cleanup; + + ret =3D v4l2_device_register_subdev(&rkcif->v4l2_dev, sd); + if (ret) { + dev_err(sd->dev, "failed to register subdev\n"); + goto err_subdev_cleanup; + } + + ret =3D rkcif_interface_add(interface); + if (ret) + goto err_subdev_unregister; + + return 0; + +err_subdev_unregister: + v4l2_device_unregister_subdev(sd); +err_subdev_cleanup: + v4l2_subdev_cleanup(sd); +err_entity_cleanup: + media_entity_cleanup(&sd->entity); +err: + return ret; +} + +void rkcif_interface_unregister(struct rkcif_interface *interface) +{ + struct v4l2_subdev *sd =3D &interface->sd; + + if (interface->status !=3D RKCIF_IF_ACTIVE) + return; + + v4l2_device_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); +} + +const struct rkcif_input_fmt * +rkcif_interface_find_input_fmt(struct rkcif_interface *interface, bool ret= _def, + u32 mbus_code) +{ + const struct rkcif_input_fmt *fmt; + unsigned int i; + + WARN_ON(interface->in_fmts_num =3D=3D 0); + + for (i =3D 0; i < interface->in_fmts_num; i++) { + fmt =3D &interface->in_fmts[i]; + if (fmt->mbus_code =3D=3D mbus_code) + return fmt; + } + if (ret_def) + return &interface->in_fmts[0]; + else + return NULL; +} diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-interface.h b/driv= ers/media/platform/rockchip/rkcif/rkcif-interface.h new file mode 100644 index 000000000000..f37fde4cc6a2 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-interface.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Abstraction for the INTERFACE and CROP parts of the different CIF varia= nts. + * They shall be represented as V4L2 subdevice with one sink pad and one + * source pad. The sink pad is connected to a subdevice: either the subdev= ice + * provided by the driver of the companion chip connected to the DVP, or t= he + * subdevice provided by the MIPI CSI Receiver driver in + * rkcif-mipi-csi-receiver.c. The source pad is connected to an instance o= f the + * DMA abstraction in rkcif-stream.c. + * + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_INTERFACE_H +#define _RKCIF_INTERFACE_H + +#include "rkcif-common.h" + +int rkcif_interface_register(struct rkcif_device *rkcif, + struct rkcif_interface *interface); + +void rkcif_interface_unregister(struct rkcif_interface *interface); + +const struct rkcif_input_fmt * +rkcif_interface_find_input_fmt(struct rkcif_interface *interface, bool ret= _def, + u32 mbus_code); + +#endif diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-regs.h b/drivers/m= edia/platform/rockchip/rkcif/rkcif-regs.h new file mode 100644 index 000000000000..07fd64174e80 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-regs.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Copyright (C) 2023 Mehdi Djait + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_REGS_H +#define _RKCIF_REGS_H + +enum rkcif_dvp_register_index { + RKCIF_DVP_CTRL, + RKCIF_DVP_INTEN, + RKCIF_DVP_INTSTAT, + RKCIF_DVP_FOR, + RKCIF_DVP_LINE_NUM_ADDR, + RKCIF_DVP_FRM0_ADDR_Y, + RKCIF_DVP_FRM0_ADDR_UV, + RKCIF_DVP_FRM1_ADDR_Y, + RKCIF_DVP_FRM1_ADDR_UV, + RKCIF_DVP_VIR_LINE_WIDTH, + RKCIF_DVP_SET_SIZE, + RKCIF_DVP_SCL_CTRL, + RKCIF_DVP_CROP, + RKCIF_DVP_FRAME_STATUS, + RKCIF_DVP_LAST_LINE, + RKCIF_DVP_LAST_PIX, + RKCIF_DVP_REGISTER_MAX +}; + +#define RKCIF_REGISTER_NOTSUPPORTED 0x420000 + +#define RKCIF_FETCH_Y(VAL) ((VAL) & 0x1fff) + +#define RKCIF_CTRL_ENABLE_CAPTURE BIT(0) +#define RKCIF_CTRL_MODE_PINGPONG BIT(1) +#define RKCIF_CTRL_MODE_LINELOOP BIT(2) +#define RKCIF_CTRL_AXI_BURST_16 (0xf << 12) + +#define RKCIF_INTEN_FRAME_END_EN BIT(0) +#define RKCIF_INTEN_LINE_ERR_EN BIT(2) +#define RKCIF_INTEN_BUS_ERR_EN BIT(6) +#define RKCIF_INTEN_SCL_ERR_EN BIT(7) +#define RKCIF_INTEN_PST_INF_FRAME_END_EN BIT(9) + +#define RKCIF_INTSTAT_CLS 0x3ff +#define RKCIF_INTSTAT_FRAME_END BIT(0) +#define RKCIF_INTSTAT_LINE_END BIT(1) +#define RKCIF_INTSTAT_LINE_ERR BIT(2) +#define RKCIF_INTSTAT_PIX_ERR BIT(3) +#define RKCIF_INTSTAT_DFIFO_OF BIT(5) +#define RKCIF_INTSTAT_BUS_ERR BIT(6) +#define RKCIF_INTSTAT_PRE_INF_FRAME_END BIT(8) +#define RKCIF_INTSTAT_PST_INF_FRAME_END BIT(9) +#define RKCIF_INTSTAT_FRAME_END_CLR BIT(0) +#define RKCIF_INTSTAT_LINE_END_CLR BIT(1) +#define RKCIF_INTSTAT_LINE_ERR_CLR BIT(2) +#define RKCIF_INTSTAT_PST_INF_FRAME_END_CLR BIT(9) +#define RKCIF_INTSTAT_ERR 0xfc + +#define RKCIF_FRAME_STAT_CLS 0x00 +#define RKCIF_FRAME_FRM0_STAT_CLS 0x20 + +#define RKCIF_FORMAT_VSY_HIGH_ACTIVE BIT(0) +#define RKCIF_FORMAT_HSY_LOW_ACTIVE BIT(1) + +#define RKCIF_FORMAT_INPUT_MODE_YUV (0x00 << 2) +#define RKCIF_FORMAT_INPUT_MODE_PAL (0x02 << 2) +#define RKCIF_FORMAT_INPUT_MODE_NTSC (0x03 << 2) +#define RKCIF_FORMAT_INPUT_MODE_BT1120 (0x07 << 2) +#define RKCIF_FORMAT_INPUT_MODE_RAW (0x04 << 2) +#define RKCIF_FORMAT_INPUT_MODE_JPEG (0x05 << 2) +#define RKCIF_FORMAT_INPUT_MODE_MIPI (0x06 << 2) + +#define RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY (0x00 << 5) +#define RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU (0x01 << 5) +#define RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY (0x02 << 5) +#define RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV (0x03 << 5) +#define RKCIF_FORMAT_YUV_INPUT_422 (0x00 << 7) +#define RKCIF_FORMAT_YUV_INPUT_420 BIT(7) + +#define RKCIF_FORMAT_INPUT_420_ORDER_ODD BIT(8) + +#define RKCIF_FORMAT_CCIR_INPUT_ORDER_EVEN BIT(9) + +#define RKCIF_FORMAT_RAW_DATA_WIDTH_8 (0x00 << 11) +#define RKCIF_FORMAT_RAW_DATA_WIDTH_10 (0x01 << 11) +#define RKCIF_FORMAT_RAW_DATA_WIDTH_12 (0x02 << 11) + +#define RKCIF_FORMAT_YUV_OUTPUT_422 (0x00 << 16) +#define RKCIF_FORMAT_YUV_OUTPUT_420 BIT(16) + +#define RKCIF_FORMAT_OUTPUT_420_ORDER_EVEN (0x00 << 17) +#define RKCIF_FORMAT_OUTPUT_420_ORDER_ODD BIT(17) + +#define RKCIF_FORMAT_RAWD_DATA_LITTLE_ENDIAN (0x00 << 18) +#define RKCIF_FORMAT_RAWD_DATA_BIG_ENDIAN BIT(18) + +#define RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV (0x00 << 19) +#define RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU BIT(19) + +#define RKCIF_FORMAT_BT1120_CLOCK_SINGLE_EDGES (0x00 << 24) +#define RKCIF_FORMAT_BT1120_CLOCK_DOUBLE_EDGES BIT(24) +#define RKCIF_FORMAT_BT1120_TRANSMIT_INTERFACE (0x00 << 25) +#define RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS BIT(25) +#define RKCIF_FORMAT_BT1120_YC_SWAP BIT(26) + +#define RKCIF_SCL_CTRL_ENABLE_SCL_DOWN BIT(0) +#define RKCIF_SCL_CTRL_ENABLE_SCL_UP BIT(1) +#define RKCIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS BIT(4) +#define RKCIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS BIT(5) +#define RKCIF_SCL_CTRL_ENABLE_32BIT_BYPASS BIT(6) +#define RKCIF_SCL_CTRL_DISABLE_32BIT_BYPASS (0x00 << 6) + +#define RKCIF_INTSTAT_F0_READY BIT(0) +#define RKCIF_INTSTAT_F1_READY BIT(1) + +#define RKCIF_XY_COORD(x, y) (((y) << 16) | (x)) + +/* GRF register offsets */ +#define RK3568_GRF_VI_CON0 0x340 +#define RK3568_GRF_VI_CON1 0x344 +#define RK3568_GRF_VI_STATUS0 0x348 + +#define RK3568_GRF_VI_CON1_CIF_DATAPATH BIT(9) +#define RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM GENMASK(6, 0) + +#define RK3568_GRF_WRITE_ENABLE(x) ((x) << 16) + +#endif diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-stream.c b/drivers= /media/platform/rockchip/rkcif/rkcif-stream.c new file mode 100644 index 000000000000..bfafd76f4494 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-stream.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Camera Interface (CIF) Driver + * + * Copyright (C) 2025 Michael Riesch + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "rkcif-common.h" +#include "rkcif-stream.h" + +#define CIF_REQ_BUFS_MIN 8 +#define CIF_MIN_WIDTH 64 +#define CIF_MIN_HEIGHT 64 +#define CIF_MAX_WIDTH 8192 +#define CIF_MAX_HEIGHT 8192 + +static inline struct rkcif_buffer *to_rkcif_buffer(struct vb2_v4l2_buffer = *vb) +{ + return container_of(vb, struct rkcif_buffer, vb); +} + +static inline struct rkcif_stream *to_rkcif_stream(struct video_device *vd= ev) +{ + return container_of(vdev, struct rkcif_stream, vdev); +} + +static struct rkcif_buffer *rkcif_stream_pop_buffer(struct rkcif_stream *s= tream) +{ + struct rkcif_buffer *buffer =3D NULL; + unsigned long lock_flags; + + spin_lock_irqsave(&stream->driver_queue_lock, lock_flags); + + if (list_empty(&stream->driver_queue)) + goto err_empty; + + buffer =3D list_first_entry(&stream->driver_queue, struct rkcif_buffer, + queue); + list_del(&buffer->queue); + +err_empty: + spin_unlock_irqrestore(&stream->driver_queue_lock, lock_flags); + return buffer; +} + +static void rkcif_stream_push_buffer(struct rkcif_stream *stream, + struct rkcif_buffer *buffer) +{ + unsigned long lock_flags; + + spin_lock_irqsave(&stream->driver_queue_lock, lock_flags); + list_add_tail(&buffer->queue, &stream->driver_queue); + spin_unlock_irqrestore(&stream->driver_queue_lock, lock_flags); +} + +static inline void rkcif_stream_return_buffer(struct rkcif_buffer *buffer, + enum vb2_buffer_state state) +{ + struct vb2_v4l2_buffer *vb =3D &buffer->vb; + + vb2_buffer_done(&vb->vb2_buf, state); +} + +static void rkcif_stream_complete_buffer(struct rkcif_stream *stream, + struct rkcif_buffer *buffer) +{ + struct vb2_v4l2_buffer *vb =3D &buffer->vb; + + vb->vb2_buf.timestamp =3D ktime_get_ns(); + vb->sequence =3D stream->frame_idx; + vb2_buffer_done(&vb->vb2_buf, VB2_BUF_STATE_DONE); + stream->frame_idx++; +} + +void rkcif_stream_pingpong(struct rkcif_stream *stream) +{ + struct rkcif_buffer *buffer; + + buffer =3D stream->buffers[stream->frame_phase]; + if (!buffer->is_dummy) + rkcif_stream_complete_buffer(stream, buffer); + + buffer =3D rkcif_stream_pop_buffer(stream); + if (buffer) { + stream->buffers[stream->frame_phase] =3D buffer; + stream->buffers[stream->frame_phase]->is_dummy =3D false; + } else { + stream->buffers[stream->frame_phase] =3D &stream->dummy.buffer; + stream->buffers[stream->frame_phase]->is_dummy =3D true; + dev_warn(stream->rkcif->dev, + "no buffer available, frame will be dropped\n"); + } + + if (stream->queue_buffer) + stream->queue_buffer(stream, stream->frame_phase); + + stream->frame_phase =3D 1 - stream->frame_phase; +} + +static int rkcif_stream_init_buffers(struct rkcif_stream *stream) +{ + struct v4l2_pix_format_mplane *pix =3D &stream->pix; + int i; + + stream->buffers[0] =3D rkcif_stream_pop_buffer(stream); + if (!stream->buffers[0]) + goto err_buff_0; + + stream->buffers[1] =3D rkcif_stream_pop_buffer(stream); + if (!stream->buffers[1]) + goto err_buff_1; + + if (stream->queue_buffer) { + stream->queue_buffer(stream, 0); + stream->queue_buffer(stream, 1); + } + + stream->dummy.size =3D pix->num_planes * pix->plane_fmt[0].sizeimage; + stream->dummy.vaddr =3D + dma_alloc_attrs(stream->rkcif->dev, stream->dummy.size, + &stream->dummy.buffer.buff_addr[0], GFP_KERNEL, + DMA_ATTR_NO_KERNEL_MAPPING); + if (!stream->dummy.vaddr) + goto err_dummy; + + for (i =3D 1; i < pix->num_planes; i++) + stream->dummy.buffer.buff_addr[i] =3D + stream->dummy.buffer.buff_addr[i - 1] + + pix->plane_fmt[i - 1].bytesperline * pix->height; + + return 0; + +err_dummy: + rkcif_stream_return_buffer(stream->buffers[1], VB2_BUF_STATE_QUEUED); + stream->buffers[1] =3D NULL; + +err_buff_1: + rkcif_stream_return_buffer(stream->buffers[0], VB2_BUF_STATE_QUEUED); + stream->buffers[0] =3D NULL; +err_buff_0: + return -EINVAL; +} + +static void rkcif_stream_return_all_buffers(struct rkcif_stream *stream, + enum vb2_buffer_state state) +{ + struct rkcif_buffer *buffer; + + if (stream->buffers[0] && !stream->buffers[0]->is_dummy) { + rkcif_stream_return_buffer(stream->buffers[0], state); + stream->buffers[0] =3D NULL; + } + + if (stream->buffers[1] && !stream->buffers[1]->is_dummy) { + rkcif_stream_return_buffer(stream->buffers[1], state); + stream->buffers[1] =3D NULL; + } + + while ((buffer =3D rkcif_stream_pop_buffer(stream))) + rkcif_stream_return_buffer(buffer, state); + + if (stream->dummy.vaddr) { + dma_free_attrs(stream->rkcif->dev, stream->dummy.size, + stream->dummy.vaddr, + stream->dummy.buffer.buff_addr[0], + DMA_ATTR_NO_KERNEL_MAPPING); + stream->dummy.vaddr =3D NULL; + } +} + +static int rkcif_stream_setup_queue(struct vb2_queue *queue, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct rkcif_stream *stream =3D queue->drv_priv; + struct v4l2_pix_format_mplane *pix =3D &stream->pix; + unsigned int i; + + if (*num_planes) { + if (*num_planes !=3D pix->num_planes) + return -EINVAL; + + for (i =3D 0; i < pix->num_planes; i++) + if (sizes[i] < pix->plane_fmt[i].sizeimage) + return -EINVAL; + } else { + *num_planes =3D pix->num_planes; + for (i =3D 0; i < pix->num_planes; i++) + sizes[i] =3D pix->plane_fmt[i].sizeimage; + } + + return 0; +} + +static int rkcif_stream_prepare_buffer(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb); + struct rkcif_buffer *buffer =3D to_rkcif_buffer(vbuf); + struct rkcif_stream *stream =3D vb->vb2_queue->drv_priv; + const struct rkcif_output_fmt *fmt; + struct v4l2_pix_format_mplane *pix =3D &stream->pix; + unsigned int i; + + memset(buffer->buff_addr, 0, sizeof(buffer->buff_addr)); + for (i =3D 0; i < pix->num_planes; i++) + buffer->buff_addr[i] =3D vb2_dma_contig_plane_dma_addr(vb, i); + + /* apply fallback for non-mplane formats, if required */ + if (pix->num_planes =3D=3D 1) { + fmt =3D rkcif_stream_find_output_fmt(stream, true, + pix->pixelformat); + for (i =3D 1; i < fmt->cplanes; i++) + buffer->buff_addr[i] =3D + buffer->buff_addr[i - 1] + + pix->plane_fmt[i - 1].bytesperline * + pix->height; + } + + for (i =3D 0; i < pix->num_planes; i++) { + unsigned long size =3D pix->plane_fmt[i].sizeimage; + + if (vb2_plane_size(vb, i) < size) { + dev_err(stream->rkcif->dev, + "user buffer too small (%ld < %ld)\n", + vb2_plane_size(vb, i), size); + return -EINVAL; + } + + vb2_set_plane_payload(vb, i, size); + } + + return 0; +} + +static void rkcif_stream_queue_buffer(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb); + struct rkcif_buffer *buffer =3D to_rkcif_buffer(vbuf); + struct rkcif_stream *stream =3D vb->vb2_queue->drv_priv; + + rkcif_stream_push_buffer(stream, buffer); +} + +static int rkcif_stream_start_streaming(struct vb2_queue *queue, + unsigned int count) +{ + struct rkcif_stream *stream =3D queue->drv_priv; + struct rkcif_device *rkcif =3D stream->rkcif; + u64 mask; + int ret; + + stream->frame_idx =3D 0; + stream->frame_phase =3D 0; + + ret =3D video_device_pipeline_start(&stream->vdev, &stream->pipeline); + if (ret) { + dev_err(rkcif->dev, "failed to start pipeline %d\n", ret); + goto err_out; + } + + ret =3D pm_runtime_resume_and_get(rkcif->dev); + if (ret < 0) { + dev_err(rkcif->dev, "failed to get runtime pm, %d\n", ret); + goto err_pipeline_stop; + } + + ret =3D rkcif_stream_init_buffers(stream); + if (ret) + goto err_runtime_put; + + if (stream->start_streaming) { + ret =3D stream->start_streaming(stream); + if (ret < 0) + goto err_runtime_put; + } + + mask =3D BIT_ULL(stream->id); + ret =3D v4l2_subdev_enable_streams(&stream->interface->sd, + RKCIF_IF_PAD_SRC, mask); + if (ret < 0) + goto err_stop_stream; + + return 0; + +err_stop_stream: + if (stream->stop_streaming) + stream->stop_streaming(stream); +err_runtime_put: + pm_runtime_put(rkcif->dev); +err_pipeline_stop: + video_device_pipeline_stop(&stream->vdev); +err_out: + rkcif_stream_return_all_buffers(stream, VB2_BUF_STATE_QUEUED); + return ret; +} + +static void rkcif_stream_stop_streaming(struct vb2_queue *queue) +{ + struct rkcif_stream *stream =3D queue->drv_priv; + struct rkcif_device *rkcif =3D stream->rkcif; + u64 mask; + int ret; + + mask =3D BIT_ULL(stream->id); + v4l2_subdev_disable_streams(&stream->interface->sd, RKCIF_IF_PAD_SRC, + mask); + + stream->stopping =3D true; + ret =3D wait_event_timeout(stream->wq_stopped, !stream->stopping, + msecs_to_jiffies(1000)); + + if (!ret && stream->stop_streaming) + stream->stop_streaming(stream); + + pm_runtime_put(rkcif->dev); + + rkcif_stream_return_all_buffers(stream, VB2_BUF_STATE_ERROR); + + video_device_pipeline_stop(&stream->vdev); +} + +static const struct vb2_ops rkcif_stream_vb2_ops =3D { + .queue_setup =3D rkcif_stream_setup_queue, + .buf_prepare =3D rkcif_stream_prepare_buffer, + .buf_queue =3D rkcif_stream_queue_buffer, + .wait_prepare =3D vb2_ops_wait_prepare, + .wait_finish =3D vb2_ops_wait_finish, + .start_streaming =3D rkcif_stream_start_streaming, + .stop_streaming =3D rkcif_stream_stop_streaming, +}; + +static int rkcif_stream_try_format(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct rkcif_stream *stream =3D video_drvdata(file); + struct v4l2_pix_format_mplane *pix =3D &f->fmt.pix_mp; + const struct rkcif_output_fmt *fmt; + u32 height, width; + + fmt =3D rkcif_stream_find_output_fmt(stream, true, pix->pixelformat); + height =3D clamp_t(u32, pix->height, CIF_MIN_HEIGHT, CIF_MAX_HEIGHT); + width =3D clamp_t(u32, pix->width, CIF_MIN_WIDTH, CIF_MAX_WIDTH); + v4l2_fill_pixfmt_mp(pix, fmt->fourcc, width, height); + + return 0; +} + +static int rkcif_stream_set_format(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct rkcif_stream *stream =3D video_drvdata(file); + struct v4l2_pix_format_mplane *pix =3D &f->fmt.pix_mp; + int ret; + + if (vb2_is_busy(&stream->buf_queue)) + return -EBUSY; + + ret =3D rkcif_stream_try_format(file, priv, f); + if (ret) + return ret; + + stream->pix =3D *pix; + + return 0; +} + +static int rkcif_stream_get_format(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct rkcif_stream *stream =3D video_drvdata(file); + + f->fmt.pix_mp =3D stream->pix; + + return 0; +} + +static int rkcif_stream_enum_formats(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct rkcif_stream *stream =3D video_drvdata(file); + + if (f->index >=3D stream->out_fmts_num) + return -EINVAL; + + f->pixelformat =3D stream->out_fmts[f->index].fourcc; + + return 0; +} + +static int rkcif_stream_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index > 0) + return -EINVAL; + + fsize->type =3D V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise.min_width =3D CIF_MIN_WIDTH; + fsize->stepwise.max_width =3D CIF_MAX_WIDTH; + fsize->stepwise.step_width =3D 8; + fsize->stepwise.min_height =3D CIF_MIN_HEIGHT; + fsize->stepwise.max_height =3D CIF_MAX_HEIGHT; + fsize->stepwise.step_height =3D 8; + + return 0; +} + +static int rkcif_stream_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct rkcif_stream *stream =3D video_drvdata(file); + struct device *dev =3D stream->rkcif->dev; + + strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); + strscpy(cap->card, dev->driver->name, sizeof(cap->card)); + + return 0; +} + +static const struct v4l2_ioctl_ops rkcif_stream_ioctl_ops =3D { + .vidioc_reqbufs =3D vb2_ioctl_reqbufs, + .vidioc_querybuf =3D vb2_ioctl_querybuf, + .vidioc_create_bufs =3D vb2_ioctl_create_bufs, + .vidioc_qbuf =3D vb2_ioctl_qbuf, + .vidioc_expbuf =3D vb2_ioctl_expbuf, + .vidioc_dqbuf =3D vb2_ioctl_dqbuf, + .vidioc_prepare_buf =3D vb2_ioctl_prepare_buf, + .vidioc_streamon =3D vb2_ioctl_streamon, + .vidioc_streamoff =3D vb2_ioctl_streamoff, + .vidioc_try_fmt_vid_cap_mplane =3D rkcif_stream_try_format, + .vidioc_s_fmt_vid_cap_mplane =3D rkcif_stream_set_format, + .vidioc_g_fmt_vid_cap_mplane =3D rkcif_stream_get_format, + .vidioc_enum_fmt_vid_cap =3D rkcif_stream_enum_formats, + .vidioc_enum_framesizes =3D rkcif_stream_enum_framesizes, + .vidioc_querycap =3D rkcif_stream_querycap, +}; + +static int rkcif_stream_link_validate(struct media_link *link) +{ + struct video_device *vdev =3D + media_entity_to_video_device(link->sink->entity); + struct v4l2_mbus_framefmt *source_fmt; + struct v4l2_subdev *sd; + struct v4l2_subdev_state *state; + struct rkcif_stream *stream =3D to_rkcif_stream(vdev); + int ret =3D -EINVAL; + + if (!media_entity_remote_source_pad_unique(link->sink->entity)) + return -ENOTCONN; + + sd =3D media_entity_to_v4l2_subdev(link->source->entity); + + state =3D v4l2_subdev_lock_and_get_active_state(sd); + + source_fmt =3D v4l2_subdev_state_get_format(state, link->source->index, + stream->id); + if (!source_fmt) + goto out; + + if (source_fmt->height !=3D stream->pix.height || + source_fmt->width !=3D stream->pix.width) { + dev_dbg(stream->rkcif->dev, + "link '%s':%u -> '%s':%u not valid: %ux%u !=3D %ux%u\n", + link->source->entity->name, link->source->index, + link->sink->entity->name, link->sink->index, + source_fmt->width, source_fmt->height, + stream->pix.width, stream->pix.height); + goto out; + } + + ret =3D 0; + +out: + v4l2_subdev_unlock_state(state); + return ret; +} + +static const struct media_entity_operations rkcif_stream_media_ops =3D { + .link_validate =3D rkcif_stream_link_validate, +}; + +static const struct v4l2_file_operations rkcif_stream_file_ops =3D { + .open =3D v4l2_fh_open, + .release =3D vb2_fop_release, + .unlocked_ioctl =3D video_ioctl2, + .poll =3D vb2_fop_poll, + .mmap =3D vb2_fop_mmap, +}; + +static int rkcif_stream_init_vb2_queue(struct vb2_queue *q, + struct rkcif_stream *stream) +{ + q->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + q->io_modes =3D VB2_MMAP | VB2_DMABUF; + q->drv_priv =3D stream; + q->ops =3D &rkcif_stream_vb2_ops; + q->mem_ops =3D &vb2_dma_contig_memops; + q->buf_struct_size =3D sizeof(struct rkcif_buffer); + q->min_queued_buffers =3D CIF_REQ_BUFS_MIN; + q->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->lock =3D &stream->vlock; + q->dev =3D stream->rkcif->dev; + + return vb2_queue_init(q); +} + +int rkcif_stream_register(struct rkcif_device *rkcif, + struct rkcif_stream *stream) +{ + struct rkcif_interface *interface =3D stream->interface; + struct v4l2_device *v4l2_dev =3D &rkcif->v4l2_dev; + struct video_device *vdev =3D &stream->vdev; + u32 link_flags =3D 0; + int ret; + + stream->rkcif =3D rkcif; + + INIT_LIST_HEAD(&stream->driver_queue); + spin_lock_init(&stream->driver_queue_lock); + + init_waitqueue_head(&stream->wq_stopped); + + mutex_init(&stream->vlock); + + vdev->device_caps =3D V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING | + V4L2_CAP_IO_MC; + vdev->entity.ops =3D &rkcif_stream_media_ops; + vdev->fops =3D &rkcif_stream_file_ops; + vdev->ioctl_ops =3D &rkcif_stream_ioctl_ops; + vdev->lock =3D &stream->vlock; + vdev->minor =3D -1; + vdev->release =3D video_device_release_empty; + vdev->v4l2_dev =3D v4l2_dev; + vdev->vfl_dir =3D VFL_DIR_RX; + video_set_drvdata(vdev, stream); + + stream->pad.flags =3D MEDIA_PAD_FL_SINK; + + rkcif_stream_init_vb2_queue(&stream->buf_queue, stream); + + vdev->queue =3D &stream->buf_queue; + if (interface->type =3D=3D RKCIF_IF_DVP) + snprintf(vdev->name, sizeof(vdev->name), "rkcif-dvp0-id%d", + stream->id); + else if (interface->type =3D=3D RKCIF_IF_MIPI) + snprintf(vdev->name, sizeof(vdev->name), "rkcif-mipi%d-id%d", + interface->index - RKCIF_MIPI_BASE, stream->id); + + ret =3D media_entity_pads_init(&vdev->entity, 1, &stream->pad); + if (ret < 0) { + dev_err(rkcif->dev, + "failed to initialize stream media pad: %d\n", ret); + return ret; + } + + ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + dev_err(rkcif->dev, "failed to register video device: %d\n", + ret); + goto err_media_entity_cleanup; + } + + /* enable only stream ID0 by default */ + if (stream->id =3D=3D RKCIF_ID0) + link_flags |=3D MEDIA_LNK_FL_ENABLED; + + ret =3D media_create_pad_link(&interface->sd.entity, RKCIF_IF_PAD_SRC, + &stream->vdev.entity, 0, link_flags); + if (ret) { + dev_err(rkcif->dev, "failed to link stream media pad: %d\n", + ret); + goto err_video_unregister; + } + + v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, + vdev->num); + + return 0; + +err_video_unregister: + video_unregister_device(&stream->vdev); +err_media_entity_cleanup: + media_entity_cleanup(&stream->vdev.entity); + return ret; +} + +void rkcif_stream_unregister(struct rkcif_stream *stream) +{ + video_unregister_device(&stream->vdev); + media_entity_cleanup(&stream->vdev.entity); +} + +const struct rkcif_output_fmt * +rkcif_stream_find_output_fmt(struct rkcif_stream *stream, bool ret_def, + u32 pixelfmt) +{ + const struct rkcif_output_fmt *fmt; + unsigned int i; + + WARN_ON(stream->out_fmts_num =3D=3D 0); + + for (i =3D 0; i < stream->out_fmts_num; i++) { + fmt =3D &stream->out_fmts[i]; + if (fmt->fourcc =3D=3D pixelfmt) + return fmt; + } + + if (ret_def) + return &stream->out_fmts[0]; + else + return NULL; +} diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-stream.h b/drivers= /media/platform/rockchip/rkcif/rkcif-stream.h new file mode 100644 index 000000000000..e50c9771f1b0 --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-stream.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Camera Interface (CIF) Driver + * + * Abstraction for the DMA part and the ping-pong scheme (a double-bufferi= ng + * mechanism) of the different CIF variants. + * Each stream is represented as V4L2 device whose corresponding media ent= ity + * has one sink pad. + * The sink pad is connected to an instance of the INTERFACE/CROP abstract= ion + * in rkcif-interface.c. + * + * Copyright (C) 2025 Michael Riesch + */ + +#ifndef _RKCIF_STREAM_H +#define _RKCIF_STREAM_H + +#include "rkcif-common.h" + +void rkcif_stream_pingpong(struct rkcif_stream *stream); + +int rkcif_stream_register(struct rkcif_device *rkcif, + struct rkcif_stream *stream); + +void rkcif_stream_unregister(struct rkcif_stream *stream); + +const struct rkcif_output_fmt * +rkcif_stream_find_output_fmt(struct rkcif_stream *stream, bool ret_def, + u32 pixelfmt); + +#endif --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FEBF235063; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; cv=none; b=F1mr/cTIPmlNN7X2Uyv8QoPapnHRrd+vm+7ouJbnrypOdjMiLJguG4DNEhVVcRs5Wvwh4buDHuCkPIzd5ZHjOzyhuNZ3okCszbi1msb3Vg+xb5keKbEJRprcLiRJK1s+cVE88anTc6fnBUBJqWjIOobLxXAGdx9ADiJG3OMcM3Y= ARC-Message-Signature: i=1; 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b=sLhGqNTYvkvz9nZFVPbw00xfeJ7k1ZQarEeX3wrWJC7rtpr0KgMCRtYfR4rz4HstZ BFi8PSKPrMhV9iHXKdABO7Q+71+sB7ilVJyZhY42JVSBNIPGIL/ygQJGASnUNTY5lG 7OzDQwdOpHJ/KDmLFnmtrfiRZRICV1Qzc2494a6Fu9rYpEcaCjN08p4xkn/vgmrdjG 8vISe0lzhWU7BI9sAe/Vfx21ZwtTGwluTebSvNr5fDJVGTQ6YuHyVHgbO8gtzRU6bc qn3+Id1b4ey6wehQ6BwkJ34dXPQsA4XANFOCBNY8AUoujuCUAZTEonri3rhNEu/LEU XPpVYztnJOF1w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D3A1C3ABA9; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:56 +0200 Subject: [PATCH v6 07/13] media: rockchip: rkcif: add driver for mipi csi-2 receiver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-7-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=20544; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=ZZHJDk0wn/yQ5gJzCKt7Rutiou4UUqSs9cWQYEkDr4A=; b=+VNYbWNYdDe8yt2f/hnm908d6n88hEjGe7HJOEHqzQin+7PdfjgMtQttTkOzjuuQ2KkNAzPd1 ln2IuoSFhbBDCIGBDnru6VWElq1ZvfXAPMcVdFZvCOkrLu0hclEZI2b X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3568 MIPI CSI-2 Receiver is a CSI-2 bridge with one input port and one output port. It receives the data with the help of an external MIPI PHY (C-PHY or D-PHY) and passes it to the Rockchip RK3568 Video Capture (VICAP) block. Add a V4L2 subdevice driver for this unit. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/rkcif/Makefile | 3 + .../rockchip/rkcif/rkcif-mipi-csi-receiver.c | 731 +++++++++++++++++= ++++ 2 files changed, 734 insertions(+) diff --git a/drivers/media/platform/rockchip/rkcif/Makefile b/drivers/media= /platform/rockchip/rkcif/Makefile index 818424972c7b..a5c18a45c213 100644 --- a/drivers/media/platform/rockchip/rkcif/Makefile +++ b/drivers/media/platform/rockchip/rkcif/Makefile @@ -5,3 +5,6 @@ rockchip-cif-objs +=3D rkcif-dev.o \ rkcif-capture-mipi.o \ rkcif-interface.o \ rkcif-stream.o + +obj-$(CONFIG_VIDEO_ROCKCHIP_CIF) +=3D rockchip-mipi-csi.o +rockchip-mipi-csi-objs +=3D rkcif-mipi-csi-receiver.o diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-mipi-csi-receiver.= c b/drivers/media/platform/rockchip/rkcif/rkcif-mipi-csi-receiver.c new file mode 100644 index 000000000000..81489f70490f --- /dev/null +++ b/drivers/media/platform/rockchip/rkcif/rkcif-mipi-csi-receiver.c @@ -0,0 +1,731 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip MIPI CSI-2 Receiver Driver + * + * Copyright (C) 2019 Rockchip Electronics Co., Ltd. + * Copyright (C) 2025 Michael Riesch + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define CSI2HOST_N_LANES 0x04 +#define CSI2HOST_CSI2_RESETN 0x10 +#define CSI2HOST_PHY_STATE 0x14 +#define CSI2HOST_ERR1 0x20 +#define CSI2HOST_ERR2 0x24 +#define CSI2HOST_MSK1 0x28 +#define CSI2HOST_MSK2 0x2c +#define CSI2HOST_CONTROL 0x40 + +#define SW_CPHY_EN(x) ((x) << 0) +#define SW_DSI_EN(x) ((x) << 4) +#define SW_DATATYPE_FS(x) ((x) << 8) +#define SW_DATATYPE_FE(x) ((x) << 14) +#define SW_DATATYPE_LS(x) ((x) << 20) +#define SW_DATATYPE_LE(x) ((x) << 26) + +#define RKCIF_CSI_CLKS_MAX 1 + +enum { + RKCIF_CSI_PAD_SINK, + RKCIF_CSI_PAD_SRC, + RKCIF_CSI_PAD_MAX, +}; + +struct rkcif_csi_format { + u32 code; + u8 depth; + u8 csi_dt; +}; + +struct rkcif_csi_device { + struct device *dev; + + void __iomem *base_addr; + struct clk_bulk_data *clks; + unsigned int clks_num; + struct phy *phy; + struct reset_control *reset; + + const struct rkcif_csi_format *formats; + unsigned int formats_num; + + struct media_pad pads[RKCIF_CSI_PAD_MAX]; + struct v4l2_async_notifier notifier; + struct v4l2_fwnode_endpoint vep; + struct v4l2_subdev sd; + + struct v4l2_subdev *source_sd; + u32 source_pad; +}; + +static const struct v4l2_mbus_framefmt default_format =3D { + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_RAW, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_FULL_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_NONE, +}; + +static const struct rkcif_csi_format formats[] =3D { + /* YUV formats */ + { + .code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + /* RGB formats */ + { + .code =3D MEDIA_BUS_FMT_RGB888_1X24, + .depth =3D 24, + .csi_dt =3D MIPI_CSI2_DT_RGB888, + }, + { + .code =3D MEDIA_BUS_FMT_BGR888_1X24, + .depth =3D 24, + .csi_dt =3D MIPI_CSI2_DT_RGB888, + }, + /* Bayer formats */ + { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, +}; + +static inline struct rkcif_csi_device *to_rkcif_csi(struct v4l2_subdev *sd) +{ + return container_of(sd, struct rkcif_csi_device, sd); +} + +static inline __maybe_unused void +rkcif_csi_write(struct rkcif_csi_device *csi_dev, unsigned int addr, u32 v= al) +{ + writel(val, csi_dev->base_addr + addr); +} + +static inline __maybe_unused u32 +rkcif_csi_read(struct rkcif_csi_device *csi_dev, unsigned int addr) +{ + return readl(csi_dev->base_addr + addr); +} + +static const struct rkcif_csi_format * +rkcif_csi_find_format(struct rkcif_csi_device *csi_dev, u32 mbus_code) +{ + const struct rkcif_csi_format *format; + + WARN_ON(csi_dev->formats_num =3D=3D 0); + + for (int i =3D 0; i < csi_dev->formats_num; i++) { + format =3D &csi_dev->formats[i]; + if (format->code =3D=3D mbus_code) + return format; + } + + return NULL; +} + +static int rkcif_csi_start(struct rkcif_csi_device *csi_dev) +{ + enum v4l2_mbus_type bus_type =3D csi_dev->vep.bus_type; + union phy_configure_opts opts; + s64 link_freq; + u32 lanes =3D csi_dev->vep.bus.mipi_csi2.num_data_lanes; + u32 control =3D 0; + + if (lanes < 1 || lanes > 4) + return -EINVAL; + + /* set mult and div to 0, thus completely rely on V4L2_CID_LINK_FREQ */ + link_freq =3D v4l2_get_link_freq(csi_dev->source_sd->ctrl_handler, 0, 0); + if (link_freq <=3D 0) + return -EINVAL; + + if (bus_type =3D=3D V4L2_MBUS_CSI2_DPHY) { + struct phy_configure_opts_mipi_dphy *cfg =3D &opts.mipi_dphy; + + phy_mipi_dphy_get_default_config_for_hsclk(link_freq * 2, lanes, + cfg); + phy_set_mode(csi_dev->phy, PHY_MODE_MIPI_DPHY); + phy_configure(csi_dev->phy, &opts); + + control |=3D SW_CPHY_EN(0); + + } else if (bus_type =3D=3D V4L2_MBUS_CSI2_CPHY) { + control |=3D SW_CPHY_EN(1); + + /* TODO: implement CPHY configuration */ + } else { + return -EINVAL; + } + + control |=3D SW_DATATYPE_FS(0x00) | SW_DATATYPE_FE(0x01) | + SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03); + + rkcif_csi_write(csi_dev, CSI2HOST_N_LANES, lanes - 1); + rkcif_csi_write(csi_dev, CSI2HOST_CONTROL, control); + rkcif_csi_write(csi_dev, CSI2HOST_CSI2_RESETN, 1); + + phy_power_on(csi_dev->phy); + + return 0; +} + +static void rkcif_csi_stop(struct rkcif_csi_device *csi_dev) +{ + phy_power_off(csi_dev->phy); + + rkcif_csi_write(csi_dev, CSI2HOST_CSI2_RESETN, 0); + rkcif_csi_write(csi_dev, CSI2HOST_MSK1, ~0); + rkcif_csi_write(csi_dev, CSI2HOST_MSK2, ~0); +} + +static const struct media_entity_operations rkcif_csi_media_ops =3D { + .link_validate =3D v4l2_subdev_link_validate, +}; + +static int rkcif_csi_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct rkcif_csi_device *csi_dev =3D to_rkcif_csi(sd); + + if (code->pad =3D=3D RKCIF_CSI_PAD_SRC) { + const struct v4l2_mbus_framefmt *sink_fmt; + + if (code->index) + return -EINVAL; + + sink_fmt =3D v4l2_subdev_state_get_format(sd_state, + RKCIF_CSI_PAD_SINK); + code->code =3D sink_fmt->code; + + return 0; + } else if (code->pad =3D=3D RKCIF_CSI_PAD_SINK) { + if (code->index > csi_dev->formats_num) + return -EINVAL; + + code->code =3D csi_dev->formats[code->index].code; + return 0; + } + + return -EINVAL; +} + +static int rkcif_csi_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *format) +{ + struct rkcif_csi_device *csi_dev =3D to_rkcif_csi(sd); + const struct rkcif_csi_format *fmt; + struct v4l2_mbus_framefmt *sink, *src; + + /* the format on the source pad always matches the sink pad */ + if (format->pad =3D=3D RKCIF_CSI_PAD_SRC) + return v4l2_subdev_get_fmt(sd, state, format); + + sink =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); + if (!sink) + return -EINVAL; + + fmt =3D rkcif_csi_find_format(csi_dev, format->format.code); + if (fmt) + *sink =3D format->format; + else + *sink =3D default_format; + + /* propagate the format to the source pad */ + src =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!src) + return -EINVAL; + + *src =3D *sink; + + return 0; +} + +static int rkcif_csi_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + int ret; + + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + ret =3D v4l2_subdev_set_routing_with_fmt(sd, state, routing, + &default_format); + if (ret) + return ret; + + return 0; +} + +static int rkcif_csi_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct rkcif_csi_device *csi_dev =3D to_rkcif_csi(sd); + struct v4l2_subdev *remote_sd; + struct media_pad *sink_pad, *remote_pad; + struct device *dev =3D csi_dev->dev; + u64 mask; + int ret; + + sink_pad =3D &sd->entity.pads[RKCIF_CSI_PAD_SINK]; + remote_pad =3D media_pad_remote_pad_first(sink_pad); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + mask =3D v4l2_subdev_state_xlate_streams(state, RKCIF_CSI_PAD_SINK, + RKCIF_CSI_PAD_SRC, + &streams_mask); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + goto err; + + ret =3D rkcif_csi_start(csi_dev); + if (ret) { + dev_err(dev, "failed to enable CSI hardware\n"); + goto err_pm_runtime_put; + } + + ret =3D v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); + if (ret) + goto err_csi_stop; + + return 0; + +err_csi_stop: + rkcif_csi_stop(csi_dev); +err_pm_runtime_put: + pm_runtime_put_sync(dev); +err: + return ret; +} + +static int rkcif_csi_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct rkcif_csi_device *csi_dev =3D to_rkcif_csi(sd); + struct v4l2_subdev *remote_sd; + struct media_pad *sink_pad, *remote_pad; + struct device *dev =3D csi_dev->dev; + u64 mask; + int ret; + + sink_pad =3D &sd->entity.pads[RKCIF_CSI_PAD_SINK]; + remote_pad =3D media_pad_remote_pad_first(sink_pad); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + mask =3D v4l2_subdev_state_xlate_streams(state, RKCIF_CSI_PAD_SINK, + RKCIF_CSI_PAD_SRC, + &streams_mask); + + ret =3D v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); + + rkcif_csi_stop(csi_dev); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static const struct v4l2_subdev_pad_ops rkcif_csi_pad_ops =3D { + .enum_mbus_code =3D rkcif_csi_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D rkcif_csi_set_fmt, + .set_routing =3D rkcif_csi_set_routing, + .enable_streams =3D rkcif_csi_enable_streams, + .disable_streams =3D rkcif_csi_disable_streams, +}; + +static const struct v4l2_subdev_ops rkcif_csi_ops =3D { + .pad =3D &rkcif_csi_pad_ops, +}; + +static int rkcif_csi_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] =3D { + { + .sink_pad =3D RKCIF_CSI_PAD_SINK, + .sink_stream =3D 0, + .source_pad =3D RKCIF_CSI_PAD_SRC, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + }, + }; + struct v4l2_subdev_krouting routing =3D { + .len_routes =3D ARRAY_SIZE(routes), + .num_routes =3D ARRAY_SIZE(routes), + .routes =3D routes, + }; + int ret; + + ret =3D v4l2_subdev_set_routing_with_fmt(sd, state, &routing, + &default_format); + + return ret; +} + +static const struct v4l2_subdev_internal_ops rkcif_csi_internal_ops =3D { + .init_state =3D rkcif_csi_init_state, +}; + +static int rkcif_csi_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_connection *asd) +{ + struct rkcif_csi_device *csi_dev =3D + container_of(notifier, struct rkcif_csi_device, notifier); + int source_pad; + + source_pad =3D media_entity_get_fwnode_pad(&sd->entity, sd->fwnode, + MEDIA_PAD_FL_SOURCE); + if (source_pad < 0) { + dev_err(csi_dev->dev, "failed to find source pad for %s\n", + sd->name); + return source_pad; + } + + csi_dev->source_sd =3D sd; + csi_dev->source_pad =3D source_pad; + + return media_create_pad_link(&sd->entity, source_pad, + &csi_dev->sd.entity, RKCIF_CSI_PAD_SINK, + MEDIA_LNK_FL_ENABLED); +} + +static const struct v4l2_async_notifier_operations rkcif_csi_notifier_ops = =3D { + .bound =3D rkcif_csi_notifier_bound, +}; + +static int rkcif_csi_register_notifier(struct rkcif_csi_device *csi_dev) +{ + struct v4l2_async_connection *asd; + struct v4l2_async_notifier *ntf =3D &csi_dev->notifier; + struct v4l2_fwnode_endpoint *vep =3D &csi_dev->vep; + struct v4l2_subdev *sd =3D &csi_dev->sd; + struct device *dev =3D csi_dev->dev; + struct fwnode_handle *ep; + int ret =3D 0; + + ep =3D fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); + if (!ep) + return dev_err_probe(dev, -ENODEV, "failed to get endpoint\n"); + + vep->bus_type =3D V4L2_MBUS_UNKNOWN; + ret =3D v4l2_fwnode_endpoint_parse(ep, vep); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to parse endpoint\n"); + goto out; + } + + if (vep->bus_type !=3D V4L2_MBUS_CSI2_DPHY && + vep->bus_type !=3D V4L2_MBUS_CSI2_CPHY) { + ret =3D dev_err_probe(dev, -EINVAL, + "invalid bus type of endpoint\n"); + goto out; + } + + v4l2_async_subdev_nf_init(ntf, sd); + ntf->ops =3D &rkcif_csi_notifier_ops; + + asd =3D v4l2_async_nf_add_fwnode_remote(ntf, ep, + struct v4l2_async_connection); + if (IS_ERR(asd)) { + ret =3D PTR_ERR(asd); + goto err_nf_cleanup; + } + + ret =3D v4l2_async_nf_register(ntf); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register notifier\n"); + goto err_nf_cleanup; + } + + goto out; + +err_nf_cleanup: + v4l2_async_nf_cleanup(ntf); +out: + fwnode_handle_put(ep); + return ret; +} + +static int rkcif_csi_register(struct rkcif_csi_device *csi_dev) +{ + struct media_pad *pads =3D csi_dev->pads; + struct v4l2_subdev *sd =3D &csi_dev->sd; + int ret; + + ret =3D rkcif_csi_register_notifier(csi_dev); + if (ret) + goto err; + + v4l2_subdev_init(sd, &rkcif_csi_ops); + sd->dev =3D csi_dev->dev; + sd->entity.ops =3D &rkcif_csi_media_ops; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; + sd->internal_ops =3D &rkcif_csi_internal_ops; + sd->owner =3D THIS_MODULE; + snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-csi %s", + dev_name(csi_dev->dev)); + + pads[RKCIF_CSI_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK | + MEDIA_PAD_FL_MUST_CONNECT; + pads[RKCIF_CSI_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + ret =3D media_entity_pads_init(&sd->entity, RKCIF_CSI_PAD_MAX, pads); + if (ret) + goto err_notifier_unregister; + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto err_entity_cleanup; + + ret =3D v4l2_async_register_subdev(sd); + if (ret) { + dev_err(sd->dev, "failed to register CSI subdev\n"); + goto err_subdev_cleanup; + } + + return 0; + +err_subdev_cleanup: + v4l2_subdev_cleanup(sd); +err_entity_cleanup: + media_entity_cleanup(&sd->entity); +err_notifier_unregister: + v4l2_async_nf_unregister(&csi_dev->notifier); + v4l2_async_nf_cleanup(&csi_dev->notifier); +err: + return ret; +} + +static void rkcif_csi_unregister(struct rkcif_csi_device *csi_dev) +{ + struct v4l2_subdev *sd =3D &csi_dev->sd; + + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); + v4l2_async_nf_unregister(&csi_dev->notifier); + v4l2_async_nf_cleanup(&csi_dev->notifier); +} + +static const struct of_device_id rkcif_csi_of_match[] =3D { + { + .compatible =3D "rockchip,rk3568-mipi-csi", + }, + {} +}; +MODULE_DEVICE_TABLE(of, rkcif_csi_of_match); + +static int rkcif_csi_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rkcif_csi_device *csi_dev; + int ret; + + csi_dev =3D devm_kzalloc(dev, sizeof(*csi_dev), GFP_KERNEL); + if (!csi_dev) + return -ENOMEM; + csi_dev->dev =3D dev; + dev_set_drvdata(dev, csi_dev); + + csi_dev->base_addr =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(csi_dev->base_addr)) + return PTR_ERR(csi_dev->base_addr); + + ret =3D devm_clk_bulk_get_all(dev, &csi_dev->clks); + if (ret !=3D RKCIF_CSI_CLKS_MAX) + return dev_err_probe(dev, -ENODEV, "failed to get clocks\n"); + csi_dev->clks_num =3D ret; + + csi_dev->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(csi_dev->phy)) + return dev_err_probe(dev, PTR_ERR(csi_dev->phy), + "failed to get MIPI CSI PHY\n"); + + csi_dev->reset =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(csi_dev->reset)) + return dev_err_probe(dev, PTR_ERR(csi_dev->reset), + "failed to get reset\n"); + + csi_dev->formats =3D formats; + csi_dev->formats_num =3D ARRAY_SIZE(formats); + + pm_runtime_enable(dev); + + ret =3D phy_init(csi_dev->phy); + if (ret) { + ret =3D dev_err_probe(dev, ret, + "failed to initialize MIPI CSI PHY\n"); + goto err_pm_runtime_disable; + } + + ret =3D rkcif_csi_register(csi_dev); + if (ret) + goto err_phy_exit; + + return 0; + +err_phy_exit: + phy_exit(csi_dev->phy); +err_pm_runtime_disable: + pm_runtime_disable(dev); + return ret; +} + +static void rkcif_csi_remove(struct platform_device *pdev) +{ + struct rkcif_csi_device *csi_dev =3D platform_get_drvdata(pdev); + struct device *dev =3D &pdev->dev; + + rkcif_csi_unregister(csi_dev); + phy_exit(csi_dev->phy); + pm_runtime_disable(dev); +} + +static int rkcif_csi_runtime_suspend(struct device *dev) +{ + struct rkcif_csi_device *csi_dev =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(csi_dev->clks_num, csi_dev->clks); + + return 0; +} + +static int rkcif_csi_runtime_resume(struct device *dev) +{ + struct rkcif_csi_device *csi_dev =3D dev_get_drvdata(dev); + int ret; + + reset_control_assert(csi_dev->reset); + udelay(5); + reset_control_deassert(csi_dev->reset); + + ret =3D clk_bulk_prepare_enable(csi_dev->clks_num, csi_dev->clks); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops rkcif_csi_pm_ops =3D { + .runtime_suspend =3D rkcif_csi_runtime_suspend, + .runtime_resume =3D rkcif_csi_runtime_resume, +}; + +static struct platform_driver rkcif_csi_drv =3D { + .driver =3D { + .name =3D "rockchip-mipi-csi", + .of_match_table =3D rkcif_csi_of_match, + .pm =3D &rkcif_csi_pm_ops, + }, + .probe =3D rkcif_csi_probe, + .remove =3D rkcif_csi_remove, +}; +module_platform_driver(rkcif_csi_drv); + +MODULE_DESCRIPTION("Rockchip MIPI CSI-2 Receiver platform driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F3F1235062; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Mzrjz5SE" Received: by smtp.kernel.org (Postfix) with ESMTPS id 27EF2C113CF; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746005265; bh=er8wKurj7xeDRCWEi9hOjleFbPWe/I5Mcz4gBPG2580=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Mzrjz5SE9TTP/MKzJ2SSyQwOcMEbrql6kN5I0ihnuTZtMHJZSpoS7RsCPnjd/6gqP Sz2hGqNMz4vxLGG87cgZ+Y8J4/U/oLA4tgQiA2iKlrZXGKnjYiKWQX1XVIPougO9WA yMzpNp7R68493e8hhZ92X+wJvU8MLNRZt4WzJq3WM8JKfnfACfooJUqv6vwcF0MP4w 5iO3i3DTFQvNJqH24EAB2UNHjxkLa++7wRdLd725ue4bY9HTmXuWBHya4WUaWwXbjH jBsm2hVf9Hd3+xRmcYrC4hcVKuzZo0Knlg6W9un4R1PL9FHMyQm10eZ+C6OfDKcRih QWbpCzfsTTEtw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DD9FC369DC; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:57 +0200 Subject: [PATCH v6 08/13] media: rockchip: rkcif: add support for mipi csi-2 capture Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-8-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=24868; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=SWJfvyiLGNJhEdVtMrheuT6meb+cOLr+vpK+5TQD5v0=; b=yNo7v6A11CCXfSB7pUxBCh6CEc4PXhyoyCEmMWcbT4IM5XNy8c97Bjq7nc74TBQT0U0qMCL0s UPjAcyPRnqDCHGauLQKSm2SNqOhHGpocNsSheiyqSUQbxaYlFiKsSEz X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The RK3568 Video Capture (VICAP) unit features a MIPI CSI-2 capture interface that can receive video data and write it into system memory using the ping-pong scheme. Add support for it. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch Reviewed-by: Bryan O'Donoghue --- .../platform/rockchip/rkcif/rkcif-capture-mipi.c | 695 +++++++++++++++++= ++++ .../platform/rockchip/rkcif/rkcif-capture-mipi.h | 2 + .../media/platform/rockchip/rkcif/rkcif-common.h | 16 + drivers/media/platform/rockchip/rkcif/rkcif-dev.c | 1 + .../platform/rockchip/rkcif/rkcif-interface.c | 5 +- drivers/media/platform/rockchip/rkcif/rkcif-regs.h | 24 +- 6 files changed, 741 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c b/d= rivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c index 0c3f7b8cfa18..5e1c624e17c6 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c @@ -6,22 +6,717 @@ * Copyright (C) 2025 Michael Riesch */ =20 +#include + +#include +#include +#include +#include +#include +#include +#include +#include + #include "rkcif-capture-mipi.h" #include "rkcif-common.h" +#include "rkcif-interface.h" +#include "rkcif-regs.h" #include "rkcif-stream.h" =20 +#define RKCIF_MIPI_CTRL0_COMPACT_EN BIT(6) +#define RKCIF_MIPI_CTRL0_CROP_EN BIT(5) +#define RKCIF_MIPI_CTRL0_TYPE(type) ((type) << 1) +#define RKCIF_MIPI_CTRL0_TYPE_RAW8 RKCIF_MIPI_CTRL0_TYPE(0x0) +#define RKCIF_MIPI_CTRL0_TYPE_RAW10 RKCIF_MIPI_CTRL0_TYPE(0x1) +#define RKCIF_MIPI_CTRL0_TYPE_RAW12 RKCIF_MIPI_CTRL0_TYPE(0x2) +#define RKCIF_MIPI_CTRL0_TYPE_RGB888 RKCIF_MIPI_CTRL0_TYPE(0x3) +#define RKCIF_MIPI_CTRL0_TYPE_YUV422SP RKCIF_MIPI_CTRL0_TYPE(0x4) +#define RKCIF_MIPI_CTRL0_TYPE_YUV420SP RKCIF_MIPI_CTRL0_TYPE(0x5) +#define RKCIF_MIPI_CTRL0_TYPE_YUV400 RKCIF_MIPI_CTRL0_TYPE(0x6) +#define RKCIF_MIPI_CTRL0_CAP_EN BIT(0) + +#define RKCIF_MIPI_INT_FRAME0_END(id) BIT(8 + (id) * 2 + 0) +#define RKCIF_MIPI_INT_FRAME1_END(id) BIT(8 + (id) * 2 + 1) + +static const struct rkcif_output_fmt mipi_out_fmts[] =3D { + /* YUV formats */ + { + .fourcc =3D V4L2_PIX_FMT_YUYV, + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .depth =3D 16, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_YUV422_8B, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_UYVY, + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .depth =3D 16, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_YUV422_8B, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_YVYU, + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .depth =3D 16, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_YUV422_8B, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_VYUY, + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .depth =3D 16, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_YUV422_8B, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + /* RGB formats */ + { + .fourcc =3D V4L2_PIX_FMT_RGB24, + .mbus_code =3D MEDIA_BUS_FMT_RGB888_1X24, + .depth =3D 24, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RGB888, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RGB888, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_BGR24, + .mbus_code =3D MEDIA_BUS_FMT_BGR888_1X24, + .depth =3D 24, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RGB888, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RGB888, + }, + }, + /* Bayer formats */ + { + .fourcc =3D V4L2_PIX_FMT_SBGGR8, + .mbus_code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .depth =3D 8, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW8, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG8, + .mbus_code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .depth =3D 8, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW8, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG8, + .mbus_code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .depth =3D 8, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW8, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB8, + .mbus_code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .depth =3D 8, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW8, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW8, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR10, + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR10P, + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG10, + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG10P, + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG10, + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG10P, + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB10, + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB10P, + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .depth =3D 10, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW10, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW10 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR12, + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SBGGR12P, + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG12, + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGBRG12P, + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG12, + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SGRBG12P, + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB12, + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_SRGGB12P, + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .depth =3D 12, + .cplanes =3D 1, + .mipi =3D { + .dt =3D MIPI_CSI2_DT_RAW12, + .ctrl0_val =3D RKCIF_MIPI_CTRL0_TYPE_RAW12 | RKCIF_MIPI_CTRL0_COMPACT_E= N, + }, + }, +}; + +static const struct rkcif_input_fmt mipi_in_fmts[] =3D { + /* YUV formats */ + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + }, + /* RGB formats */ + { + .mbus_code =3D MEDIA_BUS_FMT_RGB888_1X24, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_BGR888_1X24, + }, + /* Bayer formats */ + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + }, +}; + +const struct rkcif_mipi_match_data rkcif_rk3568_vicap_mipi_match_data =3D { + .mipi_num =3D 1, + .regs =3D { + [RKCIF_MIPI_CTRL] =3D 0x20, + [RKCIF_MIPI_INTEN] =3D 0xa4, + [RKCIF_MIPI_INTSTAT] =3D 0xa8, + }, + .regs_id =3D { + [RKCIF_ID0] =3D { + [RKCIF_MIPI_CTRL0] =3D 0x00, + [RKCIF_MIPI_CTRL1] =3D 0x04, + [RKCIF_MIPI_FRAME0_ADDR_Y] =3D 0x24, + [RKCIF_MIPI_FRAME0_ADDR_UV] =3D 0x2c, + [RKCIF_MIPI_FRAME0_VLW_Y] =3D 0x34, + [RKCIF_MIPI_FRAME0_VLW_UV] =3D 0x3c, + [RKCIF_MIPI_FRAME1_ADDR_Y] =3D 0x28, + [RKCIF_MIPI_FRAME1_ADDR_UV] =3D 0x30, + [RKCIF_MIPI_FRAME1_VLW_Y] =3D 0x38, + [RKCIF_MIPI_FRAME1_VLW_UV] =3D 0x40, + [RKCIF_MIPI_CROP_START] =3D 0xbc, + }, + [RKCIF_ID1] =3D { + [RKCIF_MIPI_CTRL0] =3D 0x08, + [RKCIF_MIPI_CTRL1] =3D 0x0c, + [RKCIF_MIPI_FRAME0_ADDR_Y] =3D 0x44, + [RKCIF_MIPI_FRAME0_ADDR_UV] =3D 0x4c, + [RKCIF_MIPI_FRAME0_VLW_Y] =3D 0x54, + [RKCIF_MIPI_FRAME0_VLW_UV] =3D 0x5c, + [RKCIF_MIPI_FRAME1_ADDR_Y] =3D 0x48, + [RKCIF_MIPI_FRAME1_ADDR_UV] =3D 0x50, + [RKCIF_MIPI_FRAME1_VLW_Y] =3D 0x58, + [RKCIF_MIPI_FRAME1_VLW_UV] =3D 0x60, + [RKCIF_MIPI_CROP_START] =3D 0xc0, + }, + [RKCIF_ID2] =3D { + [RKCIF_MIPI_CTRL0] =3D 0x10, + [RKCIF_MIPI_CTRL1] =3D 0x14, + [RKCIF_MIPI_FRAME0_ADDR_Y] =3D 0x64, + [RKCIF_MIPI_FRAME0_ADDR_UV] =3D 0x6c, + [RKCIF_MIPI_FRAME0_VLW_Y] =3D 0x74, + [RKCIF_MIPI_FRAME0_VLW_UV] =3D 0x7c, + [RKCIF_MIPI_FRAME1_ADDR_Y] =3D 0x68, + [RKCIF_MIPI_FRAME1_ADDR_UV] =3D 0x70, + [RKCIF_MIPI_FRAME1_VLW_Y] =3D 0x78, + [RKCIF_MIPI_FRAME1_VLW_UV] =3D 0x80, + [RKCIF_MIPI_CROP_START] =3D 0xc4, + }, + [RKCIF_ID3] =3D { + [RKCIF_MIPI_CTRL0] =3D 0x18, + [RKCIF_MIPI_CTRL1] =3D 0x1c, + [RKCIF_MIPI_FRAME0_ADDR_Y] =3D 0x84, + [RKCIF_MIPI_FRAME0_ADDR_UV] =3D 0x8c, + [RKCIF_MIPI_FRAME0_VLW_Y] =3D 0x94, + [RKCIF_MIPI_FRAME0_VLW_UV] =3D 0x9c, + [RKCIF_MIPI_FRAME1_ADDR_Y] =3D 0x88, + [RKCIF_MIPI_FRAME1_ADDR_UV] =3D 0x90, + [RKCIF_MIPI_FRAME1_VLW_Y] =3D 0x98, + [RKCIF_MIPI_FRAME1_VLW_UV] =3D 0xa0, + [RKCIF_MIPI_CROP_START] =3D 0xc8, + }, + }, + .blocks =3D { + { + .offset =3D 0x80, + }, + }, +}; + +static inline unsigned int rkcif_mipi_get_reg(struct rkcif_interface *inte= rface, + unsigned int index) +{ + struct rkcif_device *rkcif =3D interface->rkcif; + unsigned int block, offset, reg; + + block =3D interface->index - RKCIF_MIPI_BASE; + + if (WARN_ON_ONCE(block > RKCIF_MIPI_MAX - RKCIF_MIPI_BASE) || + WARN_ON_ONCE(index > RKCIF_MIPI_REGISTER_MAX)) + return RKCIF_REGISTER_NOTSUPPORTED; + + offset =3D rkcif->match_data->mipi->blocks[block].offset; + reg =3D rkcif->match_data->mipi->regs[index]; + if (reg =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return reg; + + return offset + reg; +} + +static inline unsigned int rkcif_mipi_id_get_reg(struct rkcif_stream *stre= am, + unsigned int index) +{ + struct rkcif_device *rkcif =3D stream->rkcif; + unsigned int block, id, offset, reg; + + block =3D stream->interface->index - RKCIF_MIPI_BASE; + id =3D stream->id; + + if (WARN_ON_ONCE(block > RKCIF_MIPI_MAX - RKCIF_MIPI_BASE) || + WARN_ON_ONCE(id > RKCIF_ID_MAX) || + WARN_ON_ONCE(index > RKCIF_MIPI_ID_REGISTER_MAX)) + return RKCIF_REGISTER_NOTSUPPORTED; + + offset =3D rkcif->match_data->mipi->blocks[block].offset; + reg =3D rkcif->match_data->mipi->regs_id[id][index]; + if (reg =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return reg; + + return offset + reg; +} + +static inline __maybe_unused void +rkcif_mipi_write(struct rkcif_interface *interface, unsigned int index, u3= 2 val) +{ + unsigned int addr =3D rkcif_mipi_get_reg(interface, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return; + + writel(val, interface->rkcif->base_addr + addr); +} + +static inline __maybe_unused void +rkcif_mipi_stream_write(struct rkcif_stream *stream, unsigned int index, + u32 val) +{ + unsigned int addr =3D rkcif_mipi_id_get_reg(stream, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return; + + writel(val, stream->rkcif->base_addr + addr); +} + +static inline __maybe_unused u32 +rkcif_mipi_read(struct rkcif_interface *interface, unsigned int index) +{ + unsigned int addr =3D rkcif_mipi_get_reg(interface, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return 0; + + return readl(interface->rkcif->base_addr + addr); +} + +static inline __maybe_unused u32 +rkcif_mipi_stream_read(struct rkcif_stream *stream, unsigned int index) +{ + unsigned int addr =3D rkcif_mipi_id_get_reg(stream, index); + + if (addr =3D=3D RKCIF_REGISTER_NOTSUPPORTED) + return 0; + + return readl(stream->rkcif->base_addr + addr); +} + +static void rkcif_mipi_queue_buffer(struct rkcif_stream *stream, + unsigned int index) +{ + struct rkcif_buffer *buffer =3D stream->buffers[index]; + u32 frm_addr_y, frm_addr_uv; + + frm_addr_y =3D index ? RKCIF_MIPI_FRAME1_ADDR_Y : + RKCIF_MIPI_FRAME0_ADDR_Y; + frm_addr_uv =3D index ? RKCIF_MIPI_FRAME1_ADDR_UV : + RKCIF_MIPI_FRAME0_ADDR_UV; + + rkcif_mipi_stream_write(stream, frm_addr_y, + buffer->buff_addr[RKCIF_PLANE_Y]); + rkcif_mipi_stream_write(stream, frm_addr_uv, + buffer->buff_addr[RKCIF_PLANE_UV]); +} + +static int rkcif_mipi_start_streaming(struct rkcif_stream *stream) +{ + struct rkcif_interface *interface =3D stream->interface; + const struct rkcif_output_fmt *active_out_fmt; + struct v4l2_subdev_state *state; + u32 ctrl0 =3D 0, ctrl1 =3D 0, int_temp =3D 0, int_mask =3D 0, vlw =3D 0; + u16 height, width; + int ret =3D -EINVAL; + + state =3D v4l2_subdev_lock_and_get_active_state(&interface->sd); + + active_out_fmt =3D rkcif_stream_find_output_fmt(stream, false, + stream->pix.pixelformat); + if (!active_out_fmt) + goto out; + + height =3D stream->pix.height; + width =3D stream->pix.width; + /* TODO there may be different factors and/or alignment constraints */ + vlw =3D ALIGN(width * 2, 8); + + ctrl0 |=3D active_out_fmt->mipi.dt << 10; + ctrl0 |=3D active_out_fmt->mipi.ctrl0_val; + ctrl0 |=3D RKCIF_MIPI_CTRL0_CROP_EN; + ctrl0 |=3D RKCIF_MIPI_CTRL0_CAP_EN; + + ctrl1 =3D RKCIF_XY_COORD(width, height); + + int_mask |=3D RKCIF_MIPI_INT_FRAME0_END(stream->id); + int_mask |=3D RKCIF_MIPI_INT_FRAME1_END(stream->id); + + int_temp =3D rkcif_mipi_read(interface, RKCIF_MIPI_INTEN); + int_temp |=3D int_mask; + rkcif_mipi_write(interface, RKCIF_MIPI_INTEN, int_temp); + + int_temp =3D rkcif_mipi_read(interface, RKCIF_MIPI_INTSTAT); + int_temp &=3D ~int_mask; + rkcif_mipi_write(interface, RKCIF_MIPI_INTSTAT, int_temp); + + rkcif_mipi_stream_write(stream, RKCIF_MIPI_FRAME0_VLW_Y, vlw); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_FRAME1_VLW_Y, vlw); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_FRAME0_VLW_UV, vlw); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_FRAME1_VLW_UV, vlw); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_CROP_START, 0x0); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_CTRL1, ctrl1); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_CTRL0, ctrl0); + + ret =3D 0; + +out: + v4l2_subdev_unlock_state(state); + return ret; +} + +static void rkcif_mipi_stop_streaming(struct rkcif_stream *stream) +{ + struct rkcif_interface *interface =3D stream->interface; + struct v4l2_subdev_state *state; + u32 int_temp =3D 0, int_mask =3D 0; + + state =3D v4l2_subdev_lock_and_get_active_state(&interface->sd); + + rkcif_mipi_stream_write(stream, RKCIF_MIPI_CTRL0, 0); + + int_mask |=3D RKCIF_MIPI_INT_FRAME0_END(stream->id); + int_mask |=3D RKCIF_MIPI_INT_FRAME1_END(stream->id); + + int_temp =3D rkcif_mipi_read(interface, RKCIF_MIPI_INTEN); + int_temp &=3D ~int_mask; + rkcif_mipi_write(interface, RKCIF_MIPI_INTEN, int_temp); + + int_temp =3D rkcif_mipi_read(interface, RKCIF_MIPI_INTSTAT); + int_temp &=3D ~int_mask; + rkcif_mipi_write(interface, RKCIF_MIPI_INTSTAT, int_temp); + + stream->stopping =3D false; + + v4l2_subdev_unlock_state(state); +} + +static void rkcif_mipi_set_crop(struct rkcif_stream *stream, u16 left, u16= top) +{ + u32 val; + + val =3D RKCIF_XY_COORD(left, top); + rkcif_mipi_stream_write(stream, RKCIF_MIPI_CROP_START, val); +} + irqreturn_t rkcif_mipi_isr(int irq, void *ctx) { + struct device *dev =3D ctx; + struct rkcif_device *rkcif =3D dev_get_drvdata(dev); irqreturn_t ret =3D IRQ_NONE; + u32 intstat; + + for (int i =3D 0; i < rkcif->match_data->mipi->mipi_num; i++) { + enum rkcif_interface_index index =3D RKCIF_MIPI_BASE + i; + struct rkcif_interface *interface =3D &rkcif->interfaces[index]; + + intstat =3D rkcif_mipi_read(interface, RKCIF_MIPI_INTSTAT); + rkcif_mipi_write(interface, RKCIF_MIPI_INTSTAT, intstat); + + for (int j =3D 0; j < interface->streams_num; j++) { + struct rkcif_stream *stream =3D &interface->streams[j]; + + if (intstat & RKCIF_MIPI_INT_FRAME0_END(stream->id) || + intstat & RKCIF_MIPI_INT_FRAME1_END(stream->id)) { + rkcif_stream_pingpong(stream); + ret =3D IRQ_HANDLED; + } + } + } =20 return ret; } =20 int rkcif_mipi_register(struct rkcif_device *rkcif) { + int ret, i; + + if (!rkcif->match_data->mipi) + return 0; + + for (i =3D 0; i < rkcif->match_data->mipi->mipi_num; i++) { + enum rkcif_interface_index index =3D RKCIF_MIPI_BASE + i; + struct rkcif_interface *interface =3D &rkcif->interfaces[index]; + + interface->index =3D index; + interface->type =3D RKCIF_IF_MIPI; + interface->in_fmts =3D mipi_in_fmts; + interface->in_fmts_num =3D ARRAY_SIZE(mipi_in_fmts); + interface->set_crop =3D rkcif_mipi_set_crop; + interface->streams_num =3D 0; + ret =3D rkcif_interface_register(rkcif, interface); + if (ret) + continue; + + for (int j =3D 0; j < RKCIF_ID_MAX; j++) { + struct rkcif_stream *stream =3D &interface->streams[j]; + + stream->id =3D j; + stream->interface =3D interface; + stream->out_fmts =3D mipi_out_fmts; + stream->out_fmts_num =3D ARRAY_SIZE(mipi_out_fmts); + stream->queue_buffer =3D rkcif_mipi_queue_buffer; + stream->start_streaming =3D rkcif_mipi_start_streaming; + stream->stop_streaming =3D rkcif_mipi_stop_streaming; + ret =3D rkcif_stream_register(rkcif, stream); + if (ret) + goto err; + interface->streams_num++; + } + } + return 0; + +err: + for (; i >=3D 0; i--) { + enum rkcif_interface_index index =3D RKCIF_MIPI_BASE + i; + struct rkcif_interface *interface =3D &rkcif->interfaces[index]; + + for (int j =3D 0; j < interface->streams_num; j++) + rkcif_stream_unregister(&interface->streams[j]); + + rkcif_interface_unregister(interface); + } + return ret; } =20 void rkcif_mipi_unregister(struct rkcif_device *rkcif) { + if (!rkcif->match_data->mipi) + return; + + for (int i =3D 0; i < rkcif->match_data->mipi->mipi_num; i++) { + enum rkcif_interface_index index =3D RKCIF_MIPI_BASE + i; + struct rkcif_interface *interface =3D &rkcif->interfaces[index]; + + for (int j =3D 0; j < interface->streams_num; j++) + rkcif_stream_unregister(&interface->streams[j]); + + rkcif_interface_unregister(interface); + } } diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h b/d= rivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h index ee1a50a59505..1248af70bdab 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.h @@ -11,6 +11,8 @@ =20 #include "rkcif-common.h" =20 +extern const struct rkcif_mipi_match_data rkcif_rk3568_vicap_mipi_match_da= ta; + int rkcif_mipi_register(struct rkcif_device *rkcif); =20 void rkcif_mipi_unregister(struct rkcif_device *rkcif); diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-common.h b/drivers= /media/platform/rockchip/rkcif/rkcif-common.h index 62fb3580eec5..d0d929648f21 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-common.h +++ b/drivers/media/platform/rockchip/rkcif/rkcif-common.h @@ -93,9 +93,14 @@ struct rkcif_output_fmt { u32 fourcc; u32 mbus_code; u8 cplanes; + u8 depth; =20 union { u32 dvp_fmt_val; + struct { + u8 dt; + u32 ctrl0_val; + } mipi; }; }; =20 @@ -183,6 +188,16 @@ struct rkcif_interface { void (*set_crop)(struct rkcif_stream *stream, u16 left, u16 top); }; =20 +struct rkcif_mipi_match_data { + unsigned int mipi_num; + unsigned int regs[RKCIF_MIPI_REGISTER_MAX]; + unsigned int regs_id[RKCIF_ID_MAX][RKCIF_MIPI_ID_REGISTER_MAX]; + + struct { + unsigned int offset; + } blocks[RKCIF_MIPI_MAX - RKCIF_MIPI_BASE]; +}; + struct rkcif_dvp_match_data { const struct rkcif_input_fmt *in_fmts; unsigned int in_fmts_num; @@ -198,6 +213,7 @@ struct rkcif_match_data { const char *const *clks; unsigned int clks_num; const struct rkcif_dvp_match_data *dvp; + const struct rkcif_mipi_match_data *mipi; }; =20 struct rkcif_device { diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-dev.c b/drivers/me= dia/platform/rockchip/rkcif/rkcif-dev.c index 2dcd35771fc9..1d8815156c46 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-dev.c +++ b/drivers/media/platform/rockchip/rkcif/rkcif-dev.c @@ -49,6 +49,7 @@ static const struct rkcif_match_data rk3568_vicap_match_d= ata =3D { .clks =3D rk3568_vicap_clks, .clks_num =3D ARRAY_SIZE(rk3568_vicap_clks), .dvp =3D &rkcif_rk3568_vicap_dvp_match_data, + .mipi =3D &rkcif_rk3568_vicap_mipi_match_data, }; =20 static const struct of_device_id rkcif_plat_of_match[] =3D { diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-interface.c b/driv= ers/media/platform/rockchip/rkcif/rkcif-interface.c index 0ec524586594..f598a62f9fbd 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-interface.c +++ b/drivers/media/platform/rockchip/rkcif/rkcif-interface.c @@ -188,7 +188,10 @@ static int rkcif_interface_enable_streams(struct v4l2_= subdev *sd, stream =3D &interface->streams[RKCIF_ID0]; rkcif_interface_apply_crop(stream, state); } else { - /* TODO implement for MIPI */ + for_each_active_route(&state->routing, route) { + stream =3D &interface->streams[route->sink_stream]; + rkcif_interface_apply_crop(stream, state); + } } =20 mask =3D v4l2_subdev_state_xlate_streams(state, RKCIF_IF_PAD_SINK, diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-regs.h b/drivers/m= edia/platform/rockchip/rkcif/rkcif-regs.h index 07fd64174e80..3d1f0c45c638 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-regs.h +++ b/drivers/media/platform/rockchip/rkcif/rkcif-regs.h @@ -30,7 +30,29 @@ enum rkcif_dvp_register_index { RKCIF_DVP_REGISTER_MAX }; =20 -#define RKCIF_REGISTER_NOTSUPPORTED 0x420000 +enum rkcif_mipi_register_index { + RKCIF_MIPI_CTRL, + RKCIF_MIPI_INTEN, + RKCIF_MIPI_INTSTAT, + RKCIF_MIPI_REGISTER_MAX +}; + +enum rkcif_mipi_id_register_index { + RKCIF_MIPI_CTRL0, + RKCIF_MIPI_CTRL1, + RKCIF_MIPI_FRAME0_ADDR_Y, + RKCIF_MIPI_FRAME0_ADDR_UV, + RKCIF_MIPI_FRAME0_VLW_Y, + RKCIF_MIPI_FRAME0_VLW_UV, + RKCIF_MIPI_FRAME1_ADDR_Y, + RKCIF_MIPI_FRAME1_ADDR_UV, + RKCIF_MIPI_FRAME1_VLW_Y, + RKCIF_MIPI_FRAME1_VLW_UV, + RKCIF_MIPI_CROP_START, + RKCIF_MIPI_ID_REGISTER_MAX +}; + +#define RKCIF_REGISTER_NOTSUPPORTED 0x420000 =20 #define RKCIF_FETCH_Y(VAL) ((VAL) & 0x1fff) =20 --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7410523504B; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; cv=none; b=snwnwo3/3xznxYXYNXDCaNrXa8JA3XOIGW5q/VOCzMWylWQTORu1HzHdLhMHq2x55ATjqsIH7ajPo6PFmfpN0p/mwIHM2ynMDIPaxpo6FhdiVpFqg/s8CWhOVY7+I8Z9dbLWuuWbiHL8inHvIJo3hpc37Haq2z8tfUIz1PZ9Jns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; c=relaxed/simple; bh=B5XjYTfglp+Es1h3q+EiooNvXOUXKpsC93FJIsCIIVE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:58 +0200 Subject: [PATCH v6 09/13] arm64: defconfig: enable rockchip camera interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-9-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=764; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=YywfWp66Y4vQTxzH3S912ReMsygZed8gsGkdLcdgxgY=; b=SOdhNT9BlY2fUd/dPSaj3UF/shCzwOoeaA8W402+CmaOdLhOQFiOMrJyElpFIq3h6bD877lhr rAjgMJvGS2xDMl0EUZrO+kARa05Gimvs+XsLlTdLTzdYvdfKMZ5sAaM X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip Camera Interface (CIF) is featured in many Rockchip SoCs in different variations. Enable the driver for it in the default configuration. Signed-off-by: Michael Riesch Reviewed-by: Bryan O'Donoghue --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..110ff52195a6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -858,6 +858,7 @@ CONFIG_VIDEO_RENESAS_FCP=3Dm CONFIG_VIDEO_RENESAS_FDP1=3Dm CONFIG_VIDEO_RENESAS_VSP1=3Dm CONFIG_VIDEO_RCAR_DRIF=3Dm +CONFIG_VIDEO_ROCKCHIP_CIF=3Dm CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=3Dm CONFIG_VIDEO_SAMSUNG_S5P_JPEG=3Dm CONFIG_VIDEO_SAMSUNG_S5P_MFC=3Dm --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6477235074; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; cv=none; b=H/8IgkDG1EN3qbSD+vKKBP5uhaFth56QrxESvL+Nknc/rD/BBXJDI9xPMQb1l5Gy1Ur28Q83XsS/iEJ/KLBLJugZfjxtrSwrFcrnGAe5CK9NDPPf1KCqrK6XWlZiV9iIht9pNFw6EJOlVintXib92zpLtSkpW7APel8IF41yGFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005265; c=relaxed/simple; bh=xgXsedVSUFwJxfdbZ+OMjnP+EyVsw+vIcIpvCuIoqpE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xx/JW1icGFPL+NtG7InG2otsGHK5RwqHTJpJwF4yD1CsOXKJE+/lZ3H0V9f+QHRipLT1HPgj7coOyDu9tDt9wy1o1nTaXFgQ3v5bp4It5wfvviN+PreP7zQOQX4n04bEox3Di9quAUVRsNb7XWe0DcnJCHxxKG5DXvhvSRbLvCA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eHeMYrWA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eHeMYrWA" Received: by smtp.kernel.org (Postfix) with ESMTPS id 44E19C4CEEC; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746005265; bh=xgXsedVSUFwJxfdbZ+OMjnP+EyVsw+vIcIpvCuIoqpE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eHeMYrWAO0KMQTb1lbhjZckcKL8zCkAFLGwFHWypikvZgR+z2HK+JW5lAlhUOAAsT klN4arw9U7aHfT8cqJy8zi3L90/uDDNdoX03IRSceFET7jcEQxZEBgGJXrPgGoGUbC dclWtx5Ya+yeXk4A8qGWVUN6DPpx1zSQ3jPWVNKdCHPSaCzc5ndrBxmimem/HVh5tr EDUHg3Lepq7pomgN3fDIg7rDbsfGKPewBgqSU1fX04/uAzuEhqou0ahLOt/Om3F3mu VLXPoMAOfU8tI9zNr84DWGGuCFulIBv9Mw4DZwkEPCpBkL0JLiG/yHi6gbei82VvmR scSlwKp0K6sCQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A5D2C3ABAD; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:15:59 +0200 Subject: [PATCH v6 10/13] arm64: dts: rockchip: add the vip node to px30 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-10-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch , Mehdi Djait X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=1272; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=frVH3YZJKlIZ2oOEYo9xSW4fg9sYwlZ7N9+sfEetpaM=; b=f/XlA9aKsmLgWN/s11bRRZ2pmxvczzmIR4HenT4pMoxd/Hl6M75U8CRfW0HIre0QNHeQrJ/Z3 HTEsXYWi0x/CXIAkccAYT1NekYgJ6lqW5ujJjFvXinDWPrdn+O/sVEX X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Mehdi Djait Add the device tree node for the PX30 Video Input Processor (VIP). Signed-off-by: Mehdi Djait [added cosmetic changes] Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/px30.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/r= ockchip/px30.dtsi index 9137dd76e72c..c2acf5952d08 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1282,6 +1282,18 @@ isp_mmu: iommu@ff4a8000 { #iommu-cells =3D <0>; }; =20 + cif: video-capture@ff490000 { + compatible =3D "rockchip,px30-vip"; + reg =3D <0x0 0xff490000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names =3D "aclk", "hclk", "pclk"; + power-domains =3D <&power PX30_PD_VI>; + resets =3D <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names =3D "axi", "ahb", "pclkin"; + status =3D "disabled"; + }; + qos_gmac: qos@ff518000 { compatible =3D "rockchip,px30-qos", "syscon"; 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Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:16:00 +0200 Subject: [PATCH v6 11/13] arm64: dts: rockchip: add vicap node to rk356x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-11-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=2050; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=lEu6UcdwUJ585mOVJj4+wXFbf1qt1nIxcP9Qq7FSezA=; b=9kHWHPvD7COocURldCYU2YJvQ4OOl8C6TIsThUOnkLdnb5lJGnjvjsaP7ztrntMneDpF+Coxi Ay55XofThONBV9GXitc7EyW/0TvuigvB59/xC+ZUSqnRLiPzywj8BHy X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add the device tree node for the RK356x Video Capture (VICAP) unit. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 44 +++++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index fd2214b6fad4..e0e4dc85a3a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -564,6 +564,50 @@ gpu: gpu@fde60000 { status =3D "disabled"; }; =20 + vicap: video-capture@fdfe0000 { + compatible =3D "rockchip,rk3568-vicap"; + reg =3D <0x0 0xfdfe0000 0x0 0x200>; + interrupts =3D ; + assigned-clocks =3D <&cru DCLK_VICAP>; + assigned-clock-rates =3D <300000000>; + clocks =3D <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names =3D "aclk", "hclk", "dclk", "iclk"; + iommus =3D <&vicap_mmu>; + power-domains =3D <&power RK3568_PD_VI>; + resets =3D <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names =3D "arst", "hrst", "drst", "prst", "irst"; + rockchip,grf =3D <&grf>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vicap_dvp: port@0 { + reg =3D <0>; + }; + + vicap_mipi: port@1 { + reg =3D <1>; + }; + }; + }; + + vicap_mmu: iommu@fdfe0800 { + compatible =3D "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdfe0800 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names =3D "aclk", "iface"; + #iommu-cells =3D <0>; + power-domains =3D <&power RK3568_PD_VI>; + rockchip,disable-mmu-reset; + status =3D "disabled"; + }; + vpu: video-codec@fdea0400 { compatible =3D "rockchip,rk3568-vpu"; reg =3D <0x0 0xfdea0000 0x0 0x800>; --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B657B235076; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-12-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=1513; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=n7SsQ0Jm8O3DWkSGx7UsFwouL+EV1n9f6o7pvgBiZes=; b=lzw29BwM3tPkfOdfKBg86jtDgvUqZAFVH/p8kgRrW4iML8dcwBQh6mVMnW27scM/bIG9zX2J2 s9auiD0AejAD5isRCKPOV6ATrHZZvxyjxfjIP1mGH33LkSZiAvadxkV X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add the device tree node for the RK356x MIPI CSI-2 Receiver. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 +++++++++++++++++++++++= ++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index e0e4dc85a3a9..a1eab57003f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -564,6 +564,33 @@ gpu: gpu@fde60000 { status =3D "disabled"; }; =20 + csi: csi@fdfb0000 { + compatible =3D "rockchip,rk3568-mipi-csi"; + reg =3D <0x0 0xfdfb0000 0x0 0x10000>; + clocks =3D <&cru PCLK_CSI2HOST1>; + phys =3D <&csi_dphy>; + power-domains =3D <&power RK3568_PD_VI>; + resets =3D <&cru SRST_P_CSI2HOST1>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi_in: port@0 { + reg =3D <0>; + }; + + csi_out: port@1 { + reg =3D <1>; + + csi_output: endpoint { + remote-endpoint =3D <&vicap_mipi_input>; + }; + }; + }; + }; + vicap: video-capture@fdfe0000 { compatible =3D "rockchip,rk3568-vicap"; reg =3D <0x0 0xfdfe0000 0x0 0x200>; @@ -592,6 +619,10 @@ vicap_dvp: port@0 { =20 vicap_mipi: port@1 { reg =3D <1>; + + vicap_mipi_input: endpoint { + remote-endpoint =3D <&csi_output>; + }; }; }; }; --=20 2.39.5 From nobody Fri Dec 19 18:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03DFD23C4F0; Wed, 30 Apr 2025 09:27:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005267; cv=none; b=hcoUo5WSkbBBhYgE/igY13HzdLXhc/taGrGMctf1jh26LIDvvuoTio8R/QfmAm47nl2UeTYimPWsN+KZ32zWMbDnFswRpQhyeHLVWY767+xm5VfPN7aQUzdqsYkiEtRK7k9+sIrs5bCyOjCFepCeHjmvuE07Z8eXoRy3OxBg3Ns= ARC-Message-Signature: i=1; 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b=XHD1g7mEXepkcqFEDjh0IvzjiGvi7eFktGPyg/MFqLn8bHqEDcA3Yb544xJ5wQKXb JP+sCrSdpDB9i33x5dor2boASRpkQjd7QB3kyRKznEgFDmwjMhYSyr4/xkJ4OYXAa4 exbkgba4Pf9x1L2BI0vIV3/Ycl50dyY0UL96tpKj3jGdVNvNmDxvfZqGqvjUQSoUn0 SFm3Dq4xRRIjP3bOiQAgh9U/nAx/80Ki67wN45M1f8aDWoVSg7EgVXrNRhgk/DtTH9 a67/KMOqOEV7EQ53vtRPgR7nRwGs1B97gEIMFjmr7Sxj57xLy572Dq6yrVzxowB0P6 8Qr9jhsqrmNLQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65511C3ABAD; Wed, 30 Apr 2025 09:27:45 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 30 Apr 2025 11:16:02 +0200 Subject: [PATCH v6 13/13] arm64: dts: rockchip: enable vicap dvp on wolfvision pf5 io expander Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v6-13-d2f5fbee1551@collabora.com> References: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v6-0-d2f5fbee1551@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Gerald Loacker , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746004564; l=1541; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=A46w67oMbroxqAcXCMQ9mjlreHO/teIN06ITNLENh64=; b=DNjWNIQuisPD8Z6OqpGmpAqpPC0hDoXzJO04Ec7Kajm4EErb2OOIEfBS83cMC0SVrDN6bR/cX OeR7cHJDynmB0Jnmki/i35gIkGyEoVsfqQl26P3BNbj7r8uEp4cHMhU X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Digital Video Port (DVP, the 16-bit variant) of the RK3568 VICAP is broken out to the PF5 mainboard expansion header. Enable it in the device tree overlay for the WolfVision PF5 IO Expander board. Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch --- .../rockchip/rk3568-wolfvision-pf5-io-expander.dtso | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander= .dtso b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso index 048933de2943..8cfce71dd318 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 &{/} { @@ -134,3 +135,22 @@ &usb2phy0_host { phy-supply =3D <&usb_host_vbus>; status =3D "okay"; }; + +&vicap { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; + status =3D "okay"; +}; + +&vicap_dvp { + vicap_dvp_input: endpoint { + bus-type =3D ; + bus-width =3D <16>; + pclk-sample =3D ; + rockchip,dvp-clk-delay =3D <10>; + }; +}; + +&vicap_mmu { + status =3D "okay"; +}; --=20 2.39.5