From nobody Tue Feb 10 00:00:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C885E314A88; Tue, 14 Oct 2025 13:02:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760446966; cv=none; b=snQLigCjoN00Js44PRMf39B+RGNFrWVAnakG9HdDLUT+vj1vfGL9VFh6mF27bXg3tuzmuMnY5DeUhxGq/BNSQ8mm5JxS+sE/KvD+RBdOGEOldbLak8L7YiYUPPXYFahs55fP81c2t8mqB25iUsceF9TvwPIzURr1h8UsUXAAKfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760446966; c=relaxed/simple; bh=wuzAERlHcFZ5qJ3fXg5vICyL/mdzCzcA8kaK/4vNPFk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gS/tiWVqUiRN77GacaCxwoBW51dmvsTAWqc7ErukyzOtdpk+LzOHj+pe4f8eAVnJgi+B1UlODRjNovvWpeNRrQGVIQO1Ha1Iw61MWNUzHehffCtXQYD1OtCttb7IYbgMxAMmsGDBGXnUy1uHTY4CmPhjRYAv1E29sf+/aeEttHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UIlw+Jd2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UIlw+Jd2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7A5EFC4CEF1; Tue, 14 Oct 2025 13:02:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760446966; bh=wuzAERlHcFZ5qJ3fXg5vICyL/mdzCzcA8kaK/4vNPFk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UIlw+Jd2gRjJpLhrMXIyGrs8ajveB+4BDvjWJqPdYQlvzJQTQuhJ1/9m8xWIcFM7d h86/E2bPQpoRZRRr24FN0IWCpOi3Of9ZahIKZY0eE0gTZDf7siXvi0nJf+2pybbkfG oqeEXf23LCsEBTn8EEuOWLwyXh9hQuUkkQ4EUMP3uQ+jnZ/ETMynI8mGAH81I30sGH qWzf+tfGjFSXJXTndkHnqCw8qJu6mq6tyENP+6hIv5dnDCkBzfhYYlnT2+T+6/hGg8 rXK3wd/11E7ve6foZFXESzYUwL0xxsJIk43h0fkVcfuZhsEGBeHoxdlwY9z2ei1ijA 2B2oYQmE+QPfQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 705A7CCD194; Tue, 14 Oct 2025 13:02:46 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 14 Oct 2025 15:01:57 +0200 Subject: [PATCH v12 11/18] media: rockchip: rkcif: add support for rk3568 vicap dvp capture Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v12-11-c6dbece6bb98@collabora.com> References: <20240220-rk3568-vicap-v12-0-c6dbece6bb98@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v12-0-c6dbece6bb98@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , Gerald Loacker , Bryan O'Donoghue , Markus Elfring , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760446963; l=10872; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=ZDvA55eFuTvHZDXBIDU39HmOOFX4CnFS7u4BodrXIAw=; b=LC9E8qKsniyCaw0BOrOpULlKzD8S/ofkBrCmonSj0HCiFGd2e6t5DDf6FczOcNzd6P4C4Hhw2 n/dO7AJPJfrByPfkg1GEb1mcrNgFYIhpGIWpUhwgc2Va6culD4HOxSS X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The RK3568 Video Capture (VICAP) unit features a Digital Video Port (DVP). Add support for it. Tested-by: Gerald Loacker Reviewed-by: Gerald Loacker Signed-off-by: Michael Riesch Reviewed-by: Mehdi Djait --- .../platform/rockchip/rkcif/rkcif-capture-dvp.c | 276 +++++++++++++++++= ++++ .../platform/rockchip/rkcif/rkcif-capture-dvp.h | 1 + drivers/media/platform/rockchip/rkcif/rkcif-dev.c | 1 + 3 files changed, 278 insertions(+) diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c b/dr= ivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c index b40135035ab8..dbaf7636aeeb 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c @@ -332,6 +332,282 @@ const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_= match_data =3D { }, }; =20 +static const struct rkcif_input_fmt rk3568_dvp_in_fmts[] =3D { + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type =3D RKCIF_FMT_TYPE_YUV, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_INPUT_MODE_BT1120 | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val =3D RKCIF_FORMAT_YUV_INPUT_422 | + RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU | + RKCIF_FORMAT_BT1120_YC_SWAP | + RKCIF_FORMAT_INPUT_MODE_BT1120, + .field =3D V4L2_FIELD_INTERLACED, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_RGB888_1X24, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y8_1X8, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y10_1X10, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, + { + .mbus_code =3D MEDIA_BUS_FMT_Y12_1X12, + .dvp_fmt_val =3D RKCIF_FORMAT_INPUT_MODE_RAW | + RKCIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type =3D RKCIF_FMT_TYPE_RAW, + .field =3D V4L2_FIELD_NONE, + }, +}; + +static void rk3568_dvp_grf_setup(struct rkcif_device *rkcif) +{ + u32 con1 =3D RK3568_GRF_WRITE_ENABLE(RK3568_GRF_VI_CON1_CIF_DATAPATH | + RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM); + + if (!rkcif->grf) + return; + + con1 |=3D rkcif->interfaces[RKCIF_DVP].dvp.dvp_clk_delay & + RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM; + + if (rkcif->interfaces[RKCIF_DVP].vep.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_DUALEDGE) + con1 |=3D RK3568_GRF_VI_CON1_CIF_DATAPATH; + + regmap_write(rkcif->grf, RK3568_GRF_VI_CON1, con1); +} + +const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data =3D { + .in_fmts =3D rk3568_dvp_in_fmts, + .in_fmts_num =3D ARRAY_SIZE(rk3568_dvp_in_fmts), + .out_fmts =3D dvp_out_fmts, + .out_fmts_num =3D ARRAY_SIZE(dvp_out_fmts), + .setup =3D rk3568_dvp_grf_setup, + .has_scaler =3D false, + .regs =3D { + [RKCIF_DVP_CTRL] =3D 0x00, + [RKCIF_DVP_INTEN] =3D 0x04, + [RKCIF_DVP_INTSTAT] =3D 0x08, + [RKCIF_DVP_FOR] =3D 0x0c, + [RKCIF_DVP_LINE_NUM_ADDR] =3D 0x2c, + [RKCIF_DVP_FRM0_ADDR_Y] =3D 0x14, + [RKCIF_DVP_FRM0_ADDR_UV] =3D 0x18, + [RKCIF_DVP_FRM1_ADDR_Y] =3D 0x1c, + [RKCIF_DVP_FRM1_ADDR_UV] =3D 0x20, + [RKCIF_DVP_VIR_LINE_WIDTH] =3D 0x24, + [RKCIF_DVP_SET_SIZE] =3D 0x28, + [RKCIF_DVP_CROP] =3D 0x34, + [RKCIF_DVP_FRAME_STATUS] =3D 0x3c, + [RKCIF_DVP_LAST_LINE] =3D 0x44, + [RKCIF_DVP_LAST_PIX] =3D 0x48, + }, +}; + static inline unsigned int rkcif_dvp_get_addr(struct rkcif_device *rkcif, unsigned int index) { diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h b/dr= ivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h index 7b2da11497c3..a4ed37833bd6 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h +++ b/drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h @@ -14,6 +14,7 @@ #include "rkcif-common.h" =20 extern const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_match_data; +extern const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data; =20 int rkcif_dvp_register(struct rkcif_device *rkcif); =20 diff --git a/drivers/media/platform/rockchip/rkcif/rkcif-dev.c b/drivers/me= dia/platform/rockchip/rkcif/rkcif-dev.c index 207802073fd3..addc118ff8bf 100644 --- a/drivers/media/platform/rockchip/rkcif/rkcif-dev.c +++ b/drivers/media/platform/rockchip/rkcif/rkcif-dev.c @@ -48,6 +48,7 @@ static const char *const rk3568_vicap_clks[] =3D { static const struct rkcif_match_data rk3568_vicap_match_data =3D { .clks =3D rk3568_vicap_clks, .clks_num =3D ARRAY_SIZE(rk3568_vicap_clks), + .dvp =3D &rkcif_rk3568_vicap_dvp_match_data, }; =20 static const struct of_device_id rkcif_plat_of_match[] =3D { --=20 2.39.5