From nobody Sat Oct 4 09:36:25 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 915A921A436; Mon, 18 Aug 2025 23:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755560387; cv=none; b=P9JedhapSMoPWRl29JuNyS32o/aTaH0pneNhrQifydqe2qhmlJ3RezmAgkQaeFtbZC3vIXebGMK9ujMxo0UGTix8SM7xdYkD73Vke5fRH1AdKoohA2T7U6C9qscRcyESnjbsvucqLCxORou5yO5Sl7mTJn8ws96g2u9CHzlrfeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755560387; c=relaxed/simple; bh=RX/P8k1BvqgYw6PMb4P6MZlDy6xA6NOugjHwP8dfba0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vm/4YaNcZQDOVwtbwEp+PKoquvxFkzPdzNt38pHy/aUn3cDxI5ewLpEPwhgVXnH0ZkzqsBh5svDCRi1Zkx+/KQRVxxOPv8iID3paV8cpkIqsBdMAe6TPj8KQYr2+pMmqLtXD2efOVWDkXlfkIuMrfPrQjwMlltEfT9zaj+wJkKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YffkCu9N; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YffkCu9N" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D757C19423; Mon, 18 Aug 2025 23:39:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755560387; bh=RX/P8k1BvqgYw6PMb4P6MZlDy6xA6NOugjHwP8dfba0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YffkCu9NdFOy0YYy5VAGcaVJwWkOzJCqEFpx7B1pqurhXJxIeBO6AKMroecudtFkY pSfGInNLsqKAEoxkmv1uvJl7ZFo0fzh+xBxxUppyZNPVulSmDinqNpmdVFPHx0dhi1 /3A1qlU0mJVwEApBM3LJ90V6nllKNlYso2U3PAJ29v81F0lALnAqJthgMwEDDBGrml xy3j/VFYvId+/cuqtmLtwshURajbkpSu7BMgLEfkS/DeJYjrqujCdnmyHCLlM+8m9Q r9A+CsTk3ZRLBBsIrWnZuaj1UCXnawHsRzLV1RccjiSi++5pR+AwWQLIVWll7oy4Yz 4pzkLMZf9JFGg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F583CA0EF5; Mon, 18 Aug 2025 23:39:47 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:25:55 +0200 Subject: [PATCH v10 03/13] media: dt-bindings: add rockchip px30 vip Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240220-rk3568-vicap-v10-3-62d8a7b209b4@collabora.com> References: <20240220-rk3568-vicap-v10-0-62d8a7b209b4@collabora.com> In-Reply-To: <20240220-rk3568-vicap-v10-0-62d8a7b209b4@collabora.com> To: Mehdi Djait , Maxime Chevallier , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , Gerald Loacker , Bryan O'Donoghue , Markus Elfring , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch , Michael Riesch , Mehdi Djait X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755559554; l=4307; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=tqAuE+nid1WViXUYdbDWjmQxpYwJ2/O9cYJjyQ7ycBo=; b=rz4Fh39pLz1bC/rg2KX8L+KOa95sSa2nNGVt2a5nc4BwymDZ5hUHwY8Lt8aDFpjUE/1tsZPPB fekMXNtwjwACo7h4OJcKM++PiazLJWJGOz58Jlj47+WiYcz+Z2uBMb5 X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Mehdi Djait Add documentation for the Rockchip PX30 Video Input Processor (VIP). Signed-off-by: Mehdi Djait [revised description] Reviewed-by: Rob Herring (Arm) Signed-off-by: Michael Riesch Signed-off-by: Michael Riesch Reviewed-by: Bryan O'Donoghue --- .../bindings/media/rockchip,px30-vip.yaml | 122 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 123 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml= b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml new file mode 100644 index 000000000000..9f7ab6965636 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Video Input Processor (VIP) + +maintainers: + - Mehdi Djait + - Michael Riesch + +description: + The Rockchip PX30 Video Input Processor (VIP) receives the data from a c= amera + sensor or CCIR656 encoder and transfers it into system main memory by AX= I bus. + +properties: + compatible: + const: rockchip,px30-vip + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port on the parallel interface + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: [5, 6] + + required: + - bus-type + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + video-capture@ff490000 { + compatible =3D "rockchip,px30-vip"; + reg =3D <0x0 0xff490000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names =3D "aclk", "hclk", "pclk"; + power-domains =3D <&power PX30_PD_VI>; + resets =3D <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CI= F_PCLKIN>; + reset-names =3D "axi", "ahb", "pclkin"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + cif_in: endpoint { + remote-endpoint =3D <&tw9900_out>; + bus-type =3D ; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0d2adf483426..356679cfdcaa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21768,6 +21768,7 @@ M: Michael Riesch L: linux-media@vger.kernel.org S: Maintained F: Documentation/admin-guide/media/rkcif* +F: Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml =20 ROCKCHIP CRYPTO DRIVERS M: Corentin Labbe --=20 2.39.5