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FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are available when on MP25 SoC, the 4 chip select are available. Signed-off-by: Christophe Kerello Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - commit message has been updated. .../bindings/mtd/st,stm32-fmc2-nand.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml = b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml index e72cb5bacaf0..b8ef9ba88e92 100644 --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml @@ -14,10 +14,11 @@ properties: enum: - st,stm32mp15-fmc2 - st,stm32mp1-fmc2-nfc + - st,stm32mp25-fmc2-nfc =20 reg: minItems: 6 - maxItems: 7 + maxItems: 12 =20 interrupts: maxItems: 1 @@ -92,6 +93,28 @@ allOf: - description: Chip select 1 command - description: Chip select 1 address space =20 + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2-nfc + then: + properties: + reg: + items: + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + required: - compatible - reg --=20 2.25.1 From nobody Sun Feb 8 10:22:03 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59FB1374EC; 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charset="utf-8" Use dma_get_slave_caps API to get the max burst size of a DMA channel. For MP1 SoCs, MDMA is used and the max burst size is 128. For MP25 SoC, DMA3 is used and the max burst size is 64. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 29 +++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index 88811139aaf5..a7db7b675514 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -264,6 +264,8 @@ struct stm32_fmc2_nfc { struct sg_table dma_ecc_sg; u8 *ecc_buf; int dma_ecc_len; + u32 tx_dma_max_burst; + u32 rx_dma_max_burst; =20 struct completion complete; struct completion dma_data_complete; @@ -347,20 +349,26 @@ static int stm32_fmc2_nfc_select_chip(struct nand_chi= p *chip, int chipnr) stm32_fmc2_nfc_setup(chip); stm32_fmc2_nfc_timings_init(chip); =20 - if (nfc->dma_tx_ch && nfc->dma_rx_ch) { + if (nfc->dma_tx_ch) { memset(&dma_cfg, 0, sizeof(dma_cfg)); - dma_cfg.src_addr =3D nfc->data_phys_addr[nfc->cs_sel]; dma_cfg.dst_addr =3D nfc->data_phys_addr[nfc->cs_sel]; - dma_cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; dma_cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_cfg.src_maxburst =3D 32; - dma_cfg.dst_maxburst =3D 32; + dma_cfg.dst_maxburst =3D nfc->tx_dma_max_burst / + dma_cfg.dst_addr_width; =20 ret =3D dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg); if (ret) { dev_err(nfc->dev, "tx DMA engine slave config failed\n"); return ret; } + } + + if (nfc->dma_rx_ch) { + memset(&dma_cfg, 0, sizeof(dma_cfg)); + dma_cfg.src_addr =3D nfc->data_phys_addr[nfc->cs_sel]; + dma_cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_cfg.src_maxburst =3D nfc->rx_dma_max_burst / + dma_cfg.src_addr_width; =20 ret =3D dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg); if (ret) { @@ -1545,6 +1553,7 @@ static int stm32_fmc2_nfc_setup_interface(struct nand= _chip *chip, int chipnr, =20 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) { + struct dma_slave_caps caps; int ret =3D 0; =20 nfc->dma_tx_ch =3D dma_request_chan(nfc->dev, "tx"); @@ -1557,6 +1566,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc= 2_nfc *nfc) goto err_dma; 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charset="utf-8" FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are available when on MP25 SoC, the 4 chip select are available. Let's use a platform data structure for parameters that will differ. Signed-off-by: Christophe Kerello --- Changes in v2: - V1 patch 10, 11 and 12 have been squashed and reworked. - a platform data structure is handling the difference between MP1 and MP2= 5. drivers/mtd/nand/raw/stm32_fmc2_nand.c | 54 +++++++++++++++++++++----- 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index a7db7b675514..264556939a00 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,7 @@ #define FMC2_MAX_SG 16 =20 /* Max chip enable */ -#define FMC2_MAX_CE 2 +#define FMC2_MAX_CE 4 =20 /* Max ECC buffer length */ #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) @@ -243,6 +244,13 @@ static inline struct stm32_fmc2_nand *to_fmc2_nand(str= uct nand_chip *chip) return container_of(chip, struct stm32_fmc2_nand, chip); } =20 +struct stm32_fmc2_nfc; + +struct stm32_fmc2_nfc_data { + int max_ncs; + int (*set_cdev)(struct stm32_fmc2_nfc *nfc); +}; + struct stm32_fmc2_nfc { struct nand_controller base; struct stm32_fmc2_nand nand; @@ -256,6 +264,7 @@ struct stm32_fmc2_nfc { phys_addr_t data_phys_addr[FMC2_MAX_CE]; struct clk *clk; u8 irq_state; + const struct stm32_fmc2_nfc_data *data; =20 struct dma_chan *dma_tx_ch; struct dma_chan *dma_rx_ch; @@ -1809,7 +1818,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fm= c2_nfc *nfc, return ret; } =20 - if (cs >=3D FMC2_MAX_CE) { + if (cs >=3D nfc->data->max_ncs) { dev_err(nfc->dev, "invalid reg value: %d\n", cs); return -EINVAL; } @@ -1915,9 +1924,17 @@ static int stm32_fmc2_nfc_probe(struct platform_devi= ce *pdev) nand_controller_init(&nfc->base); nfc->base.ops =3D &stm32_fmc2_nfc_controller_ops; =20 - ret =3D stm32_fmc2_nfc_set_cdev(nfc); - if (ret) - return ret; + nfc->data =3D of_device_get_match_data(dev); + if (!nfc->data) + return -EINVAL; + + if (nfc->data->set_cdev) { + ret =3D nfc->data->set_cdev(nfc); + if (ret) + return ret; + } else { + nfc->cdev =3D dev->parent; + } =20 ret =3D stm32_fmc2_nfc_parse_dt(nfc); if (ret) @@ -1936,7 +1953,7 @@ static int stm32_fmc2_nfc_probe(struct platform_devic= e *pdev) if (nfc->dev =3D=3D nfc->cdev) start_region =3D 1; =20 - for (chip_cs =3D 0, mem_region =3D start_region; chip_cs < FMC2_MAX_CE; + for (chip_cs =3D 0, mem_region =3D start_region; chip_cs < nfc->data->max= _ncs; chip_cs++, mem_region +=3D 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -2092,7 +2109,7 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struc= t device *dev) =20 stm32_fmc2_nfc_wp_disable(nand); =20 - for (chip_cs =3D 0; chip_cs < FMC2_MAX_CE; chip_cs++) { + for (chip_cs =3D 0; chip_cs < nfc->data->max_ncs; chip_cs++) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; =20 @@ -2105,9 +2122,28 @@ static int __maybe_unused stm32_fmc2_nfc_resume(stru= ct device *dev) static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, stm32_fmc2_nfc_resume); =20 +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data =3D { + .max_ncs =3D 2, + .set_cdev =3D stm32_fmc2_nfc_set_cdev, +}; + +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data =3D { + .max_ncs =3D 4, +}; + static const struct of_device_id stm32_fmc2_nfc_match[] =3D { - {.compatible =3D "st,stm32mp15-fmc2"}, - {.compatible =3D "st,stm32mp1-fmc2-nfc"}, + { + .compatible =3D "st,stm32mp15-fmc2", + .data =3D &stm32_fmc2_nfc_mp1_data, + }, + { + .compatible =3D "st,stm32mp1-fmc2-nfc", + .data =3D &stm32_fmc2_nfc_mp1_data, + }, + { + .compatible =3D "st,stm32mp25-fmc2-nfc", + .data =3D &stm32_fmc2_nfc_mp25_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); --=20 2.25.1