From nobody Mon Feb 9 09:09:46 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BC413714E; Mon, 19 Feb 2024 14:04:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708351462; cv=none; b=onnZs0BNm3zOuvpHwW7dEslVZ/CQZpX8MyiSBhNdoR5viWtfY/jS8/BmwcQsNEdr5rgW1QssYNtRW4AfRLa2ccBZmG46z/loP35sA174eiHamhIho/N1+cxkemdoDyW9YBCu5FoHv/CoQgeRlqTuExkDq0LA0xD85Q0CRvDe0dc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708351462; c=relaxed/simple; bh=qSHW6OPFfzummVILpOxuq+JfoUeFatluxX5C0qZHGJM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=npTII8uv8miImvPOAOLZpay7zM+DAvk3XzxTmfNwEwlMPsTKWabon7q+Y7JJBQjrqACnDH7h6m0/TPmL5Ebe4bV9GepefZWct3qwrxUr7kNhbOa2CVCmJmvxwypDYCtDuQ7yI0zYRsLhqw0g+ZQDdQOKJIrUyR8pn59lKl3kEs4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=uYzU1gCA; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="uYzU1gCA" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41JCq3Ql019021; Mon, 19 Feb 2024 15:04:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=V5cVkP9y2VaIJ3uCl8xeruMhCBitKczDbwJB0ezbja0=; b=uY zU1gCAiVi7ma/6XZ3M5Z/jBD4uMuoKzryZYqvXK8kg6lRdJWIdSOC0zEbH3qo1gk GFs+AcakN8Fv+IHNWSh+18lKo8z3B3mCiSDq6o/VhgCFv1cVOtus43i/Qm12kSrP bOXVaj3yKfv/4bbfOD2+5lZl8GBd5Rx6dz5i7qVvE0/qu8zeaD/LOI3urndCk5oi CsBg/4cqqAbAN0eT0sO+SNptNrEhcE4Qo+HhBjTay+osnZ9tbk98OGGr+dpi9YbY mNe5MbKugZ0vZOnqgBr+V+Wg2ri44+lou7642P59sIK4Tkx+bjoy1+eHShiAQa74 UJnbJ5hF4FOAzyya1kZg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3wak3m78gn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Feb 2024 15:04:14 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A681A40049; Mon, 19 Feb 2024 15:04:10 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5C39226A985; Mon, 19 Feb 2024 15:03:44 +0100 (CET) Received: from localhost (10.201.21.177) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 19 Feb 2024 15:03:44 +0100 From: Christophe Kerello To: , , , CC: , , , Christophe Kerello Subject: [PATCH v2 2/5] memory: stm32-fmc2-ebi: check regmap_read return value Date: Mon, 19 Feb 2024 15:01:59 +0100 Message-ID: <20240219140202.85680-3-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240219140202.85680-1-christophe.kerello@foss.st.com> References: <20240219140202.85680-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-19_10,2024-02-19_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Check regmap_read return value to avoid to use uninitialized local variables. Signed-off-by: Christophe Kerello --- Changes in v2: - New patch added drivers/memory/stm32-fmc2-ebi.c | 128 +++++++++++++++++++++++--------- 1 file changed, 94 insertions(+), 34 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index 47d0ea5f1616..6eacfbdd300c 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -181,8 +181,11 @@ static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_= ebi *ebi, int cs) { u32 bcr; + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 if (bcr & FMC2_BCR_MTYP) return 0; @@ -195,8 +198,11 @@ static int stm32_fmc2_ebi_check_waitcfg(struct stm32_f= mc2_ebi *ebi, int cs) { u32 bcr, val =3D FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 if ((bcr & FMC2_BCR_MTYP) =3D=3D val && bcr & FMC2_BCR_BURSTEN) return 0; @@ -209,8 +215,11 @@ static int stm32_fmc2_ebi_check_sync_trans(struct stm3= 2_fmc2_ebi *ebi, int cs) { u32 bcr; + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 if (bcr & FMC2_BCR_BURSTEN) return 0; @@ -223,8 +232,11 @@ static int stm32_fmc2_ebi_check_async_trans(struct stm= 32_fmc2_ebi *ebi, int cs) { u32 bcr; + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) return 0; @@ -237,8 +249,11 @@ static int stm32_fmc2_ebi_check_cpsize(struct stm32_fm= c2_ebi *ebi, int cs) { u32 bcr, val =3D FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 if ((bcr & FMC2_BCR_MTYP) =3D=3D val && bcr & FMC2_BCR_BURSTEN) return 0; @@ -251,12 +266,18 @@ static int stm32_fmc2_ebi_check_address_hold(struct s= tm32_fmc2_ebi *ebi, int cs) { u32 bcr, bxtr, val =3D FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); + int ret; + + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); if (prop->reg_type =3D=3D FMC2_REG_BWTR) - regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); + ret =3D regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); else - regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); + ret =3D regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); + if (ret) + return ret; =20 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) && ((bxtr & FMC2_BXTR_ACCMOD) =3D=3D val || bcr & FMC2_BCR_MUXEN)) @@ -270,12 +291,19 @@ static int stm32_fmc2_ebi_check_clk_period(struct stm= 32_fmc2_ebi *ebi, int cs) { u32 bcr, bcr1; + int ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); - if (cs) - regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); - else + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; + + if (cs) { + ret =3D regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); + if (ret) + return ret; + } else { bcr1 =3D bcr; + } =20 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) return 0; @@ -307,12 +335,18 @@ static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm= 32_fmc2_ebi *ebi, { u32 nb_clk_cycles =3D stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); u32 bcr, btr, clk_period; + int ret; + + ret =3D regmap_read(ebi->regmap, FMC2_BCR1, &bcr); + if (ret) + return ret; =20 - regmap_read(ebi->regmap, FMC2_BCR1, &bcr); if (bcr & FMC2_BCR1_CCLKEN || !cs) - regmap_read(ebi->regmap, FMC2_BTR1, &btr); + ret =3D regmap_read(ebi->regmap, FMC2_BTR1, &btr); else - regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + ret =3D regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + if (ret) + return ret; =20 clk_period =3D FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; =20 @@ -571,11 +605,16 @@ static int stm32_fmc2_ebi_set_address_setup(struct st= m32_fmc2_ebi *ebi, if (ret) return ret; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; + if (prop->reg_type =3D=3D FMC2_REG_BWTR) - regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); + ret =3D regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); else - regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); + ret =3D regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); + if (ret) + return ret; =20 if ((bxtr & FMC2_BXTR_ACCMOD) =3D=3D val || bcr & FMC2_BCR_MUXEN) val =3D clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX); @@ -693,11 +732,14 @@ static int stm32_fmc2_ebi_set_max_low_pulse(struct st= m32_fmc2_ebi *ebi, int cs, u32 setup) { u32 old_val, new_val, pcscntr; + int ret; =20 if (setup < 1) return 0; =20 - regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); + ret =3D regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); + if (ret) + return ret; =20 /* Enable counter for the bank */ regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, @@ -944,17 +986,26 @@ static void stm32_fmc2_ebi_disable_bank(struct stm32_= fmc2_ebi *ebi, int cs) regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0); } =20 -static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) +static int stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) { unsigned int cs; + int ret; =20 for (cs =3D 0; cs < FMC2_MAX_EBI_CE; cs++) { - regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); - regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); - regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); + if (ret) + return ret; + + ret =3D regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); + if (ret) + return ret; + + ret =3D regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); + if (ret) + return ret; } =20 - regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); + return regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); } =20 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) @@ -983,22 +1034,29 @@ static void stm32_fmc2_ebi_disable_banks(struct stm3= 2_fmc2_ebi *ebi) } =20 /* NWAIT signal can not be connected to EBI controller and NAND controller= */ -static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) +static int stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) { + struct device *dev =3D ebi->dev; unsigned int cs; u32 bcr; + int ret; =20 for (cs =3D 0; cs < FMC2_MAX_EBI_CE; cs++) { if (!(ebi->bank_assigned & BIT(cs))) continue; =20 - regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + ret =3D regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); + if (ret) + return ret; + if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && - ebi->bank_assigned & BIT(FMC2_NAND)) - return true; + ebi->bank_assigned & BIT(FMC2_NAND)) { + dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); + return -EINVAL; + } } =20 - return false; + return 0; } =20 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) @@ -1085,10 +1143,9 @@ static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2= _ebi *ebi) return -ENODEV; } =20 - if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) { - dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); - return -EINVAL; - } + ret =3D stm32_fmc2_ebi_nwait_used_by_ctrls(ebi); + if (ret) + return ret; =20 stm32_fmc2_ebi_enable(ebi); =20 @@ -1133,7 +1190,10 @@ static int stm32_fmc2_ebi_probe(struct platform_devi= ce *pdev) if (ret) goto err_release; =20 - stm32_fmc2_ebi_save_setup(ebi); + ret =3D stm32_fmc2_ebi_save_setup(ebi); + if (ret) + goto err_release; + platform_set_drvdata(pdev, ebi); =20 return 0; --=20 2.25.1