From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D07EA2C693 for ; Mon, 19 Feb 2024 11:21:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341716; cv=none; b=MfD2HEBJIdYwkU7fpFk1O8KWsfA2PLR6TXMkqkiCVXHUel2y2Ah2b+ibWeD+klleOsoRwsTbtQys1LjBNBexGt51oOE16V38WfLyYBPgrOOiaOVraiXxo8Rbxd72X7iuzB7mNCYh0fMXmyu5mRPw6RDOTkqQ6T1MYHnV3mcC1iw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341716; c=relaxed/simple; bh=FU4fhoGWvuGe6qI9myzpUIIpInnM2vTTQxC1ESzz82w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tu47pkt+j/8aCXsxkgq3I5cUn6ZItjXZfBXBBdbFZ5hs6eX3ClYVFeCiDxn9TsgdkPGesgDs21PAHO9y0V2y8U6pd1kNq0sI5owP+LimxvUM52/Lro+qAcURAB5fFUFCa6nPLtK/cYzBfplf8Aagztl4aXPEnKpT66hL800hMGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WdZKyfKu; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WdZKyfKu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708341715; x=1739877715; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FU4fhoGWvuGe6qI9myzpUIIpInnM2vTTQxC1ESzz82w=; b=WdZKyfKuTF7tRNL0utkI/BiM6S9ojPgiKh1aGLJ0Y0ksG7DWVYlHYnTl NXZXrmsKeNbAH5Pt5qEf6LymeOgE86Gj+ozOl8d9bHPdOwS2eF5S9kQ3m Ju/lhEyMvRTPzu1/p9bP/1FF4XB5kquZcmDyqnAKlU4yQLnpASHbt02A8 rdwLZSliJKEZOH/6gqgyIpJfdutlDLQK1JbxaZv3UVkLIfdgsw1jekPoD WXiyUn4Mm2Vd132VFEOzXDts26VtjDRjWIkQKukEEq2TwnDBglG02CWq1 jzNULSCucvg+/HVgjhKuXtz+67rzGV+q/pelA7FaKo1v3q1kPh4kjWGSq w==; X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823334" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823334" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:21:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826784" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:21:52 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] iommu/vt-d: Track nested domains in parent Date: Mon, 19 Feb 2024 19:15:52 +0800 Message-Id: <20240219111601.96405-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu Today the parent domain (s2_domain) is unaware of which DID's are used by and which devices are attached to nested domains (s1_domain) nested on it. This leads to a problem that some operations (flush iotlb/devtlb and enable dirty tracking) on parent domain only apply to DID's and devices directly tracked in the parent domain hence are incomplete. This tracks the nested domains in list in parent domain. With this, operations on parent domain can loop the nested domains and refer to the devices and iommu_array to ensure the operations on parent domain take effect on all the affected devices and iommus. Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-2-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 6 ++++++ drivers/iommu/intel/iommu.c | 18 ++++++++++++++---- drivers/iommu/intel/nested.c | 12 +++++++++++- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index d02f916d8e59..9b27edb73aa9 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -627,6 +627,10 @@ struct dmar_domain { int agaw; /* maximum mapped address */ u64 max_addr; + /* Protect the s1_domains list */ + spinlock_t s1_lock; + /* Track s1_domains nested on this domain */ + struct list_head s1_domains; }; =20 /* Nested user domain */ @@ -637,6 +641,8 @@ struct dmar_domain { unsigned long s1_pgtbl; /* page table attributes */ struct iommu_hwpt_vtd_s1 s1_cfg; + /* link to parent domain siblings */ + struct list_head s2_link; }; }; =20 diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 6fb5f6fceea1..e393c62776f3 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3883,6 +3883,7 @@ intel_iommu_domain_alloc_user(struct device *dev, u32= flags, bool dirty_tracking =3D flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; bool nested_parent =3D flags & IOMMU_HWPT_ALLOC_NEST_PARENT; struct intel_iommu *iommu =3D info->iommu; + struct dmar_domain *dmar_domain; struct iommu_domain *domain; =20 /* Must be NESTING domain */ @@ -3908,11 +3909,16 @@ intel_iommu_domain_alloc_user(struct device *dev, u= 32 flags, if (!domain) return ERR_PTR(-ENOMEM); =20 - if (nested_parent) - to_dmar_domain(domain)->nested_parent =3D true; + dmar_domain =3D to_dmar_domain(domain); + + if (nested_parent) { + dmar_domain->nested_parent =3D true; + INIT_LIST_HEAD(&dmar_domain->s1_domains); + spin_lock_init(&dmar_domain->s1_lock); + } =20 if (dirty_tracking) { - if (to_dmar_domain(domain)->use_first_level) { + if (dmar_domain->use_first_level) { iommu_domain_free(domain); return ERR_PTR(-EOPNOTSUPP); } @@ -3924,8 +3930,12 @@ intel_iommu_domain_alloc_user(struct device *dev, u3= 2 flags, =20 static void intel_iommu_domain_free(struct iommu_domain *domain) { + struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); + + WARN_ON(dmar_domain->nested_parent && + !list_empty(&dmar_domain->s1_domains)); if (domain !=3D &si_domain->domain) - domain_exit(to_dmar_domain(domain)); + domain_exit(dmar_domain); } =20 int prepare_domain_attach_device(struct iommu_domain *domain, diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index f26c7f1c46cc..6a75f6eb18f1 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -70,7 +70,13 @@ static int intel_nested_attach_dev(struct iommu_domain *= domain, =20 static void intel_nested_domain_free(struct iommu_domain *domain) { - kfree(to_dmar_domain(domain)); + struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); + struct dmar_domain *s2_domain =3D dmar_domain->s2_domain; + + spin_lock(&s2_domain->s1_lock); + list_del(&dmar_domain->s2_link); + spin_unlock(&s2_domain->s1_lock); + kfree(dmar_domain); } =20 static void nested_flush_dev_iotlb(struct dmar_domain *domain, u64 addr, @@ -201,5 +207,9 @@ struct iommu_domain *intel_nested_domain_alloc(struct i= ommu_domain *parent, spin_lock_init(&domain->lock); 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charset="utf-8" From: Yi Liu Add __iommu_flush_iotlb_psi() to do the psi iotlb flush with a DID input rather than calculating it within the helper. This is useful when flushing cache for parent domain which reuses DIDs of its nested domains. Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-3-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 78 ++++++++++++++++++++----------------- 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index e393c62776f3..dbdb8366c42a 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1368,6 +1368,46 @@ static void domain_flush_pasid_iotlb(struct intel_io= mmu *iommu, spin_unlock_irqrestore(&domain->lock, flags); } =20 +static void __iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, + unsigned long pfn, unsigned int pages, + int ih) +{ + unsigned int aligned_pages =3D __roundup_pow_of_two(pages); + unsigned long bitmask =3D aligned_pages - 1; + unsigned int mask =3D ilog2(aligned_pages); + u64 addr =3D (u64)pfn << VTD_PAGE_SHIFT; + + /* + * PSI masks the low order bits of the base address. If the + * address isn't aligned to the mask, then compute a mask value + * needed to ensure the target range is flushed. + */ + if (unlikely(bitmask & pfn)) { + unsigned long end_pfn =3D pfn + pages - 1, shared_bits; + + /* + * Since end_pfn <=3D pfn + bitmask, the only way bits + * higher than bitmask can differ in pfn and end_pfn is + * by carrying. This means after masking out bitmask, + * high bits starting with the first set bit in + * shared_bits are all equal in both pfn and end_pfn. + */ + shared_bits =3D ~(pfn ^ end_pfn) & ~bitmask; + mask =3D shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; + } + + /* + * Fallback to domain selective flush if no PSI support or + * the size is too big. + */ + if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) + iommu->flush.flush_iotlb(iommu, did, 0, 0, + DMA_TLB_DSI_FLUSH); + else + iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, + DMA_TLB_PSI_FLUSH); +} + static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, struct dmar_domain *domain, unsigned long pfn, unsigned int pages, @@ -1384,42 +1424,10 @@ static void iommu_flush_iotlb_psi(struct intel_iomm= u *iommu, if (ih) ih =3D 1 << 6; =20 - if (domain->use_first_level) { + if (domain->use_first_level) domain_flush_pasid_iotlb(iommu, domain, addr, pages, ih); - } else { - unsigned long bitmask =3D aligned_pages - 1; - - /* - * PSI masks the low order bits of the base address. If the - * address isn't aligned to the mask, then compute a mask value - * needed to ensure the target range is flushed. - */ - if (unlikely(bitmask & pfn)) { - unsigned long end_pfn =3D pfn + pages - 1, shared_bits; - - /* - * Since end_pfn <=3D pfn + bitmask, the only way bits - * higher than bitmask can differ in pfn and end_pfn is - * by carrying. This means after masking out bitmask, - * high bits starting with the first set bit in - * shared_bits are all equal in both pfn and end_pfn. - */ - shared_bits =3D ~(pfn ^ end_pfn) & ~bitmask; - mask =3D shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; - } - - /* - * Fallback to domain selective flush if no PSI support or - * the size is too big. - */ - if (!cap_pgsel_inv(iommu->cap) || - mask > cap_max_amask_val(iommu->cap)) - iommu->flush.flush_iotlb(iommu, did, 0, 0, - DMA_TLB_DSI_FLUSH); - else - iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, - DMA_TLB_PSI_FLUSH); - } + else + __iommu_flush_iotlb_psi(iommu, did, pfn, pages, ih); =20 /* * In caching mode, changes of pages from non-present to present require --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E1412C6B9 for ; Mon, 19 Feb 2024 11:21:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341721; cv=none; b=oubcB5nt/dVEBrSoMmkwVLWuDxNU9hVPvtcXb3w7+f7sOzlT1m90EoINcQJ0iy+1rJrj33/Ujtiix5KZfROukw2zcNVcQCiyv63WfHU0kG1IKlT0VN8//gDzrK3aQqM9l6ZNUvRn82/wQ0unWsVXM1yfO5/Dzk5BYeSWeaY9KHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341721; c=relaxed/simple; bh=wdo4y+teNsTSHhgxPZRjHIAgdvEhP4G9F49w7xcQvdM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z/LFRmW41T776k4ib7jrNGFPjGiZ3dDgHwjKf5Ajrxz6txfbpSVC3OzFqCaU1aaEFMvlDnVoNIlD9rHaVLAORpIBaNMSrmRH9RlJWzTD9vaYK8sbrMu49eaOVScYSOsu7aQYcQk7Tbysd8N1jZ+8Uw+UF8H7yvJaGRfdKbYlebc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PIu7a43C; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PIu7a43C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708341720; x=1739877720; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wdo4y+teNsTSHhgxPZRjHIAgdvEhP4G9F49w7xcQvdM=; b=PIu7a43CJOCZ6dAIk+AiUTwncLe19Yc7UxTY+0EvcNnR6Br7I0I3TztU I4hZRHXgHzaSgnFKttlH5iRDRKTI+m67vqbKMUGmD7aV5oaUaTCoNLxYZ WEjqyUfPrVMxv56V8IUwcQ9YuSdckwydaLhvJkB1hJv3rzzykfxb3Zc04 N/nRJQ2pWmVUpqIkxvf9/Dfi2oecRxl/0jbLrfBLSu33rGjCHkLylqz9J K3kBNVdg8n380Q73eeKj/G/dvehD0ZSls6o27dNUEG5zi/g5lkxHf0y7J FRtylH1+MFOzce4JKoyn0kPmx3iFed+2+vFLxJKu+D5nV5CaZQk/DFiuY w==; X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823353" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823353" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:22:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826813" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:21:57 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 03/10] iommu/vt-d: Add missing iotlb flush for parent domain Date: Mon, 19 Feb 2024 19:15:54 +0800 Message-Id: <20240219111601.96405-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu If a domain is used as the parent in nested translation its mappings might be cached using DID of the nested domain. But the existing code ignores this fact to only invalidate the iotlb entries tagged by the domain's own DID. Loop the s1_domains list, if any, to invalidate all iotlb entries related to the target s2 address range. According to VT-d spec there is no need for software to explicitly flush the affected s1 cache. It's implicitly done by HW when s2 cache is invalidated. Fixes: b41e38e22539 ("iommu/vt-d: Add nested domain allocation") Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-4-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index dbdb8366c42a..e3dbcae95975 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1451,6 +1451,28 @@ static void __mapping_notify_one(struct intel_iommu = *iommu, struct dmar_domain * iommu_flush_write_buffer(iommu); } =20 +/* + * Flush the relevant caches in nested translation if the domain + * also serves as a parent + */ +static void parent_domain_flush(struct dmar_domain *domain, + unsigned long pfn, + unsigned long pages, int ih) +{ + struct dmar_domain *s1_domain; + + spin_lock(&domain->s1_lock); + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { + struct iommu_domain_info *info; + unsigned long i; + + xa_for_each(&s1_domain->iommu_array, i, info) + __iommu_flush_iotlb_psi(info->iommu, info->did, + pfn, pages, ih); + } + spin_unlock(&domain->s1_lock); +} + static void intel_flush_iotlb_all(struct iommu_domain *domain) { struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); @@ -1470,6 +1492,9 @@ static void intel_flush_iotlb_all(struct iommu_domain= *domain) if (!cap_caching_mode(iommu->cap)) iommu_flush_dev_iotlb(dmar_domain, 0, MAX_AGAW_PFN_WIDTH); } + + if (dmar_domain->nested_parent) + parent_domain_flush(dmar_domain, 0, -1, 0); } =20 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) @@ -1993,6 +2018,9 @@ static void switch_to_super_page(struct dmar_domain *= domain, iommu_flush_iotlb_psi(info->iommu, domain, start_pfn, lvl_pages, 0, 0); + if (domain->nested_parent) + parent_domain_flush(domain, start_pfn, + lvl_pages, 0); } =20 pte++; @@ -4125,6 +4153,9 @@ static void intel_iommu_tlb_sync(struct iommu_domain = *domain, start_pfn, nrpages, list_empty(&gather->freelist), 0); =20 + if (dmar_domain->nested_parent) + parent_domain_flush(dmar_domain, start_pfn, nrpages, + list_empty(&gather->freelist)); put_pages_list(&gather->freelist); } =20 --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4E962C192 for ; Mon, 19 Feb 2024 11:22:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341724; cv=none; b=XmQ4QZRdz414eSJzrXRyRyWZkdMqUyxiCpUaD7/fqGjIvxyVvv3HzG+8BGdfUziEltKHYiOUcs8VQaF+m1Tjkwa62yo5dgMPgiG1KH2eips4SZLA2YhzuYqgWehbGwsax0SgLe+rDcyoRxMYiuU9344CMc8KpbNanu9VFVJilvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341724; c=relaxed/simple; bh=MrZgKSOW1tjC5BJ1Aj4vy1HeG1IeCVgQtjxOHw/lyVA=; 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charset="utf-8" From: Yi Liu Should call domain_update_iotlb() to update the has_iotlb_device flag of the domain after attaching device to nested domain. Without it, this flag is not set properly and would result in missing device TLB flush. Fixes: 9838f2bb6b6b ("iommu/vt-d: Set the nested domain to a device") Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-5-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 1 + drivers/iommu/intel/iommu.c | 4 +--- drivers/iommu/intel/nested.c | 2 ++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 9b27edb73aa9..4145c04cb1c6 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -1066,6 +1066,7 @@ int qi_submit_sync(struct intel_iommu *iommu, struct = qi_desc *desc, */ #define QI_OPT_WAIT_DRAIN BIT(0) =20 +void domain_update_iotlb(struct dmar_domain *domain); int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *io= mmu); void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *i= ommu); void device_block_translation(struct device *dev); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index e3dbcae95975..711c3e3fe095 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -396,8 +396,6 @@ static int domain_update_device_node(struct dmar_domain= *domain) return nid; } =20 -static void domain_update_iotlb(struct dmar_domain *domain); - /* Return the super pagesize bitmap if supported. */ static unsigned long domain_super_pgsize_bitmap(struct dmar_domain *domain) { @@ -1218,7 +1216,7 @@ domain_lookup_dev_info(struct dmar_domain *domain, return NULL; } =20 -static void domain_update_iotlb(struct dmar_domain *domain) +void domain_update_iotlb(struct dmar_domain *domain) { struct dev_pasid_info *dev_pasid; struct device_domain_info *info; diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index 6a75f6eb18f1..d5af5925a31c 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -65,6 +65,8 @@ static int intel_nested_attach_dev(struct iommu_domain *d= omain, list_add(&info->link, &dmar_domain->devices); spin_unlock_irqrestore(&dmar_domain->lock, flags); =20 + domain_update_iotlb(dmar_domain); + return 0; } =20 --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C6DA2D606 for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823369" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823369" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:22:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826834" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:22:02 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 05/10] iommu/vt-d: Add missing device iotlb flush for parent domain Date: Mon, 19 Feb 2024 19:15:56 +0800 Message-Id: <20240219111601.96405-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu ATS-capable devices cache the result of nested translation. This result relies on the mappings in s2 domain (a.k.a. parent). When there are modifications in the s2 domain, the related nested translation caches on the device should be flushed. This includes the devices that are attached to the s1 domain. However, the existing code ignores this fact to only loops its own devices. As there is no easy way to identify the exact set of nested translations affected by the change of s2 domain. So, this just flushes the entire device iotlb on the device. As above, driver loops the s2 domain's s1_domains list and loops the devices list of each s1_domain to flush the entire device iotlb on the devices. Fixes: b41e38e22539 ("iommu/vt-d: Add nested domain allocation") Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-6-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 711c3e3fe095..2eee83b5441b 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1461,12 +1461,30 @@ static void parent_domain_flush(struct dmar_domain = *domain, =20 spin_lock(&domain->s1_lock); list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { + struct device_domain_info *device_info; struct iommu_domain_info *info; + unsigned long flags; unsigned long i; =20 xa_for_each(&s1_domain->iommu_array, i, info) __iommu_flush_iotlb_psi(info->iommu, info->did, pfn, pages, ih); + + if (!s1_domain->has_iotlb_device) + continue; + + spin_lock_irqsave(&s1_domain->lock, flags); + list_for_each_entry(device_info, &s1_domain->devices, link) + /* + * Address translation cache in device side caches the + * result of nested translation. There is no easy way + * to identify the exact set of nested translations + * affected by a change in S2. So just flush the entire + * device cache. + */ + __iommu_flush_dev_iotlb(device_info, 0, + MAX_AGAW_PFN_WIDTH); + spin_unlock_irqrestore(&s1_domain->lock, flags); } spin_unlock(&domain->s1_lock); } --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8C6B2C1A6 for ; Mon, 19 Feb 2024 11:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341728; cv=none; b=sJO1mo/I7/Tf7AXwKCEB0boq3/TgrMtBT3X+LDTvNa71IwSeAy+NzDfoA/nvK3KgFr/M/r1FHy+ZBd/osaH0kEiYu0qnl8JR27peZKtfNMi3kggdqs6rdD4nnD8e4CNo2uXDcJgslRYyD/kSbF+SmcNszjcVPdf+xJJ68tmjlJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341728; c=relaxed/simple; bh=7Xq0FoTONpxLm9RWoF+B7SARgkpsA7bimB+gDd+Xbq0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RYydErpbGEsjh4SvceS/A/8EOGf2EEptQeoRPjY4lruZmHJUguCpbvqVHmj3H9KJgLZdP2LuNfaZ/ZkM4Od4/IdRNlK1BjXMJLNBsBi/Yge0AgnDEEdqtDyirqLvkWPNfBsQHfJXaywjbzS6Uu7IwNyOXB5TdhdjPT2W38lQb7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lIvOZoyL; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lIvOZoyL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708341727; x=1739877727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7Xq0FoTONpxLm9RWoF+B7SARgkpsA7bimB+gDd+Xbq0=; b=lIvOZoyL6ChB/TMoFlm5bqWyYSueZV1nP5HtHs4AI4pc0VnpsiaHUtor mmXkG41A3j9BJjrcttTbwy9mD0YoUDg5oHVYJuUbeVh/06wIGw10ZkmTP x53CONktxkaWxfgkr1B7ApM5Z9ZBNyKjGz3dpUyJ3ZdUU3TDgJwFCnUHz sj9WNHG5J5w6q0G3iX7sslFfMpBzr7FZhIlyh5Y/05BZ0crksd5vQD6xD yzJ2wIacrqea5w3AmhvCoDo7nSR97kc9UCz0Wi6yO5lLvW65AsGyKyj4f rvmNGatCGXM6+NZKNfMtWH2q0oo9J/NIOuuT0F5jXLVPXNfcTiNH8V49s w==; X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823381" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823381" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:22:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826846" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:22:04 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 06/10] iommu/vt-d: Remove domain parameter for intel_pasid_setup_dirty_tracking() Date: Mon, 19 Feb 2024 19:15:57 +0800 Message-Id: <20240219111601.96405-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu The only usage of input @domain is to get the domain id (DID) to flush cache after setting dirty tracking. However, DID can be obtained from the pasid entry. So no need to pass in domain. This can make this helper cleaner when adding the missing dirty tracking for the parent domain, which needs to use the DID of nested domain. Signed-off-by: Yi Liu Reviewed-by: Joao Martins Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-7-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.h | 1 - drivers/iommu/intel/iommu.c | 7 +++---- drivers/iommu/intel/pasid.c | 3 +-- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index 8d40d4c66e31..487ede039bdd 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -307,7 +307,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *= iommu, struct dmar_domain *domain, struct device *dev, u32 pasid); int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, - struct dmar_domain *domain, struct device *dev, u32 pasid, bool enabled); int intel_pasid_setup_pass_through(struct intel_iommu *iommu, diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2eee83b5441b..d286b8554227 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4741,8 +4741,7 @@ static int intel_iommu_set_dirty_tracking(struct iomm= u_domain *domain, goto out_unlock; =20 list_for_each_entry(info, &dmar_domain->devices, link) { - ret =3D intel_pasid_setup_dirty_tracking(info->iommu, - info->domain, info->dev, + ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, IOMMU_NO_PASID, enable); if (ret) goto err_unwind; @@ -4756,8 +4755,8 @@ static int intel_iommu_set_dirty_tracking(struct iomm= u_domain *domain, =20 err_unwind: list_for_each_entry(info, &dmar_domain->devices, link) - intel_pasid_setup_dirty_tracking(info->iommu, dmar_domain, - info->dev, IOMMU_NO_PASID, + intel_pasid_setup_dirty_tracking(info->iommu, info->dev, + IOMMU_NO_PASID, dmar_domain->dirty_tracking); spin_unlock(&dmar_domain->lock); return ret; diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 3239cefa4c33..a32d7e509842 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -428,7 +428,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *= iommu, * Set up dirty tracking on a second only or nested translation type. */ int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, - struct dmar_domain *domain, struct device *dev, u32 pasid, bool enabled) { @@ -445,7 +444,7 @@ int intel_pasid_setup_dirty_tracking(struct intel_iommu= *iommu, return -ENODEV; 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charset="utf-8" From: Yi Liu Add device_set_dirty_tracking() to loop all the devices and set the dirty tracking per the @enable parameter. Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Reviewed-by: Joao Martins Link: https://lore.kernel.org/r/20240208082307.15759-8-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index d286b8554227..2ad8fbe6dc21 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4729,23 +4729,38 @@ static void *intel_iommu_hw_info(struct device *dev= , u32 *length, u32 *type) return vtd; } =20 +/* + * Set dirty tracking for the device list of a domain. The caller must + * hold the domain->lock when calling it. + */ +static int device_set_dirty_tracking(struct list_head *devices, bool enabl= e) +{ + struct device_domain_info *info; + int ret =3D 0; + + list_for_each_entry(info, devices, link) { + ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, + IOMMU_NO_PASID, enable); + if (ret) + break; + } + + return ret; +} + static int intel_iommu_set_dirty_tracking(struct iommu_domain *domain, bool enable) { struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); - struct device_domain_info *info; int ret; =20 spin_lock(&dmar_domain->lock); if (dmar_domain->dirty_tracking =3D=3D enable) goto out_unlock; =20 - list_for_each_entry(info, &dmar_domain->devices, link) { - ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, - IOMMU_NO_PASID, enable); - if (ret) - goto err_unwind; - } + ret =3D device_set_dirty_tracking(&dmar_domain->devices, enable); + if (ret) + goto err_unwind; =20 dmar_domain->dirty_tracking =3D enable; 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19 Feb 2024 03:22:09 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 08/10] iommu/vt-d: Add missing dirty tracking set for parent domain Date: Mon, 19 Feb 2024 19:15:59 +0800 Message-Id: <20240219111601.96405-9-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu Setting dirty tracking for a s2 domain requires to loop all the related devices and set the dirty tracking enable bit in the PASID table entry. This includes the devices that are attached to the nested domains of a s2 domain if this s2 domain is used as parent. However, the existing dirty tracking set only loops s2 domain's own devices. It will miss dirty page logs in the parent domain. Now, the parent domain tracks the nested domains, so it can loop the nested domains and the devices attached to the nested domains to ensure dirty tracking on the parent is set completely. Fixes: b41e38e22539 ("iommu/vt-d: Add nested domain allocation") Signed-off-by: Yi Sun Signed-off-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240208082307.15759-9-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2ad8fbe6dc21..11652e0bcab3 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4748,6 +4748,35 @@ static int device_set_dirty_tracking(struct list_hea= d *devices, bool enable) return ret; } =20 +static int parent_domain_set_dirty_tracking(struct dmar_domain *domain, + bool enable) +{ + struct dmar_domain *s1_domain; + unsigned long flags; + int ret; + + spin_lock(&domain->s1_lock); + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { + spin_lock_irqsave(&s1_domain->lock, flags); + ret =3D device_set_dirty_tracking(&s1_domain->devices, enable); + spin_unlock_irqrestore(&s1_domain->lock, flags); + if (ret) + goto err_unwind; + } + spin_unlock(&domain->s1_lock); + return 0; + +err_unwind: + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { + spin_lock_irqsave(&s1_domain->lock, flags); + device_set_dirty_tracking(&s1_domain->devices, + domain->dirty_tracking); + spin_unlock_irqrestore(&s1_domain->lock, flags); + } + spin_unlock(&domain->s1_lock); + return ret; +} + static int intel_iommu_set_dirty_tracking(struct iommu_domain *domain, bool enable) { @@ -4762,6 +4791,12 @@ static int intel_iommu_set_dirty_tracking(struct iom= mu_domain *domain, if (ret) goto err_unwind; =20 + if (dmar_domain->nested_parent) { + ret =3D parent_domain_set_dirty_tracking(dmar_domain, enable); + if (ret) + goto err_unwind; + } + dmar_domain->dirty_tracking =3D enable; out_unlock: spin_unlock(&dmar_domain->lock); --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A5C52E84D for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823406" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823406" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:22:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826883" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:22:11 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 09/10] iommu/vt-d: Set SSADE when attaching to a parent with dirty tracking Date: Mon, 19 Feb 2024 19:16:00 +0800 Message-Id: <20240219111601.96405-10-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yi Liu Should set the SSADE (Second Stage Access/Dirty bit Enable) bit of the pasid entry when attaching a device to a nested domain if its parent has already enabled dirty tracking. Fixes: 111bf85c68f6 ("iommu/vt-d: Add helper to setup pasid nested translat= ion") Signed-off-by: Yi Liu Reviewed-by: Joao Martins Link: https://lore.kernel.org/r/20240208091414.28133-1-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index a32d7e509842..108158e2b907 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -657,6 +657,8 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu,= struct device *dev, pasid_set_domain_id(pte, did); pasid_set_address_width(pte, s2_domain->agaw); pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); + if (s2_domain->dirty_tracking) + pasid_set_ssade(pte); pasid_set_translation_type(pte, PASID_ENTRY_PGTT_NESTED); pasid_set_present(pte); spin_unlock(&iommu->lock); --=20 2.34.1 From nobody Mon Feb 9 05:53:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BEFB3306B for ; Mon, 19 Feb 2024 11:22:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341736; cv=none; b=qtVIT0LTQB9WHd0k2e5S7LUGluQK/DmKr7X3XzfGFfuhoe9OyBmbrYhU8uBJeUr5Y+TnO9C0zyaohq0DcAryKOlYsu3xWS9Hzkv4TJslVKJ/1Cjrj+CNa0G3+ytcQOBTSfV1HQz1Nh1VX4aoOdpRyXDJ9CA4qT+9CjhsWH/QZzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708341736; c=relaxed/simple; bh=fCI8ry2QwMgfpyT/VHftog8+K3+UurzhRMpjSws+ROQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oAgKo7yPd9pmWqs8kPY/V5/hm2AyB3x9hN/2zqpqb+tgrGwYA38fkzaZyvp+5GPnmOtBRVmqnzB+oMKmFeH0jJ7GNjbTxDaltp2pV3PVf53cp7pU7m3x4jyL7cV9cqb+VqmLt5kCMR7MWN9DcB4deqnpIJUAGln6FPzu5kemoZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q9rUbu3l; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q9rUbu3l" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708341736; x=1739877736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fCI8ry2QwMgfpyT/VHftog8+K3+UurzhRMpjSws+ROQ=; b=Q9rUbu3lKPUu0eElfh1wn1CmDlNipsWIkyeJe8yH204Y6lcOZbcR8Bn9 wS3SbaZ5/JkuZEeyUkaBHiRtUzStRuEEhoZw90O2+/T1WtBY8oISp9Y3F Ky68iGUfEUaJnPCAmVnTi3v0Xi81xC4PS7N0q0s7Joef+0FndxVFAEcf/ Y/OqJJCDTuoNuHskNHkN7JAmODSffOqNLB8c6O8mxCaj8u5OQrOYOTT2I Ac/rAulWhgNIo4pM4u2Z7mMdwjQv2csDPbxBpj6g4OSbRD//r8/7EvA8o f01UnuzGSlXimKTI+nfpi7y3nbiIxbFofERcF2M1KjEEMhksuQdWnp8J9 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="13823413" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="13823413" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 03:22:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4826892" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 19 Feb 2024 03:22:13 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Arnd Bergmann , Kevin Tian , Joao Martins , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 10/10] iommu/vt-d: Fix constant-out-of-range warning Date: Mon, 19 Feb 2024 19:16:01 +0800 Message-Id: <20240219111601.96405-11-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219111601.96405-1-baolu.lu@linux.intel.com> References: <20240219111601.96405-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann On 32-bit builds, the vt-d driver causes a warning with clang: drivers/iommu/intel/nested.c:112:13: error: result of comparison of constan= t 18446744073709551615 with expression of type 'unsigned long' is always fa= lse [-Werror,-Wtautological-constant-out-of-range-compare] 112 | if (npages =3D=3D U64_MAX) | ~~~~~~ ^ ~~~~~~~ Make the variable a 64-bit type, which matches both the caller and the use anyway. Fixes: f6f3721244a8 ("iommu/vt-d: Add iotlb flush for nested domain") Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20240213095832.455245-1-arnd@kernel.org Signed-off-by: Lu Baolu --- drivers/iommu/intel/nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index d5af5925a31c..a7d68f3d518a 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -103,7 +103,7 @@ static void nested_flush_dev_iotlb(struct dmar_domain *= domain, u64 addr, } =20 static void intel_nested_flush_cache(struct dmar_domain *domain, u64 addr, - unsigned long npages, bool ih) + u64 npages, bool ih) { struct iommu_domain_info *info; unsigned int mask; --=20 2.34.1