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charset="utf-8" From: Lucas Stach This adds the DT nodes for all the peripherals that make up the HDMI display pipeline. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V5: No change V3: Re-ordered the HDMI parts to properly come after irqstree_hdmi inside AIPS4. Change size of LCDIF3 and PVI to match TRM sizes of 4KB. V2: I took this from Lucas' original submission with the following: Removed extra clock from HDMI-TX since it is now part of the power domain Added interrupt-parent to PVI Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx Added ports to HDMI-tx --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 94 +++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index cbb15ded4a74..433ea4ae6a16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1940,6 +1940,100 @@ irqsteer_hdmi: interrupt-controller@32fc2000 { clock-names =3D "ipg"; power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible =3D "fsl,imx8mp-hdmi-pvi"; + reg =3D <0x32fc4000 0x1000>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <12>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint =3D <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg =3D <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint =3D <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible =3D "fsl,imx8mp-lcdif"; + reg =3D <0x32fc6000 0x1000>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <8>; + clocks =3D <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names =3D "pix", "axi", "disp_axi"; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint =3D <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible =3D "fsl,imx8mp-hdmi-tx"; + reg =3D <0x32fd8000 0x7eff>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <0>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + assigned-clocks =3D <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_266M>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width =3D <1>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint =3D <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg =3D <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible =3D "fsl,imx8mp-hdmi-phy"; + reg =3D <0x32fdff00 0x100>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names =3D "apb", "ref"; + assigned-clocks =3D <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents =3D <&clk IMX8MP_CLK_24M>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; }; =20 pcie: pcie@33800000 { --=20 2.43.0