From nobody Sat Feb 7 21:24:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21BD44EB55; Sun, 18 Feb 2024 12:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; cv=none; b=e8gRmK4Y1nUsqBS6FFmsBETH7cjckNJKNIaCIVSj1/DSLTvLG/2lu4tEdVNGWAIf0Z/CU5tbcbd+bZ51sMz3K5OYrntxINUspIoSE4iiEM4Miog+WHV65rPtAQkeqhPD/rxq/V1Cr8RIrQK9eD2poKiDkuivbP59RB6G1WAm9zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; c=relaxed/simple; bh=g/cYia/nzuVeyrMQsTsvao1OEQbnaDqgWqKJyaK7rY8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qMRzoxoVI1u1Q3PH+x45KYV1ehV5xJqCmHpsJ+KK9CCVIS+nymtDRyLuJhZSjhnUl9pdHsIfe8RpfHoJG2yhZP9083otTC71VPNuQc+eOe0andcwavK/rDbK4MGchpp0bAqb+T0ijY4h0sEMTGngnbchMtguwr+p/7IiLzBr8P0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OFgJRQUE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OFgJRQUE" Received: by smtp.kernel.org (Postfix) with ESMTPS id D1FF9C43390; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708257787; bh=g/cYia/nzuVeyrMQsTsvao1OEQbnaDqgWqKJyaK7rY8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OFgJRQUEY++TYLS206WQNO+jt8L+7q6Gmudd9RZLe1c7+gN92qdBgXuXcwkuyA9gA e3JIv5D1AgaCkpgLcNOBWtBhn2FhHMPFShzNQN2o9odSb7mJF8BRP77xFr4GfbzBe2 7g3SBGFOaKHtT5WazFISJ9SpUVOrQ79XU+YJdLH6sgIETN7J1Yh8st1m2jbpUgOLMW Ik5yO9/yNdW+GO7OCPgRNlenbcUNnug6L0JQLM4QX95msoTAEm6TkbeYnbgBgR5XvJ GWS2tZi63d4XFvuibZDiRVqrUN5LfNegxdxoUzO0XR1o7qG8xoLICqt6+Ga/8LcGgw 8nHU/gxmVDj7w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9F3DC54764; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 20:02:50 +0800 Subject: [PATCH v2 1/3] arm64: dts: hi3798cv200: fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240218-cache-v2-1-1fd919e2bd3e@outlook.com> References: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708257770; l=1243; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=cM/+jwZOd1PTjdjnQjIchbxxptzvx3CBS8/AnT/3vpc=; b=9ye8m+R+egKhjC5UJ+pb6xvl8IP230gTwbautYtnWhtxuD4VgdJgtFjSOfy8w1OnxjZ/Xfz/d 3/khw/OdTQlDHls8FP7JFJJ6nhA2eFmRHIk3RuxiJkK8AssUaCT5xFy X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen During boot, kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_f= orce_probe not set Looking at GIC-400 datasheet, I believe this SoC is using a regular GIC-400 and the GICR space size should be 8 KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-= poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/bo= ot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells =3D <0>; #interrupt-cells =3D <3>; interrupt-controller; --=20 2.43.0 From nobody Sat Feb 7 21:24:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6012863412; Sun, 18 Feb 2024 12:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; cv=none; b=lrtGJRoxzaK5Y+cC5EwBIId2xUBI4fxIIcxDh7sdTNMvPI2La0WttXYUB419iYFxLDqv5ZcK6kWfmpVQlSy5gd2PCf3kjSc7Bf2P3cVpFSwGgJ25C+4h0A+b2amT18LHgVdl7e1zEuttE79R1RPldZvJMvtGtYmBPi7rX83l4/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; c=relaxed/simple; bh=RPUmB8TnTdVoKukhHeVUW8RKPIT3OlUDg9hq4euJK94=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mvrzf89Xv1NgR2tomwzuBWcs/S14d+aDl6yRqZQ59AdH9fW9hl0mQQM++XucaKwxZbUfy3PWkPRl7aq1NsFgp6kQ8omdRbJXJyl/+Yuatb2z1FLlXMXwiyyroDIUfVhlNuaCJTOBXvqrNmqcDBmt0BXb8QWoG45FQoicrBbTUKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C10tmYII; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C10tmYII" Received: by smtp.kernel.org (Postfix) with ESMTPS id DDAEEC433C7; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708257787; bh=RPUmB8TnTdVoKukhHeVUW8RKPIT3OlUDg9hq4euJK94=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=C10tmYII47FOSk1mOrHEymRzoTTfZWyRW8oVUF4Q8g8a5ZlQk+Y6rT5vUJEArVCw8 OYm0Ko0x7HyVaRdow1RMMYUrWXT40KZydT5kOBtf8WGbMx3F3bqQm+KXuCh0NlxW7D EPJVf04LMYF7VIWlgVJ41EC8JLBOh0ZVUFmvuxMgzrE38xiic2FRYOQNT52pQSpWIQ OSMS+L/B+iyfyGQcjfv1YJveP/mqQJfzSe4DPdlT/hTSJ7279iBZa4lSIyPgd9QsQJ LaMb5bUk9+Z1BWO+nRZLj0FavZO6QW6Fp8JBtB6Ofae8b6DJoAGeYMlEea1WQSjosS 1o9iZvIUOTVlA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3F6EC54766; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 20:02:51 +0800 Subject: [PATCH v2 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240218-cache-v2-2-1fd919e2bd3e@outlook.com> References: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708257770; l=1117; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=oWPOXVSM7W5vHY31kDr4p2HrgQkuCpZx2sc6S9SlCF8=; b=YbBBZa81olla9r1dJqBTLzU5eZwlr9EMPAU11UChDqur5df31Kx/+zKUl+9eMR6I2jiXr8mlW b4PZ90CnhK9BmpzF3yRdh+HkmJCb9f7ZfAsvKVslY2q6zD8eJ4GMr4D X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen This is needed by KVM to make use of VGIC code. Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified. Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/bo= ot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..fc64d2fa99eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,11 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x2000>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts =3D ; #address-cells =3D <0>; #interrupt-cells =3D <3>; interrupt-controller; --=20 2.43.0 From nobody Sat Feb 7 21:24:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6017D634E3; Sun, 18 Feb 2024 12:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; cv=none; b=ID5dabY4jZKI8TiiS+5L3+npCWloaSfOXIe9CK4p5HLhSRi54OiXTH6yfOK9fD12zWn5pL6Sli5gGejLbSL6id725OkuPtcEzxUYtE6tSOiIkqNxVJ8T0U0CPFOZwLJBRhAUzg/+lU8U7u7Aw/zGB9azFJ1FN5E+XhvhsFzPUCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708257788; c=relaxed/simple; bh=2m0qq0O3uPCadp8spW3+jjkA33xPSYEwfEwk38XWt6I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SZWXS0fkUanqDfcyeNKLb+Nkfa0DsELHr5Yq5iDmPG+oXpQTP1esmZ2KC0dTONhHNhUYuoPfaxZA9fw2orY21ac7ixuJb0qmTSe9N1k2Gpcm238FG1PuBapHX8lRbNPlyyK/mYcXaZDZUhn9xuM1oxzcvkc1jjCYjeVKYj0hyOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s5j4LxXL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s5j4LxXL" Received: by smtp.kernel.org (Postfix) with ESMTPS id ED6E1C43394; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708257788; bh=2m0qq0O3uPCadp8spW3+jjkA33xPSYEwfEwk38XWt6I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=s5j4LxXLLlK6oe6Vr3Qi7HyMsudpzoibNLNHpiQbCNbhdRlZ3UqSQQdBed7NN1JdN LLP8Bf6oFr7C/EEDUUlrDwe+OF++yUEq9rzgTPf7JYJk/J15ahsoaCHJY62mnJr+FO JzrEXTjuZlpKzZM8xU0jXj7YrxFbeZEZHb2/wWnaeGGOFkavlK9m1CSoz6nJRldtYF OdY5+AY4Q5O8rjhrQg36n4dHq2lWKi09CKLCsqlAP7kdPLKkRsDJ2nd+8+wjw7YrDJ Mm1B6Y9bisFa3SjzHmLo5ul0TflLWxdRsrE7bJnrCs2jj1XPSNda7spGAjOTpyeEa5 Wgel0Y1mDf+lg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE386C5475B; Sun, 18 Feb 2024 12:03:07 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 20:02:52 +0800 Subject: [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240218-cache-v2-3-1fd919e2bd3e@outlook.com> References: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708257770; l=2811; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=JVX6c8jTFahxkecrZwVOU639nIRHmAeZFLG8nHeqRQM=; b=JfVOap8CG+9J+E/Wm9alsBTwAWzwAa30YeKl9pEufes8+h0zju2JexaoXi9zJ24xOTA6Ym/tx 3BKeMaXqBtQA/Lc5JcMCrWHU37OQ1tA6/S3j7lG/WBT03JlR3QilC2D X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-= poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/bo= ot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..0a9533786f50 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type =3D "cpu"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type =3D "cpu"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type =3D "cpu"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type =3D "cpu"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; }; =20 + L2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x80000>; /* 512 KiB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-level =3D <2>; + }; + gic: interrupt-controller@f1001000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0xf1001000 0x0 0x1000>, /* GICD */ --=20 2.43.0