From nobody Sat Feb 7 13:45:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3F7D168A7; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708249234; cv=none; b=VuXBMSvTZAI2W6Kzb2LvlJe/IsWeCBp1jx9LoYAg4M9rOzx9okWf/AYtq+Qn1bDcZDocvToblP5fmi1mSHm4Lgk/BnEtsoKRHfBQqS/z/SrXF7yT1YQdeP/A1vP5uERrG8dDrwpvFpGpDWWwl9n0bhDOjmfU/ZSBkspN9oZHoKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708249234; c=relaxed/simple; bh=g/cYia/nzuVeyrMQsTsvao1OEQbnaDqgWqKJyaK7rY8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Pz9wZEXXURRyzRHOFLa1TFEbWGbG1t4ndw7gZh0cEy1SzZxvfOefXVMz22KoeZZVZru0re3Qaosv7DaHiQK6ueexH9RaIt+f7g9LW5xQfN8EWHrs9Hr/peOMkIfDGkG9yU/zkmV/EvIgMaDm+w+01N57NR/8XHaj8b0pi9ZN6LQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L8mmDD7S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L8mmDD7S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D3BAC433C7; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708249234; bh=g/cYia/nzuVeyrMQsTsvao1OEQbnaDqgWqKJyaK7rY8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=L8mmDD7SjB9RkrGIg0nde0/NyvsttIMhJOhWW8hLYbczEOE0oJjsGSLZIWEo8V7n1 cl8PdsHVoVduSYaZsLrAyB3ZRmBSjj1QdYwROheQNqhEgoXp11H1hBOPfeFblHuwHi c35h4ZssPTxtZQuhiUBw760eeGbz4qUJYloZAQi8Ym9O0OA5Tpk2OtmWYF9d/oFkH9 G0jdLJJb5VeVtNi415ZHjQQXcHf50XdRpsQSwqoM4wvnpHe6EhwWqeTSChJgeyqj8i RMB+Per1R40CTH6VWoTzf+e86XFdoWXW2wC6OfB4kBWhQ21s7DSV6cSVGf62l+Oszg 0YqL7fx1HbBvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22B75C48BF8; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 17:40:30 +0800 Subject: [PATCH 1/2] arm64: dts: hi3798cv200: Fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240218-cache-v1-1-2c0a8a4472e7@outlook.com> References: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> In-Reply-To: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708249233; l=1243; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=cM/+jwZOd1PTjdjnQjIchbxxptzvx3CBS8/AnT/3vpc=; b=/A9JI75VcknvkbU5W9gkLRmoqf1WJh/ohHjKqGbIMBsKkkK/WPK5yfIjww3AcQbSkUzL8JDSV NrPoGdyLs04AXuPMwP/6CSlzS2G1hIP7BvdWXE43WyHj2CAK/4lqJ+l X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen During boot, kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_f= orce_probe not set Looking at GIC-400 datasheet, I believe this SoC is using a regular GIC-400 and the GICR space size should be 8 KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-= poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/bo= ot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells =3D <0>; #interrupt-cells =3D <3>; interrupt-controller; --=20 2.43.0 From nobody Sat Feb 7 13:45:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B97B149E02; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708249234; cv=none; b=ha9FGkQsZ2LCxtEMMm8lzrfH6dKjAvYIwUUzCTWtq1hlgSUB5/DFjoub6LA2K8i/lNHHge39gy+k+3+JaluhIPhG5BgUAetIvVvWH7ywRUyuWVhJO99iW5vAKHSnLoYXLAX1ePye0PEnMC9ZgO5MGf25erVCEnYBmHRB0r+4U2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708249234; c=relaxed/simple; bh=Bj/bQ2trWxsygHgiKr1seous7X6UroCh0ciTtTi41Fo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GKBJZpPLlslSrTo4qttr0Sem5p0GLEptyKH8KKs6Y4CylduWqXLBBKUMgacCNLAWXXio8jV8nZoN3bpuRuzNFKpjDUZsvdogOdV5x0RH+Cn3n2NgrEfEAVCmqZuZnZmXLeGUSlNMuA9mokiy8H1WiNg7E6c6y8N1CxBZ8083Y4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SCnzg6Dq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SCnzg6Dq" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4C0DFC43399; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708249234; bh=Bj/bQ2trWxsygHgiKr1seous7X6UroCh0ciTtTi41Fo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SCnzg6DqpN1VlV9sEoiPAv/1js7cezWgZLDm9Q5+6yGe0yQncX/dEzxhR5W6epVqz 56FB92JZlUGPurZgyQXxzEO2NIwXAN01Hx6SzwWFrr5EDhBwdUowQtzQppIfJ1jIRD 6L1JaZ92cmstDwfaBXKhd0rXk/yKOWPGduJ8gtJnb2YAUfesdRDasCecgUNZ6B3hHW BMch3/8/2wRQXqXjoLj68UPz9mdnIE4kFxY8ckl5saPnJ7YxBqnpeAg/+RcUZdul6/ 118bqLt7XzUKIlUCSdCX6z4fM8e6nobS1JNGd7luOg021dJqF68xy025ZBa725ar5M jWqbtniKbRe8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3595CC54764; Sun, 18 Feb 2024 09:40:34 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 17:40:31 +0800 Subject: [PATCH 2/2] arm64: dts: hi3798cv200: add cache info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240218-cache-v1-2-2c0a8a4472e7@outlook.com> References: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> In-Reply-To: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708249233; l=2811; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=7KtnkY7Pm5plqx77OK2FVNdCRnse/+VsWvkr9ingato=; b=JgA/U1XbhkecOKg3NeY5nWpK5pQs6KzWIhJQ7X5xYdZ3SEesjg9+XYCBOp0+LuD/DF19H6XYU Vv1JSbzdVzpDkyQ+MyZfC9+r5HMNAtIuLJYhviNxsTYQACEzr1IuWHB X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-= poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/bo= ot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..33ded6b97f61 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type =3D "cpu"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type =3D "cpu"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type =3D "cpu"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; =20 cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type =3D "cpu"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-size =3D <0x8000>; /* 32 KiB */ + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; /* 32 KiB */ + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; }; }; =20 + L2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x80000>; /* 512 KiB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-level =3D <2>; + }; + gic: interrupt-controller@f1001000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0xf1001000 0x0 0x1000>, /* GICD */ --=20 2.43.0