From nobody Sat Feb 7 07:10:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A19C7AE59; Sat, 17 Feb 2024 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; cv=none; b=kjRerAJu8BoLm1BE56UbOA/860nQdfuIQni1d3k0PS46W9WjSKJYJZZbN98lfci0R7e/G2PSfAcNQd3CrWPDdUn0W6S0ifgQH75Z21KjDJ8cPOIqfMhe1VjoKA1Kdn0JxMZv1sCxxpqi5CrEVADAlRqmbyjqUB90GOPwFsCIR5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; c=relaxed/simple; bh=fSZGw8CHrtheqHYmGL9yCRQ6avDh/svcGOMbahUkH18=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ci2eBOfsr22mxtWDwhU+fqu9wC0WG+cLaG6miqtj9q6Vob8Wnu2yPGZLLZk7WHaCTGJShF8Ppj+hRRZsgwYgy/gFsIbtcstBOG8/HdcXkijSqGQoLfVNTjrUWuDGjJF1WA4A7qyOv3zU9UXQZOoUW+KrEmOru9ulNikejjmPtfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ItWTLi+l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ItWTLi+l" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3434C43390; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708178572; bh=fSZGw8CHrtheqHYmGL9yCRQ6avDh/svcGOMbahUkH18=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ItWTLi+lum8ZgxobUsXJoYhEZ0KRb+0nQ+rcGAxenOSCuCYbFzjQQBvZTOnIg/NKs fs5pjwyV4A0e9cQr9ybl8LkPZCqw/aVSc+C9qo++Fpr4vm0WoHAARCFm5Y2prSsj8W yy7hHcw9C3KJcYCVeTQAdqY9GtmmpN1gwDMhF/2k0cgx0d8xfbPhYC6pLG4ARnJfl6 ibEtbzgmc5m5T6PVaVU8DAuQQAEqFqRkSwxOlNJGcAjU+OhqqqpTE0K2cWtq+79SLx GfUfqTzFmKdeUA4AK7o261QhnSk5eMdUerIsM9jxtGtoPUMRPwInkBO51Ini9NiU7w oUYMeRsdaggTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8FD9C54766; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:47 +0800 Subject: [PATCH RFC v2 3/4] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240217-inno-phy-v2-3-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=4896; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=GrCYJatgoRWu7Bx47GQoBXbcdNOq+uSu0U+veti+reE=; b=io0SbJNsSxMgQ3OaTc/0Z9tbTMuoUOoI7sFB5VfjG/ciOZl7aRIc2R0BYahKWoutI+NCTpO1B 377gjmMHMKGC9NMcLg0mt9uEo6KkEz1OM3+1O/B+KLbzoqsmWc1xz3t X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen Direct MMIO resgiter access is used by Hi3798MV200. For other models, of_iomap() returns 0 due to insufficient length. So they are unaffected. Also Hi3798MV200 INNO PHY has an extra reset required to be deasserted, switch to reset_control_bulk_() APIs to resolve this. Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 65 ++++++++++++++++++--------= ---- 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisil= icon/phy-hisi-inno-usb2.c index b7e740eb4752..5175e5a351ac 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ #define PHY_CLK_ENABLE BIT(2) =20 struct hisi_inno_phy_port { + void __iomem *base; struct reset_control *utmi_rst; struct hisi_inno_phy_priv *priv; }; @@ -50,7 +52,7 @@ struct hisi_inno_phy_port { struct hisi_inno_phy_priv { void __iomem *mmio; struct clk *ref_clk; - struct reset_control *por_rst; + struct reset_control *rsts; unsigned int type; struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; }; @@ -62,26 +64,31 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_ph= y_priv *priv, u32 val; u32 value; =20 - if (priv->type =3D=3D PHY_TYPE_0) - val =3D (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | - ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | - PHY0_TEST_WREN | PHY0_TEST_RST; - else - val =3D (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | - ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | - PHY1_TEST_WREN | PHY1_TEST_RST; - writel(val, reg); - - value =3D val; - if (priv->type =3D=3D PHY_TYPE_0) - value |=3D PHY0_TEST_CLK; - else - value |=3D PHY1_TEST_CLK; - writel(value, reg); - - writel(val, reg); + if (priv->ports[port].base) + // stride is 4 + writel(data, (u32 *)priv->ports[port].base + addr); + else { + if (priv->type =3D=3D PHY_TYPE_0) + val =3D (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | + PHY0_TEST_WREN | PHY0_TEST_RST; + else + val =3D (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | + PHY1_TEST_WREN | PHY1_TEST_RST; + writel(val, reg); + + value =3D val; + if (priv->type =3D=3D PHY_TYPE_0) + value |=3D PHY0_TEST_CLK; + else + value |=3D PHY1_TEST_CLK; + writel(value, reg); + + writel(val, reg); + } } =20 static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) @@ -104,7 +111,7 @@ static int hisi_inno_phy_init(struct phy *phy) return ret; udelay(REF_CLK_STABLE_TIME); =20 - reset_control_deassert(priv->por_rst); + reset_control_deassert(priv->rsts); udelay(POR_RST_COMPLETE_TIME); =20 /* Set up phy registers */ @@ -122,7 +129,7 @@ static int hisi_inno_phy_exit(struct phy *phy) struct hisi_inno_phy_priv *priv =3D port->priv; =20 reset_control_assert(port->utmi_rst); - reset_control_assert(priv->por_rst); + reset_control_assert(priv->rsts); clk_disable_unprepare(priv->ref_clk); =20 return 0; @@ -158,15 +165,16 @@ static int hisi_inno_phy_probe(struct platform_device= *pdev) if (IS_ERR(priv->ref_clk)) return PTR_ERR(priv->ref_clk); =20 - priv->por_rst =3D devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(priv->por_rst)) - return PTR_ERR(priv->por_rst); + priv->rsts =3D devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->rsts)) + return PTR_ERR(priv->rsts); =20 priv->type =3D (uintptr_t) of_device_get_match_data(dev); =20 for_each_child_of_node(np, child) { struct reset_control *rst; struct phy *phy; + void __iomem *base; =20 rst =3D of_reset_control_get_exclusive(child, NULL); if (IS_ERR(rst)) { @@ -174,7 +182,10 @@ static int hisi_inno_phy_probe(struct platform_device = *pdev) return PTR_ERR(rst); } =20 + base =3D of_iomap(child, 0); + priv->ports[i].utmi_rst =3D rst; + priv->ports[i].base =3D base; priv->ports[i].priv =3D priv; =20 phy =3D devm_phy_create(dev, child, &hisi_inno_phy_ops); @@ -205,6 +216,8 @@ static const struct of_device_id hisi_inno_phy_of_match= [] =3D { .data =3D (void *) PHY_TYPE_0 }, { .compatible =3D "hisilicon,hi3798mv100-usb2-phy", .data =3D (void *) PHY_TYPE_1 }, + { .compatible =3D "hisilicon,hi3798mv200-usb2-phy", + .data =3D (void *) PHY_TYPE_0 }, { }, }; MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match); --=20 2.43.0