From nobody Sat Feb 7 07:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A0C36A025; Sat, 17 Feb 2024 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; cv=none; b=nJj/USXin7ieCxrjCAeqOyE9MDuxC6M0TBngvt5T1qcXDNAqcpOtbE7BWOy2ncRylLNnYyeubkF10rwSlp05orfQyeTtnu8b7AJ3qLOHOPieJ4N2J73Qvl+DffnvlpywDgllf8LUmZF07sOPx2EJrmULxHr/1mRKi/FGyIZJ5d0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; c=relaxed/simple; bh=lHIkP93cp1wiDLjkwEfV9tYxAmOs3XojUDO3LQnSIYM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EpX01ITjf76UYNEINTZTn81nx7p/DsSQ7HJO/RnWBrCzuJvXZ8NTUVQEGdx7+ArrtbZlohGowV/0Smh0CYDWPOdnVvlu7oYEoLtTrD26EV3Y70JGiEITQ+UXdpMqInq1uYMEIaI/LOBNAK+x7oRhpuf5haqk2wD2VnQIE5NQ0Iw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GTgul5cy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GTgul5cy" Received: by smtp.kernel.org (Postfix) with ESMTPS id DFD1BC433F1; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708178571; bh=lHIkP93cp1wiDLjkwEfV9tYxAmOs3XojUDO3LQnSIYM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GTgul5cyvQdPbZPbhuN5izLHjM13A4ABYWjWdg+LbgNu0QDP5uwGTzd7MpynWHc2l 9TRKh5vBOXzgnk3/PwaizCAYM1FySQG4Qw6/B3/E0p/+40i5sKNbMPotx1hbPIGmkd /KZryMaPdyO6UNXRwJwxGD1rRafxcdc8BanwsOTWfkMiyNDWPF5SjKahf6/wk5XCf3 Mtznp6RBCx73JMoVSh+UmPXBxHqLCuEktIYcz3ARnwtMLgqQK1zMy2bwdpirQj3NZK KGMfWNCWUypIJJcflhiFToWZCG72H1rOshLZcS+7YB/LkKqHVMtw6l1A+GKDzNg/qU xd0bBvV3rWRzA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2EFEC48BF8; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:45 +0800 Subject: [PATCH RFC v2 1/4] dt-bindings: phy: hisi-inno-usb2: convert to YAML Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240217-inno-phy-v2-1-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=5202; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=S10kxyAA+0zcLslyAPap5mw+bF2BBsabAHscvCgNtfw=; b=Y3S+hsOizkFLpagFOiUB+KQ7SpeWsONjf/SpDIki3AlBiNOnu9nBJZYogmDnIhD0TAF9otXJR dnBndRX/FHGD9sc0kzZaX7bMFMWEI9OMH/+9Imoj7N0yHbnI2pGRZ/7 X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen Also rename to hisilicon,inno-usb2-phy.yaml and add this name to compatible lists. Signed-off-by: Yang Xiwen --- .../bindings/phy/hisilicon,inno-usb2-phy.yaml | 95 ++++++++++++++++++= ++++ .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 71 ---------------- 2 files changed, 95 insertions(+), 71 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.= yaml b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml new file mode 100644 index 000000000000..bfbda1568557 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon HiSTB SoCs INNO USB2 PHY device + +maintainers: + - Yang Xiwen + +properties: + compatible: + minItems: 1 + items: + - enum: + - hisilicon,hi3798cv200-usb2-phy + - hisilicon,hi3798mv100-usb2-phy + - const: hisilicon,inno-usb2-phy + + reg: + maxItems: 1 + description: | + Should be the address space for PHY configuration register in periph= eral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. + Or direct MMIO address space. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + maxItems: 1 + description: reference clock + + resets: + maxItems: 1 + +patternProperties: + 'phy@[0-9a-f]+': + type: object + additionalProperties: false + description: individual ports provided by INNO PHY + + properties: + reg: + maxItems: 1 + + '#phy-cells': + const: 0 + + resets: + maxItems: 1 + + required: + - reg + - '#phy-cells' + - resets + +required: + - compatible + - clocks + - reg + - '#address-cells' + - '#size-cells' + - resets + +additionalProperties: false + +examples: + - | + #include + + usb2-phy@120 { + compatible =3D "hisilicon,hi3798cv200-usb2-phy"; + reg =3D <0x120 0x4>; + clocks =3D <&crg HISTB_USB2_PHY1_REF_CLK>; + resets =3D <&crg 0xbc 4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + resets =3D <&crg 0xbc 8>; + }; + + phy@1 { + reg =3D <1>; + #phy-cells =3D <0>; + resets =3D <&crg 0xbc 9>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b= /Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt deleted file mode 100644 index 104953e849e7..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt +++ /dev/null @@ -1,71 +0,0 @@ -Device tree bindings for HiSilicon INNO USB2 PHY - -Required properties: -- compatible: Should be one of the following strings: - "hisilicon,inno-usb2-phy", - "hisilicon,hi3798cv200-usb2-phy". -- reg: Should be the address space for PHY configuration register in perip= heral - controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. -- clocks: The phandle and clock specifier pair for INNO USB2 PHY device - reference clock. -- resets: The phandle and reset specifier pair for INNO USB2 PHY device re= set - signal. -- #address-cells: Must be 1. -- #size-cells: Must be 0. - -The INNO USB2 PHY device should be a child node of peripheral controller t= hat -contains the PHY configuration register, and each device supports up to 2 = PHY -ports which are represented as child nodes of INNO USB2 PHY device. - -Required properties for PHY port node: -- reg: The PHY port instance number. -- #phy-cells: Defined by generic PHY bindings. Must be 0. -- resets: The phandle and reset specifier pair for PHY port reset signal. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - -perictrl: peripheral-controller@8a20000 { - compatible =3D "hisilicon,hi3798cv200-perictrl", "simple-mfd"; - reg =3D <0x8a20000 0x1000>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0x0 0x8a20000 0x1000>; - - usb2_phy1: usb2-phy@120 { - compatible =3D "hisilicon,hi3798cv200-usb2-phy"; - reg =3D <0x120 0x4>; - clocks =3D <&crg HISTB_USB2_PHY1_REF_CLK>; - resets =3D <&crg 0xbc 4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - usb2_phy1_port0: phy@0 { - reg =3D <0>; - #phy-cells =3D <0>; - resets =3D <&crg 0xbc 8>; - }; - - usb2_phy1_port1: phy@1 { - reg =3D <1>; - #phy-cells =3D <0>; - resets =3D <&crg 0xbc 9>; - }; - }; - - usb2_phy2: usb2-phy@124 { - compatible =3D "hisilicon,hi3798cv200-usb2-phy"; - reg =3D <0x124 0x4>; - clocks =3D <&crg HISTB_USB2_PHY2_REF_CLK>; - resets =3D <&crg 0xbc 6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - usb2_phy2_port0: phy@0 { - reg =3D <0>; - #phy-cells =3D <0>; - resets =3D <&crg 0xbc 10>; - }; - }; -}; --=20 2.43.0 From nobody Sat Feb 7 07:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A1D77AE67; Sat, 17 Feb 2024 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; cv=none; b=e7BXx/XlYmeMyBXiBd3eH8DGa1Zoi7CFl+G27PDK9o7mSEDnagGrhWthKLcMVWx5IirgTNTBenW89WFC5XI7vz7N2iEnYBGubeAZ9qPEbcp9ZraGmuPM0LtGWTMF+IdRe7Hhxrxr9kVbIafgpU3jFxA9rNGHeRl1zxcJIgzDykw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; c=relaxed/simple; bh=esSfqR/EN2uGgQJhZInB3gQ5IgggyIpQkCwvAPI4KIE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=anAfbsWuO/rwzOs1Uo8eLXURK2Yfnee/O6otb7zpezie784HVB0E1OSSFq9NKbaGDfV1hBhIXlEbEZgLbbgfRCtizgdK4mZJN+R9tGf4BGZDARjhzFjQm/kcQT6mJpXprsz1q1FX5GZeQFYpofIwqh1QDX/AH8sSNNfiOJQQksg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NT9Ie+1H; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NT9Ie+1H" Received: by smtp.kernel.org (Postfix) with ESMTPS id E80FCC43394; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708178572; bh=esSfqR/EN2uGgQJhZInB3gQ5IgggyIpQkCwvAPI4KIE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NT9Ie+1HH/Cgr/s1+RKuwi4xdU2skqzHG2qBu26n9RRbxJKVD0GbkXXWj02Q9Cufm 2rsDWa+ojQLiL++Wx4LVU8C0hsecTcFqnvfDl0xvfhUeK+Osf+uzlhMVMwA40chvoT sjv7KVCWoqkOP4Io61j86460ohdsiKBV8twoMs7q8NjiU+nGXUcf7UvrdIQXr0999K 1T0VRlHtb0N/QtFCuQyAQ+VpiT3Q6unh5/DEzfH+y3A6BDB42ORWOBxIZ/Sq5/r8D/ 1lz1augVyMGu1BYxj5M/46fKU6TmVJyBIqwsdpInRG1qwCw1HTWupQjkmzCbfQFW4U ro2+byNGaLs2g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDF9EC48BC4; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:46 +0800 Subject: [PATCH RFC v2 2/4] phy: hisilicon: hisi-inno-phy: enable clocks for every ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240217-inno-phy-v2-2-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=971; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=jGUbESXsyAvU27nkXjLoTOKtwqcjOT068eM8RNJCWfs=; b=UHXOSwwODhww8EbGOJMLYpPN9XmbFpLtbnFuU8Z5k/lZVtDRxNc8n70BZnZEw2b+WB9jx8etr bHvTFAnMpBTAaslzLl5OHfnpTvZcXqAT/TkBUYPvHBe5bCC3fvCPJwM X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen This is needed for port1 to work. Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisil= icon/phy-hisi-inno-usb2.c index c138cd4807d6..b7e740eb4752 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -86,8 +86,10 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy= _priv *priv, =20 static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) { + int i; /* The phy clk is controlled by the port0 register 0x06. */ - hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE); + for (i =3D 0; i < INNO_PHY_PORT_NUM; i++) + hisi_inno_phy_write_reg(priv, i, 0x06, PHY_CLK_ENABLE); msleep(PHY_CLK_STABLE_TIME); } =20 --=20 2.43.0 From nobody Sat Feb 7 07:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A19C7AE59; Sat, 17 Feb 2024 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; cv=none; b=kjRerAJu8BoLm1BE56UbOA/860nQdfuIQni1d3k0PS46W9WjSKJYJZZbN98lfci0R7e/G2PSfAcNQd3CrWPDdUn0W6S0ifgQH75Z21KjDJ8cPOIqfMhe1VjoKA1Kdn0JxMZv1sCxxpqi5CrEVADAlRqmbyjqUB90GOPwFsCIR5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708178572; c=relaxed/simple; bh=fSZGw8CHrtheqHYmGL9yCRQ6avDh/svcGOMbahUkH18=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ci2eBOfsr22mxtWDwhU+fqu9wC0WG+cLaG6miqtj9q6Vob8Wnu2yPGZLLZk7WHaCTGJShF8Ppj+hRRZsgwYgy/gFsIbtcstBOG8/HdcXkijSqGQoLfVNTjrUWuDGjJF1WA4A7qyOv3zU9UXQZOoUW+KrEmOru9ulNikejjmPtfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ItWTLi+l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ItWTLi+l" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3434C43390; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708178572; bh=fSZGw8CHrtheqHYmGL9yCRQ6avDh/svcGOMbahUkH18=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ItWTLi+lum8ZgxobUsXJoYhEZ0KRb+0nQ+rcGAxenOSCuCYbFzjQQBvZTOnIg/NKs fs5pjwyV4A0e9cQr9ybl8LkPZCqw/aVSc+C9qo++Fpr4vm0WoHAARCFm5Y2prSsj8W yy7hHcw9C3KJcYCVeTQAdqY9GtmmpN1gwDMhF/2k0cgx0d8xfbPhYC6pLG4ARnJfl6 ibEtbzgmc5m5T6PVaVU8DAuQQAEqFqRkSwxOlNJGcAjU+OhqqqpTE0K2cWtq+79SLx GfUfqTzFmKdeUA4AK7o261QhnSk5eMdUerIsM9jxtGtoPUMRPwInkBO51Ini9NiU7w oUYMeRsdaggTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8FD9C54766; Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:47 +0800 Subject: [PATCH RFC v2 3/4] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240217-inno-phy-v2-3-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=4896; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=GrCYJatgoRWu7Bx47GQoBXbcdNOq+uSu0U+veti+reE=; b=io0SbJNsSxMgQ3OaTc/0Z9tbTMuoUOoI7sFB5VfjG/ciOZl7aRIc2R0BYahKWoutI+NCTpO1B 377gjmMHMKGC9NMcLg0mt9uEo6KkEz1OM3+1O/B+KLbzoqsmWc1xz3t X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen Direct MMIO resgiter access is used by Hi3798MV200. For other models, of_iomap() returns 0 due to insufficient length. So they are unaffected. Also Hi3798MV200 INNO PHY has an extra reset required to be deasserted, switch to reset_control_bulk_() APIs to resolve this. Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 65 ++++++++++++++++++--------= ---- 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisil= icon/phy-hisi-inno-usb2.c index b7e740eb4752..5175e5a351ac 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ #define PHY_CLK_ENABLE BIT(2) =20 struct hisi_inno_phy_port { + void __iomem *base; struct reset_control *utmi_rst; struct hisi_inno_phy_priv *priv; }; @@ -50,7 +52,7 @@ struct hisi_inno_phy_port { struct hisi_inno_phy_priv { void __iomem *mmio; struct clk *ref_clk; - struct reset_control *por_rst; + struct reset_control *rsts; unsigned int type; struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; }; @@ -62,26 +64,31 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_ph= y_priv *priv, u32 val; u32 value; =20 - if (priv->type =3D=3D PHY_TYPE_0) - val =3D (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | - ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | - PHY0_TEST_WREN | PHY0_TEST_RST; - else - val =3D (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | - ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | - PHY1_TEST_WREN | PHY1_TEST_RST; - writel(val, reg); - - value =3D val; - if (priv->type =3D=3D PHY_TYPE_0) - value |=3D PHY0_TEST_CLK; - else - value |=3D PHY1_TEST_CLK; - writel(value, reg); - - writel(val, reg); + if (priv->ports[port].base) + // stride is 4 + writel(data, (u32 *)priv->ports[port].base + addr); + else { + if (priv->type =3D=3D PHY_TYPE_0) + val =3D (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | + PHY0_TEST_WREN | PHY0_TEST_RST; + else + val =3D (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | + PHY1_TEST_WREN | PHY1_TEST_RST; + writel(val, reg); + + value =3D val; + if (priv->type =3D=3D PHY_TYPE_0) + value |=3D PHY0_TEST_CLK; + else + value |=3D PHY1_TEST_CLK; + writel(value, reg); + + writel(val, reg); + } } =20 static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) @@ -104,7 +111,7 @@ static int hisi_inno_phy_init(struct phy *phy) return ret; udelay(REF_CLK_STABLE_TIME); =20 - reset_control_deassert(priv->por_rst); + reset_control_deassert(priv->rsts); udelay(POR_RST_COMPLETE_TIME); =20 /* Set up phy registers */ @@ -122,7 +129,7 @@ static int hisi_inno_phy_exit(struct phy *phy) struct hisi_inno_phy_priv *priv =3D port->priv; =20 reset_control_assert(port->utmi_rst); - reset_control_assert(priv->por_rst); + reset_control_assert(priv->rsts); clk_disable_unprepare(priv->ref_clk); =20 return 0; @@ -158,15 +165,16 @@ static int hisi_inno_phy_probe(struct platform_device= *pdev) if (IS_ERR(priv->ref_clk)) return PTR_ERR(priv->ref_clk); =20 - priv->por_rst =3D devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(priv->por_rst)) - return PTR_ERR(priv->por_rst); + priv->rsts =3D devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->rsts)) + return PTR_ERR(priv->rsts); =20 priv->type =3D (uintptr_t) of_device_get_match_data(dev); =20 for_each_child_of_node(np, child) { struct reset_control *rst; struct phy *phy; + void __iomem *base; =20 rst =3D of_reset_control_get_exclusive(child, NULL); if (IS_ERR(rst)) { @@ -174,7 +182,10 @@ static int hisi_inno_phy_probe(struct platform_device = *pdev) return PTR_ERR(rst); } =20 + base =3D of_iomap(child, 0); + priv->ports[i].utmi_rst =3D rst; + priv->ports[i].base =3D base; priv->ports[i].priv =3D priv; =20 phy =3D devm_phy_create(dev, child, &hisi_inno_phy_ops); @@ -205,6 +216,8 @@ static const struct of_device_id hisi_inno_phy_of_match= [] =3D { .data =3D (void *) PHY_TYPE_0 }, { .compatible =3D "hisilicon,hi3798mv100-usb2-phy", .data =3D (void *) PHY_TYPE_1 }, + { .compatible =3D "hisilicon,hi3798mv200-usb2-phy", + .data =3D (void *) PHY_TYPE_0 }, { }, }; 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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:48 +0800 Subject: [PATCH RFC v2 4/4] dt-bindings: phy: hisi-inno-usb2: add compatible of hisilicon,hi3798mv200-usb2-phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240217-inno-phy-v2-4-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=2016; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=jLZWuS47anxDC0v84kYOmUKJTlxPytV3qZbHvwpp28g=; b=Q/aLZDrqeMAj7mGpkxaMVPftjiJie2s2j/B2+LT4yWcdXm2FhadHAELA55FE9PjR3yynydw5y IDMBjWQCPJoCX6q6Hc93VBJWE1lkbYzChX1fhYBozhNb3cuFi8sj+TC X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen It is accessed by direct MMIO, making "ranges" property mandatory for it. Also there is an extra clock for the phy. Signed-off-by: Yang Xiwen --- .../bindings/phy/hisilicon,inno-usb2-phy.yaml | 32 ++++++++++++++++++= ++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.= yaml b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml index bfbda1568557..105dd9eebd4c 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml @@ -16,6 +16,7 @@ properties: - enum: - hisilicon,hi3798cv200-usb2-phy - hisilicon,hi3798mv100-usb2-phy + - hisilicon,hi3798mv200-usb2-phy - const: hisilicon,inno-usb2-phy =20 reg: @@ -25,18 +26,27 @@ properties: controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. Or direct MMIO address space. =20 + ranges: + maxItems: 1 + '#address-cells': const: 1 =20 '#size-cells': - const: 0 + enum: [0, 1] =20 clocks: maxItems: 1 description: reference clock =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + items: + - const: port + - const: test =20 patternProperties: 'phy@[0-9a-f]+': @@ -54,6 +64,9 @@ patternProperties: resets: maxItems: 1 =20 + phy_type: + const: utmi + required: - reg - '#phy-cells' @@ -67,6 +80,21 @@ required: - '#size-cells' - resets =20 +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798mv200-usb2-phy + then: + required: + - ranges + - reset-names + else: + properties: + ranges: false + reset-names: false + additionalProperties: false =20 examples: --=20 2.43.0