From nobody Fri Dec 19 02:49:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0529E1487C0; Fri, 16 Feb 2024 22:36:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708123020; cv=none; b=OuNXhODPu6F36z//G9XKm9XY82bCrUkvG+x2u92h3wB74wnFFJtknBZmAYCAF7FFkRH6+NBBwKfo69zV7AW66fG6+flUcyA6prL3kH/+JQcq0lrsxltRoUjkkqklIzQiUmiVWv3ysygVXERzuQAtiqPVywhATLwgrA3hVyxchmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708123020; c=relaxed/simple; bh=SwGh5DLM5LsIthu3tG63lPvezvOw26wv4J7Bcpkos2c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hOxSgssxsoO4WpoPEgtcJVDq40oCE1Kc1AjM8/KtjP+oqEKCuUuyOeICjNyWxa3mmE449CZjisV6wHOAMXJAOlOX1JDRjL2Y4uEqciufWXUo6/FSYPv6CZHYhRMjpEthyq0KhwU9H0lGPUFkyTFVjweeuCfk5ql3nfLrf50fB0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HBx+jJNZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HBx+jJNZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77C9EC433C7; Fri, 16 Feb 2024 22:36:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708123019; bh=SwGh5DLM5LsIthu3tG63lPvezvOw26wv4J7Bcpkos2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HBx+jJNZVcp74Yh9OEQGJVsKg7x9CXSCrPPWDt3BIC14J7XLKK+X8JIDqjQhlz27U rweQ0f8meSVGWimYDWOsMz7YAU0bjQpXdZVaaVqxliZEisNzeX/l2VjLa+32WT/wOm VpMGJ+6c3hqIoFpSHr+KWjPaPWi4a2qK+DpDnFWuBCtRNo9Dk9oXHiyW/lchxMTpb9 Pz0iayOPJcvyjEc5tNVYL39dDBRjIy2zjQv6kPr0daOJmvRfP2hyLGzQZnuFyJzjCL G6up6HPliboZC+TT8KaHP5dpTUi/T1aOwr7GgW3ar8My9VZf7dGqYA3EYT21VWt/q0 rYAbwbXHdP2jA== Received: by mercury (Postfix, from userid 1000) id 9EF6A10633B8; Fri, 16 Feb 2024 23:36:56 +0100 (CET) From: Sebastian Reichel To: Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team , NXP Linux Team Cc: Dong Aisheng , Linus Walleij , Dmitry Torokhov , Mark Brown , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/16] dt-bindings: soc: imx: fsl,imx-anatop: add binding Date: Fri, 16 Feb 2024 23:34:23 +0100 Message-ID: <20240216223654.1312880-5-sre@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216223654.1312880-1-sre@kernel.org> References: <20240216223654.1312880-1-sre@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add missing binding for i.MX anatop syscon. Signed-off-by: Sebastian Reichel Reviewed-by: Krzysztof Kozlowski --- .../bindings/soc/imx/fsl,imx-anatop.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-anato= p.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-anatop.yaml = b/Documentation/devicetree/bindings/soc/imx/fsl,imx-anatop.yaml new file mode 100644 index 000000000000..5a59e3470510 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-anatop.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ANATOP register + +maintainers: + - Shawn Guo + - Sascha Hauer + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx6sl-anatop + - fsl,imx6sll-anatop + - fsl,imx6sx-anatop + - fsl,imx6ul-anatop + - fsl,imx7d-anatop + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + - items: + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + items: + - description: Temperature sensor event + - description: Brown-out event on either of the support regulators + - description: Brown-out event on either the core, gpu or soc regula= tors + + tempmon: + type: object + unevaluatedProperties: false + $ref: /schemas/thermal/imx-thermal.yaml + +patternProperties: + "regulator-((3p0)|(vddcore)|(vddsoc))$": + type: object + unevaluatedProperties: false + $ref: /schemas/regulator/anatop-regulator.yaml + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + anatop: anatop@20c8000 { + compatible =3D "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg =3D <0x020c8000 0x1000>; + interrupts =3D , + , + ; + + reg_3p0: regulator-3p0 { + compatible =3D "fsl,anatop-regulator"; + regulator-name =3D "vdd3p0"; + regulator-min-microvolt =3D <2625000>; + regulator-max-microvolt =3D <3400000>; + anatop-reg-offset =3D <0x120>; + anatop-vol-bit-shift =3D <8>; + anatop-vol-bit-width =3D <5>; + anatop-min-bit-val =3D <0>; + anatop-min-voltage =3D <2625000>; + anatop-max-voltage =3D <3400000>; + anatop-enable-bit =3D <0>; + }; + + reg_arm: regulator-vddcore { + compatible =3D "fsl,anatop-regulator"; + regulator-name =3D "cpu"; + regulator-min-microvolt =3D <725000>; + regulator-max-microvolt =3D <1450000>; + regulator-always-on; + anatop-reg-offset =3D <0x140>; + anatop-vol-bit-shift =3D <0>; + anatop-vol-bit-width =3D <5>; + anatop-delay-reg-offset =3D <0x170>; + anatop-delay-bit-shift =3D <24>; + anatop-delay-bit-width =3D <2>; + anatop-min-bit-val =3D <1>; + anatop-min-voltage =3D <725000>; + anatop-max-voltage =3D <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible =3D "fsl,anatop-regulator"; + regulator-name =3D "vddsoc"; + regulator-min-microvolt =3D <725000>; + regulator-max-microvolt =3D <1450000>; + regulator-always-on; + anatop-reg-offset =3D <0x140>; + anatop-vol-bit-shift =3D <18>; + anatop-vol-bit-width =3D <5>; + anatop-delay-reg-offset =3D <0x170>; + anatop-delay-bit-shift =3D <28>; + anatop-delay-bit-width =3D <2>; + anatop-min-bit-val =3D <1>; + anatop-min-voltage =3D <725000>; + anatop-max-voltage =3D <1450000>; + }; + + tempmon: tempmon { + compatible =3D "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent =3D <&gpc>; + interrupts =3D ; + fsl,tempmon =3D <&anatop>; + nvmem-cells =3D <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names =3D "calib", "temp_grade"; + clocks =3D <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells =3D <0>; + }; + }; --=20 2.43.0