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charset="utf-8" Make it possible to use wait_until_mux_stable() for MUX registers where the mask is different from MUX_MASK (e.g. in upcoming CPU clock implementation for Exynos850). No functional change. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 744b609c222d..5ea618da0bc1 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -134,16 +134,16 @@ static void wait_until_divider_stable(void __iomem *d= iv_reg, unsigned long mask) * value was changed. */ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, - unsigned long mux_value) + unsigned long mask, unsigned long mux_value) { unsigned long timeout =3D jiffies + msecs_to_jiffies(MAX_STAB_TIME); =20 do { - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) =3D=3D mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) =3D=3D mux_value) return; } while (time_before(jiffies, timeout)); =20 - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) =3D=3D mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) =3D=3D mux_value) return; =20 pr_err("%s: re-parenting mux timed-out\n", __func__); @@ -248,7 +248,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_not= ifier_data *ndata, /* select sclk_mpll as the alternate parent */ mux_reg =3D readl(base + regs->mux_sel); writel(mux_reg | (1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 2); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2); =20 /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -289,7 +289,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_no= tifier_data *ndata, /* select mout_apll as the alternate parent */ mux_reg =3D readl(base + regs->mux_sel); writel(mux_reg & ~(1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 1); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1); =20 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { div |=3D (cfg_data->div0 & E4210_DIV0_ATB_MASK); @@ -361,7 +361,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk= _notifier_data *ndata, /* select the alternate parent */ mux_reg =3D readl(base + regs->mux_sel); writel(mux_reg | 1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 2); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2); =20 /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -389,7 +389,7 @@ static int exynos5433_cpuclk_post_rate_change(struct cl= k_notifier_data *ndata, /* select apll as the alternate parent */ mux_reg =3D readl(base + regs->mux_sel); writel(mux_reg & ~1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 1); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1); =20 exynos_set_safe_div(cpuclk, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags); --=20 2.39.2