From nobody Fri Dec 19 17:38:05 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F94E12BEA5; Fri, 16 Feb 2024 13:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708091750; cv=none; b=HipsJNY0xEGQm8FvEyCV0XR3BUrZBwv6KOnqFIrYFTDI+Vjn7tMiFLS+rvQAry06UCxnJqk+Ogcx2ww8QaRVFl4irKuwbR0+1t+W7tPtg/ciKc6/plAzRmYjhkNsadyJAQECc8b0yEzHku/dOivzXA/CYALBI5opBTWD3BY1ypk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708091750; c=relaxed/simple; bh=wk1n0oWjh34QbIeqz7ZNkSxon2SKxcvJK+7DW2eQqgQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Pya6G4fj2vChfGTNOHw+H/eSaLXtBtALgoG8R5DYBe4fr1TZZ/+dvHpDv9IhuyVwqQbIC2rpflSVP5SPM9P1Qn3gb68Wc+14y4NDoOrj+5e2wgGLGLvB+VHb9uR1JlusTiSzIbFNlqIB4OdUHkk1OQlqyon4iZ24ciJMF69DVh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=D0vTeH6i; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="D0vTeH6i" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41GDtfk7095614; Fri, 16 Feb 2024 07:55:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1708091741; bh=F9VQ5cICpZyC3r18cZBGn07fwGkoD+GP7y8K4AAm+eI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D0vTeH6iRGxWDLIMUVjHx1yZA+fx/gdkMIEGg4Oc7/0GcccVZag+dRB0KmnzAj5TH 8C34jyf+tR208prQcQBZ9S/oTJv2q8PRAjl0TJKbcgSB/I9+THXPtNaS7YsQQutNUp V997ubZuN8vS5k62LKS/9c3YvFuAYBhY59hyrqsE= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41GDtfnG004093 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 Feb 2024 07:55:41 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 16 Feb 2024 07:55:40 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 16 Feb 2024 07:55:40 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41GDtXrT127060; Fri, 16 Feb 2024 07:55:37 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , Subject: [PATCH 1/2] arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1 Date: Fri, 16 Feb 2024 19:25:32 +0530 Message-ID: <20240216135533.904130-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216135533.904130-1-vaishnav.a@ti.com> References: <20240216135533.904130-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli Enable MAC Port 1 of CPSW3G instance of CPSW Ethernet Switch in RGMII-RXID mode of operation. Port 2 is not connected on the EVM, thus keep it disabled. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index b4f2fee53a97..9e12a6e9111f 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -8,6 +8,7 @@ =20 /dts-v1/; =20 +#include #include "k3-j722s.dtsi" =20 / { @@ -160,6 +161,58 @@ J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ >; bootph-all; }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; +}; + +&cpsw3g { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status =3D "disabled"; }; =20 &main_gpio1 { --=20 2.34.1 From nobody Fri Dec 19 17:38:05 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74C8712BF1B; Fri, 16 Feb 2024 13:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708091752; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41GDtXrU127060; Fri, 16 Feb 2024 07:55:41 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , Subject: [PATCH 2/2] arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support Date: Fri, 16 Feb 2024 19:25:33 +0530 Message-ID: <20240216135533.904130-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216135533.904130-1-vaishnav.a@ti.com> References: <20240216135533.904130-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J722S EVM has S28HS512T 64 MiB Octal SPI NOR flash connected to the OSPI interface, add support for the flash and describe the partition information as per bootloader. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 79 +++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 9e12a6e9111f..b1c6499c0c9d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -169,6 +169,23 @@ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO= */ >; }; =20 + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ + >; + bootph-all; + }; + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins =3D < J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ @@ -290,6 +307,68 @@ exp1: gpio@23 { }; }; =20 +&ospi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ospi0_pins_default>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + bootph-all; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "ospi.tiboot3"; + reg =3D <0x00 0x80000>; + }; + + partition@80000 { + label =3D "ospi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "ospi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "ospi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@6c0000 { + label =3D "ospi.env.backup"; + reg =3D <0x6c0000 0x40000>; + }; + + partition@800000 { + label =3D "ospi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label =3D "ospi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + }; + +}; + &sdhci1 { /* SD/MMC */ vmmc-supply =3D <&vdd_mmc1>; --=20 2.34.1