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Signed-off-by: Antonio Borneo Fixes: 046a6ee2343b ("irqchip: Bulk conversion to generic_handle_domain_irq= ()") --- drivers/irqchip/irq-stm32-exti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 971240e2e31b..69982f21126a 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -322,7 +322,7 @@ static void stm32_irq_handler(struct irq_desc *desc) while ((pending =3D stm32_exti_pending(gc))) { for_each_set_bit(n, &pending, IRQS_PER_BANK) generic_handle_domain_irq(domain, irq_base + n); - } + } } =20 chained_irq_exit(chip, desc); --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 471EE64A90; Mon, 15 Apr 2024 13:50:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Commit 046a6ee2343b ("irqchip: Bulk conversion to generic_handle_domain_irq()") incorrectly adds a leading space character in the line indentation. Use only TAB for indentation, removing the leading space. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 26a5193d0ae41..3b35f138ed3d7 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -322,7 +322,7 @@ static void stm32_irq_handler(struct irq_desc *desc) while ((pending =3D stm32_exti_pending(gc))) { for_each_set_bit(n, &pending, IRQS_PER_BANK) generic_handle_domain_irq(domain, irq_base + n); - } + } } =20 chained_irq_exit(chip, desc); --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 739AD1BC36; Fri, 16 Feb 2024 09:49:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; 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Fri, 16 Feb 2024 10:49:06 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 89DB340048; Fri, 16 Feb 2024 10:49:03 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3D0A8237D75; Fri, 16 Feb 2024 10:48:18 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:48:17 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , , Fabrice Gasnier Subject: [PATCH 02/12] dt-bindings: interrupt-controller: stm32-exti: Add irq nexus child node Date: Fri, 16 Feb 2024 10:47:47 +0100 Message-ID: <20240216094758.916722-3-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" The mapping of EXTI interrupts to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new table to the driver's code and a new compatible for each new EXTI instance. Add to the binding an interrupt nexus child node that will be used on the new EXTI instances and can be optionally used on the existing instances. The property 'interrupt-map' in the nexus node maps each EXTI interrupt to the parent interrupt. Align #address-cells and #interrupt-cells between the EXTI node and its nexus node. Signed-off-by: Antonio Borneo Signed-off-by: Fabrice Gasnier --- .../interrupt-controller/st,stm32-exti.yaml | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm3= 2-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm= 32-exti.yaml index 00c10a8258f1..1a4cf9537b9e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml @@ -26,6 +26,9 @@ properties: "#interrupt-cells": const: 2 =20 + "#address-cells": + const: 0 + reg: maxItems: 1 =20 @@ -42,6 +45,24 @@ properties: description: Interrupts references to primary interrupt controller =20 + exti-interrupt-map: + type: object + properties: + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 2 + + "#address-cells": + const: 0 + + required: + - interrupt-map + - "#interrupt-cells" + - "#address-cells" + required: - "#interrupt-cells" - compatible @@ -89,8 +110,27 @@ examples: reg =3D <0x5000d000 0x400>; }; =20 + - | //Example 2 - exti2: interrupt-controller@40013c00 { + #include + exti2: interrupt-controller@5000d000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + reg =3D <0x5000d000 0x400>; + exti-interrupt-map { + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-map-mask =3D <0xffffffff 0>; + interrupt-map =3D + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + - | + //Example 3 + exti3: interrupt-controller@40013c00 { compatible =3D "st,stm32-exti"; interrupt-controller; #interrupt-cells =3D <2>; --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A8E973186; Mon, 15 Apr 2024 13:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The mapping of EXTI events to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new mapping table to the driver's code and a new compatible for each new EXTI instance. Use the interrupts-extended property to list, for each EXTI event, the associated parent interrupt. Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Signed-off-by: Antonio Borneo Reviewed-by: Rob Herring (Arm) --- .../interrupt-controller/st,stm32-exti.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm3= 2-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm= 32-exti.yaml index 00c10a8258f13..9967e57b449b0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml @@ -89,8 +89,23 @@ examples: reg =3D <0x5000d000 0x400>; }; =20 + - | //Example 2 - exti2: interrupt-controller@40013c00 { + #include + exti2: interrupt-controller@5000d000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + reg =3D <0x5000d000 0x400>; + interrupts-extended =3D + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" The mapping of EXTI interrupts to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new table to the driver's code and a new compatible for each new EXTI instance. Check for the presence of the optional interrupt nexus child node and use its property 'interrup-map' to map EXTI interrupts to the parent's interrupts. For old DT's without the optional nexus child node, the driver's behavior is unchanged, thus keeps backward compatibility. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 69982f21126a..95bb3dd10b2c 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -61,6 +61,7 @@ struct stm32_exti_host_data { struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; + struct device_node *irq_map_node; }; =20 static struct stm32_exti_host_data *stm32_host_data; @@ -713,8 +714,9 @@ static int stm32_exti_h_domain_alloc(struct irq_domain = *dm, u8 desc_irq; struct irq_fwspec *fwspec =3D data; struct irq_fwspec p_fwspec; + struct of_phandle_args out_irq; irq_hw_number_t hwirq; - int bank; + int bank, ret; u32 event_trg; struct irq_chip *chip; =20 @@ -731,6 +733,25 @@ static int stm32_exti_h_domain_alloc(struct irq_domain= *dm, =20 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); =20 + if (host_data->irq_map_node) { + out_irq.np =3D host_data->irq_map_node; + out_irq.args_count =3D 2; + out_irq.args[0] =3D fwspec->param[0]; + out_irq.args[1] =3D fwspec->param[1]; + + ret =3D of_irq_parse_raw(NULL, &out_irq); + if (ret) + return ret; + /* we only support one parent, so far */ + if (of_node_to_fwnode(out_irq.np) !=3D dm->parent->fwnode) + return -EINVAL; + + of_phandle_args_to_fwspec(out_irq.np, out_irq.args, + out_irq.args_count, &p_fwspec); + + return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); + } + if (!host_data->drv_data->desc_irqs) return -EINVAL; =20 @@ -908,7 +929,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) { int ret, i; struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; + struct device_node *child, *np =3D dev->of_node; struct irq_domain *parent_domain, *domain; struct stm32_exti_host_data *host_data; const struct stm32_exti_drv_data *drv_data; @@ -976,6 +997,10 @@ static int stm32_exti_probe(struct platform_device *pd= ev) if (ret) return ret; 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charset="utf-8" The mapping of EXTI events to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new mapping table to the driver's code and a new compatible for each new EXTI instance. Check for the presence of the optional interrupts-extended property and use it to map EXTI events to the parent's interrupts. For old DTs without the optional interrupts-extended property, the driver's behavior is unchanged, thus keeps backward compatibility. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 3b35f138ed3d7..e5714a0111e7b 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -61,6 +61,7 @@ struct stm32_exti_host_data { struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; + bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from D= T */ }; =20 static struct stm32_exti_host_data *stm32_host_data; @@ -731,6 +732,23 @@ static int stm32_exti_h_domain_alloc(struct irq_domain= *dm, =20 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); =20 + if (host_data->dt_has_irqs_desc) { + struct of_phandle_args out_irq; + int ret; + + ret =3D of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq); + if (ret) + return ret; + /* we only support one parent, so far */ + if (of_node_to_fwnode(out_irq.np) !=3D dm->parent->fwnode) + return -EINVAL; + + of_phandle_args_to_fwspec(out_irq.np, out_irq.args, + out_irq.args_count, &p_fwspec); + + return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); + } + if (!host_data->drv_data->desc_irqs) return -EINVAL; =20 @@ -975,6 +993,9 @@ static int stm32_exti_probe(struct platform_device *pde= v) if (ret) return ret; =20 + if (of_property_read_bool(np, "interrupts-extended")) + host_data->dt_has_irqs_desc =3D true; + stm32_exti_h_syscore_init(host_data); =20 return 0; --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A1473196; Mon, 15 Apr 2024 13:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189046; cv=none; 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charset="utf-8" All driver's dependencies for suspend/resume have been fixed long ago. There are no more reasons to use syscore PM for the part of this driver related to Cortex-A MPU. Switch to standard PM using NOIRQ_SYSTEM_SLEEP_PM_OPS, so all the registers of the interrupt controller get resumed before any irq gets enabled. A side effect of this change is to drop the only global variable 'stm32_host_data', used to keep the driver's data for syscore_ops. This makes the driver ready to support multiple EXTI instances. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 57 ++++++++++---------------------- 1 file changed, 17 insertions(+), 40 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index e5714a0111e7b..ded20d9bde73f 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include =20 #include =20 @@ -64,8 +64,6 @@ struct stm32_exti_host_data { bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from D= T */ }; =20 -static struct stm32_exti_host_data *stm32_host_data; - static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D { .imr_ofst =3D 0x00, .emr_ofst =3D 0x04, @@ -622,50 +620,32 @@ static int stm32_exti_h_set_affinity(struct irq_data = *d, return IRQ_SET_MASK_OK_DONE; } =20 -static int __maybe_unused stm32_exti_h_suspend(void) +static int stm32_exti_h_suspend(struct device *dev) { + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; =20 - for (i =3D 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data =3D &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; stm32_chip_suspend(chip_data, chip_data->wake_active); - raw_spin_unlock(&chip_data->rlock); } =20 return 0; } =20 -static void __maybe_unused stm32_exti_h_resume(void) +static int stm32_exti_h_resume(struct device *dev) { + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; =20 - for (i =3D 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data =3D &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; stm32_chip_resume(chip_data, chip_data->mask_cache); - raw_spin_unlock(&chip_data->rlock); } -} =20 -static struct syscore_ops stm32_exti_h_syscore_ops =3D { -#ifdef CONFIG_PM_SLEEP - .suspend =3D stm32_exti_h_suspend, - .resume =3D stm32_exti_h_resume, -#endif -}; - -static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_da= ta) -{ - stm32_host_data =3D host_data; - register_syscore_ops(&stm32_exti_h_syscore_ops); -} - -static void stm32_exti_h_syscore_deinit(void) -{ - unregister_syscore_ops(&stm32_exti_h_syscore_ops); + return 0; } =20 static int stm32_exti_h_retrigger(struct irq_data *d) @@ -789,8 +769,6 @@ stm32_exti_host_data *stm32_exti_host_init(const struct= stm32_exti_drv_data *dd, goto free_chips_data; } =20 - stm32_host_data =3D host_data; - return host_data; =20 free_chips_data: @@ -916,11 +894,6 @@ static void stm32_exti_remove_irq(void *data) irq_domain_remove(domain); } =20 -static void stm32_exti_remove(struct platform_device *pdev) -{ - stm32_exti_h_syscore_deinit(); -} - static int stm32_exti_probe(struct platform_device *pdev) { int ret, i; @@ -934,6 +907,8 @@ static int stm32_exti_probe(struct platform_device *pde= v) if (!host_data) return -ENOMEM; =20 + dev_set_drvdata(dev, host_data); + /* check for optional hwspinlock which may be not available yet */ ret =3D of_hwspin_lock_get_id(np, 0); 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charset="utf-8" All driver's dependencies for suspend/resume have been fixed long ago. There are no more reasons to use syscore PM for the part of this driver related to Cortex-A MPU. Switch to standard PM using NOIRQ_SYSTEM_SLEEP_PM_OPS, so all the registers of the interrupt controller get resumed before any irq gets enabled. A side effect of this change is to drop the only global variable 'stm32_host_data', used to keep the driver's data for syscore_ops. This makes the driver ready to support multiple EXTI instances. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 58 ++++++++++---------------------- 1 file changed, 17 insertions(+), 41 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 95bb3dd10b2c..de18cddf6b88 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include =20 #include =20 @@ -64,8 +64,6 @@ struct stm32_exti_host_data { struct device_node *irq_map_node; }; =20 -static struct stm32_exti_host_data *stm32_host_data; - static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D { .imr_ofst =3D 0x00, .emr_ofst =3D 0x04, @@ -622,50 +620,32 @@ static int stm32_exti_h_set_affinity(struct irq_data = *d, return IRQ_SET_MASK_OK_DONE; } =20 -static int __maybe_unused stm32_exti_h_suspend(void) +static int stm32_exti_h_suspend(struct device *dev) { + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; =20 - for (i =3D 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data =3D &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; stm32_chip_suspend(chip_data, chip_data->wake_active); - raw_spin_unlock(&chip_data->rlock); } =20 return 0; } =20 -static void __maybe_unused stm32_exti_h_resume(void) +static int stm32_exti_h_resume(struct device *dev) { + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; =20 - for (i =3D 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data =3D &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; stm32_chip_resume(chip_data, chip_data->mask_cache); - raw_spin_unlock(&chip_data->rlock); } -} =20 -static struct syscore_ops stm32_exti_h_syscore_ops =3D { -#ifdef CONFIG_PM_SLEEP - .suspend =3D stm32_exti_h_suspend, - .resume =3D stm32_exti_h_resume, -#endif -}; - -static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_da= ta) -{ - stm32_host_data =3D host_data; - register_syscore_ops(&stm32_exti_h_syscore_ops); -} - -static void stm32_exti_h_syscore_deinit(void) -{ - unregister_syscore_ops(&stm32_exti_h_syscore_ops); + return 0; } =20 static int stm32_exti_h_retrigger(struct irq_data *d) @@ -792,8 +772,6 @@ stm32_exti_host_data *stm32_exti_host_init(const struct= stm32_exti_drv_data *dd, goto free_chips_data; } =20 - stm32_host_data =3D host_data; - return host_data; =20 free_chips_data: @@ -919,12 +897,6 @@ static void stm32_exti_remove_irq(void *data) irq_domain_remove(domain); } =20 -static int stm32_exti_remove(struct platform_device *pdev) -{ - stm32_exti_h_syscore_deinit(); - return 0; -} - static int stm32_exti_probe(struct platform_device *pdev) { int ret, i; @@ -938,6 +910,8 @@ static int stm32_exti_probe(struct platform_device *pde= v) if (!host_data) return -ENOMEM; =20 + dev_set_drvdata(dev, host_data); + /* check for optional hwspinlock which may be not available yet */ ret =3D of_hwspin_lock_get_id(np, 0); if (ret =3D=3D -EPROBE_DEFER) @@ -1001,8 +975,6 @@ static int stm32_exti_probe(struct platform_device *pd= ev) if (child && of_property_read_bool(child, "interrupt-map")) host_data->irq_map_node =3D child; =20 - stm32_exti_h_syscore_init(host_data); - return 0; } =20 @@ -1014,12 +986,16 @@ static const struct of_device_id stm32_exti_ids[] = =3D { }; MODULE_DEVICE_TABLE(of, stm32_exti_ids); =20 +static const struct dev_pm_ops stm32_exti_dev_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) +}; + static struct platform_driver stm32_exti_driver =3D { .probe =3D stm32_exti_probe, - .remove =3D stm32_exti_remove, .driver =3D { .name =3D "stm32_exti", .of_match_table =3D stm32_exti_ids, + .pm =3D &stm32_exti_dev_pm_ops, }, }; =20 --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E0B51CA9F; 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Fri, 16 Feb 2024 10:50:08 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D4F8A4002D; Fri, 16 Feb 2024 10:50:04 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 38326237D78; Fri, 16 Feb 2024 10:49:22 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:21 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 05/12] irqchip/stm32-exti: Skip secure events Date: Fri, 16 Feb 2024 10:47:50 +0100 Message-ID: <20240216094758.916722-6-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Secure OS can reserve some EXTI event, marking them as "secure" by setting the corresponding bit in register SECCFGR (aka TZENR). These events cannot be used by Linux. Read the list of reserved events and check it during irq domain allocation. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index de18cddf6b88..85a40e07fbc3 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -36,6 +36,7 @@ struct stm32_exti_bank { u32 rpr_ofst; u32 fpr_ofst; u32 trg_ofst; + u32 seccfgr_ofst; }; =20 #define UNDEF_REG ~0 @@ -54,10 +55,12 @@ struct stm32_exti_chip_data { u32 mask_cache; u32 rtsr_cache; u32 ftsr_cache; + u32 event_reserved; }; =20 struct stm32_exti_host_data { void __iomem *base; + struct device *dev; struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; @@ -73,6 +76,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D= { .rpr_ofst =3D 0x14, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] =3D { @@ -93,6 +97,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 =3D= { .rpr_ofst =3D 0x88, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b2 =3D { @@ -104,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = =3D { .rpr_ofst =3D 0x98, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b3 =3D { @@ -115,6 +121,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = =3D { .rpr_ofst =3D 0xA8, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] =3D { @@ -137,6 +144,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = =3D { .rpr_ofst =3D 0x0C, .fpr_ofst =3D 0x10, .trg_ofst =3D 0x3EC, + .seccfgr_ofst =3D 0x14, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { @@ -148,6 +156,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = =3D { .rpr_ofst =3D 0x2C, .fpr_ofst =3D 0x30, .trg_ofst =3D 0x3E8, + .seccfgr_ofst =3D 0x34, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { @@ -159,6 +168,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = =3D { .rpr_ofst =3D 0x4C, .fpr_ofst =3D 0x50, .trg_ofst =3D 0x3E4, + .seccfgr_ofst =3D 0x54, }; =20 static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { @@ -707,6 +717,12 @@ static int stm32_exti_h_domain_alloc(struct irq_domain= *dm, bank =3D hwirq / IRQS_PER_BANK; chip_data =3D &host_data->chips_data[bank]; =20 + /* Check if event is reserved (Secure) */ + if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { + dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); + return -EPERM; + } + event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? &stm32_exti_h_chip : &stm32_exti_h_chip_direct; @@ -806,6 +822,10 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm3= 2_exti_host_data *h_data, if (stm32_bank->emr_ofst !=3D UNDEF_REG) writel_relaxed(0, base + stm32_bank->emr_ofst); =20 + /* reserve Secure events */ + if (stm32_bank->seccfgr_ofst !=3D UNDEF_REG) + chip_data->event_reserved =3D readl_relaxed(base + stm32_bank->seccfgr_o= fst); + pr_info("%pOF: bank%d\n", node, bank_idx); =20 return chip_data; @@ -911,6 +931,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) return -ENOMEM; =20 dev_set_drvdata(dev, host_data); + host_data->dev =3D dev; =20 /* check for optional hwspinlock which may be not available yet */ ret =3D of_hwspin_lock_get_id(np, 0); --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D5E4757F8; Mon, 15 Apr 2024 13:51:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189112; cv=none; b=bU4l3nOid4H3WRPqlVEKoae9ENiP7UJk/3AO1AXTd91uzsdfbo2f9wyeHXnLo6VXEoyfpNsjH6S7cK7RG2UKlap3KQnmKU/+rtBIT+XtGZDp35AQHOXNT1g6OkkmMHYGNzjezRJmXmvaQqivNyncIG3duCgbeHz/p0CwvMiKa1M= ARC-Message-Signature: i=1; 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charset="utf-8" Secure OS can reserve some EXTI event, marking them as "secure" by setting the corresponding bit in register SECCFGR (aka TZENR). These events cannot be used by Linux. Read the list of reserved events and check it during irq domain allocation. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index ded20d9bde73f..c0a020aab557a 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -36,6 +36,7 @@ struct stm32_exti_bank { u32 rpr_ofst; u32 fpr_ofst; u32 trg_ofst; + u32 seccfgr_ofst; }; =20 #define UNDEF_REG ~0 @@ -54,10 +55,12 @@ struct stm32_exti_chip_data { u32 mask_cache; u32 rtsr_cache; u32 ftsr_cache; + u32 event_reserved; }; =20 struct stm32_exti_host_data { void __iomem *base; + struct device *dev; struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; @@ -73,6 +76,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D= { .rpr_ofst =3D 0x14, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] =3D { @@ -93,6 +97,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 =3D= { .rpr_ofst =3D 0x88, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b2 =3D { @@ -104,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = =3D { .rpr_ofst =3D 0x98, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b3 =3D { @@ -115,6 +121,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = =3D { .rpr_ofst =3D 0xA8, .fpr_ofst =3D UNDEF_REG, .trg_ofst =3D UNDEF_REG, + .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] =3D { @@ -137,6 +144,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = =3D { .rpr_ofst =3D 0x0C, .fpr_ofst =3D 0x10, .trg_ofst =3D 0x3EC, + .seccfgr_ofst =3D 0x14, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { @@ -148,6 +156,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = =3D { .rpr_ofst =3D 0x2C, .fpr_ofst =3D 0x30, .trg_ofst =3D 0x3E8, + .seccfgr_ofst =3D 0x34, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { @@ -159,6 +168,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = =3D { .rpr_ofst =3D 0x4C, .fpr_ofst =3D 0x50, .trg_ofst =3D 0x3E4, + .seccfgr_ofst =3D 0x54, }; =20 static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { @@ -706,6 +716,12 @@ static int stm32_exti_h_domain_alloc(struct irq_domain= *dm, bank =3D hwirq / IRQS_PER_BANK; chip_data =3D &host_data->chips_data[bank]; =20 + /* Check if event is reserved (Secure) */ + if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { + dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); + return -EPERM; + } + event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? &stm32_exti_h_chip : &stm32_exti_h_chip_direct; @@ -803,6 +819,10 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm3= 2_exti_host_data *h_data, if (stm32_bank->emr_ofst !=3D UNDEF_REG) writel_relaxed(0, base + stm32_bank->emr_ofst); =20 + /* reserve Secure events */ + if (stm32_bank->seccfgr_ofst !=3D UNDEF_REG) + chip_data->event_reserved =3D readl_relaxed(base + stm32_bank->seccfgr_o= fst); + pr_info("%pOF: bank%d\n", node, bank_idx); =20 return chip_data; @@ -908,6 +928,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) return -ENOMEM; =20 dev_set_drvdata(dev, host_data); + host_data->dev =3D dev; =20 /* check for optional hwspinlock which may be not available yet */ ret =3D of_hwspin_lock_get_id(np, 0); --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F8AA1CAA7; Fri, 16 Feb 2024 09:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708077025; cv=none; b=Zix8DdaP7Y0qIrbzKSNv3cQ4wjn974y58SpHramqTgDrUoMrhJJV2rQ1kDcgVxTXYa3fYq2V80csLgN9x1RKWfU2fhzzyYW2uxAz1gsIjdxQ2V3BlMVKZjrl+rhlVgwWtbOxW1Ad6xryMs4rLo4gCcrsO1mrtl3Nm3ypgG3OPM0= ARC-Message-Signature: i=1; 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charset="utf-8" EXTI events availability depends on Resource Isolation Framework (RIF) configuration. RIF grants access to buses with Compartment ID (CID) filtering, secure and privilege level. It also assigns EXTI events to one or several processors (CID, Secure, Privilege). EXTI events used by Linux must be CID-filtered (EnCIDCFGR.CFEN=3D1) and statically assigned to CID1 (EnCIDCFR.CID=3DCID1). EXTI events not filling these conditions are marked as reserved and can't be used by Linux. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 40 ++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 85a40e07fbc3..68af5fe4764b 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -23,9 +23,22 @@ =20 #include =20 -#define IRQS_PER_BANK 32 +#define IRQS_PER_BANK 32 =20 -#define HWSPNLCK_TIMEOUT 1000 /* usec */ +#define HWSPNLCK_TIMEOUT 1000 /* usec */ + +#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) +#define EXTI_HWCFGR1 0x3f0 + +/* Register: EXTI_EnCIDCFGR(n) */ +#define EXTI_CIDCFGR_CFEN_MASK BIT(0) +#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) +#define EXTI_CIDCFGR_CID_SHIFT 4 + +/* Register: EXTI_HWCFGR1 */ +#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) + +#define EXTI_CID1 1 =20 struct stm32_exti_bank { u32 imr_ofst; @@ -910,6 +923,27 @@ static const struct irq_domain_ops stm32_exti_h_domain= _ops =3D { .xlate =3D irq_domain_xlate_twocell, }; =20 +static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) +{ + u32 cid, cidcfgr, hwcfgr1; + unsigned int bank, i, event; + + /* quit on CID not supported */ + hwcfgr1 =3D readl_relaxed(host_data->base + EXTI_HWCFGR1); + if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) =3D=3D 0) + return; + + for (bank =3D 0; bank < host_data->drv_data->bank_nr; bank++) { + for (i =3D 0; i < IRQS_PER_BANK; i++) { + event =3D bank * IRQS_PER_BANK + i; + cidcfgr =3D readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); + cid =3D (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; + if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid !=3D EXTI_CID1) + host_data->chips_data[bank].event_reserved |=3D BIT(i); + } + } +} + static void stm32_exti_remove_irq(void *data) { struct irq_domain *domain =3D data; @@ -972,6 +1006,8 @@ static int stm32_exti_probe(struct platform_device *pd= ev) for (i =3D 0; i < drv_data->bank_nr; i++) stm32_exti_chip_init(host_data, i, np); =20 + stm32_exti_check_rif(host_data); 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charset="utf-8" EXTI events availability depends on Resource Isolation Framework (RIF) configuration. RIF grants access to buses with Compartment ID (CID) filtering, secure and privilege level. It also assigns EXTI events to one or several processors (CID, Secure, Privilege). EXTI events used by Linux must be CID-filtered (EnCIDCFGR.CFEN=3D1) and statically assigned to CID1 (EnCIDCFR.CID=3DCID1). EXTI events not filling these conditions are marked as reserved and can't be used by Linux. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 40 ++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index c0a020aab557a..2cc9f3b7d6690 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -23,9 +23,22 @@ =20 #include =20 -#define IRQS_PER_BANK 32 +#define IRQS_PER_BANK 32 =20 -#define HWSPNLCK_TIMEOUT 1000 /* usec */ +#define HWSPNLCK_TIMEOUT 1000 /* usec */ + +#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) +#define EXTI_HWCFGR1 0x3f0 + +/* Register: EXTI_EnCIDCFGR(n) */ +#define EXTI_CIDCFGR_CFEN_MASK BIT(0) +#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) +#define EXTI_CIDCFGR_CID_SHIFT 4 + +/* Register: EXTI_HWCFGR1 */ +#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) + +#define EXTI_CID1 1 =20 struct stm32_exti_bank { u32 imr_ofst; @@ -907,6 +920,27 @@ static const struct irq_domain_ops stm32_exti_h_domain= _ops =3D { .xlate =3D irq_domain_xlate_twocell, }; =20 +static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) +{ + unsigned int bank, i, event; + u32 cid, cidcfgr, hwcfgr1; + + /* quit on CID not supported */ + hwcfgr1 =3D readl_relaxed(host_data->base + EXTI_HWCFGR1); + if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) =3D=3D 0) + return; + + for (bank =3D 0; bank < host_data->drv_data->bank_nr; bank++) { + for (i =3D 0; i < IRQS_PER_BANK; i++) { + event =3D bank * IRQS_PER_BANK + i; + cidcfgr =3D readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); + cid =3D (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; + if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid !=3D EXTI_CID1) + host_data->chips_data[bank].event_reserved |=3D BIT(i); + } + } +} + static void stm32_exti_remove_irq(void *data) { struct irq_domain *domain =3D data; @@ -969,6 +1003,8 @@ static int stm32_exti_probe(struct platform_device *pd= ev) for (i =3D 0; i < drv_data->bank_nr; i++) stm32_exti_chip_init(host_data, i, np); =20 + stm32_exti_check_rif(host_data); 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charset="utf-8" ARCH_STM32 needs to use STM32 EXTI interrupt controller for GPIO and wakeup interrupts. Signed-off-by: Antonio Borneo --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..19bf58a9d5e1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -302,6 +302,7 @@ config ARCH_STM32 select GPIOLIB select PINCTRL select PINCTRL_STM32MP257 + select STM32_EXTI select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75CC477A03; Mon, 15 Apr 2024 13:51:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189116; cv=none; b=udJzqhQCCrgW695pAQHkzwWGWUNRkEC/h8bqpppFkrRce6/5A0R3MCyS6Lyr5Xj0iNa1c3EnsMwE7YalAk3QiQShKeB2MsXyb4iA2+g+zRELUvTFVhs8vS4OfiUYl5/5Sdhkp7Vft2v0f2nFQiKSDCbtIcjF+8z4VX5m3xwhSwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189116; c=relaxed/simple; bh=KIYrUxY+b9z+lxbDqbvGLtVKWQfYAVPg7QIHFhflyJw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TohTi8hwmRW/3cFmoXl/HttxbCwgXq4W/UtJU5jgzxUeRft4z+tuCnl5Cqs6Ozp/QxxWokLSIx6jo8vZdBSmreyD0sT/03g4aE9YMU9gqMShZgU+Mmem9xpr2/k/3ePHUD+H15IPw726ofwd9NRJ4qP/PRzuSCUtulnZMZ/J5NQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=x0oSHiJe; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="x0oSHiJe" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43FCaK9X024860; Mon, 15 Apr 2024 15:51:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=QsaD5br63QiPS08LMVeUwl+S5bVO25sOLw/LZKdTl/A=; b=x0 oSHiJeqXIs3PRk1PrWgxXuE7GK5B2Oaxehn8+qOYrTP/Ky8/SzviaJsHFpZeo+zT rKkY3NDbQpSaYoM0em8tPc5OzraNHjH36wnLa/QGaQi0bIY0byai48cTP+j8cIg4 ljE7MZANslFx9kZyBWlLqc1/z0gpWdSrtU/qeSsfXY2K42264g0EavBfz4h8vVc8 mh8lNglZez/JOzfq/yLCT/ml3T/+rFv7s/ADb7WNVb3Qadh7WM1UTIkA/sTMsuaW zEUQhT/bVmXt5ZLzhzOHfq1+E7dTXUJcjDzwR1TsmDFVavzymHJd4mLK481nhZN+ 2YV/wB/alkniXGhV5Rdg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3xff647xnd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Apr 2024 15:51:37 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 52A4140044; Mon, 15 Apr 2024 15:51:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2706421660B; Mon, 15 Apr 2024 15:50:50 +0200 (CEST) Received: from localhost (10.48.86.102) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 15 Apr 2024 15:50:49 +0200 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , Fabrice Gasnier , , , , Subject: [PATCH v2 07/11] arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32 Date: Mon, 15 Apr 2024 15:49:22 +0200 Message-ID: <20240415134926.1254428-8-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-15_11,2024-04-15_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" ARCH_STM32 needs to use STM32 EXTI interrupt controller for GPIO and wakeup interrupts. Signed-off-by: Antonio Borneo --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad56..19bf58a9d5e1b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -302,6 +302,7 @@ config ARCH_STM32 select GPIOLIB select PINCTRL select PINCTRL_STM32MP257 + select STM32_EXTI select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0ACD20DF0; Fri, 16 Feb 2024 09:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708077029; cv=none; b=Ig+UKeutMI2rl+BkVbd7X3Vtj3F9YDu57rZdnRm/ZH6KcCXmPWUw5Sj70809HWjIw356BMhC1qwxFP1nm3l2RLaUsI4Gizn5q5pDQ9V+iDMSWC2mfq9QCTUSVcHEtRf6McTEoeC3dW6MAmYBSIuJu1dY7m5gZX4AIc4JvvvoabY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708077029; c=relaxed/simple; bh=CKF19vvrEXl+K22tbPsavgofVcgBDneCNcVVkmh0WN0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g5eg9YhLfld2eXsHdAwhsXgo/qQ/Jn71lv5Kp0S6zRAt3Mhf4dLBG5xtReOhym9HSC1wYX4Br2b28xv7EySYh8fP3yqZzfrITZKCkhcHIvFKxyNETd/JwAIuq/0sZ26IntxAIGUnwf3DSjlRGvaUtBEADoNHUmA3JSAHMVaWd9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=Appw7fH4; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Appw7fH4" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41G4qPtY015733; Fri, 16 Feb 2024 10:50:12 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=+fxKXdkROzT3M+/iRky170lOst61Y8+W0nzGBLi971o=; b=Ap pw7fH4IJUX/c324kbwir6nOnL40h6y/qP0alnLqfIszOFG6JHz0jdTTMMWti158G eyMC/7WlUIbWn94woIe321T3IRDy/9LlI88eFJyeoszxvvI+JfbJhvTb6HMMCDL1 AKckjOk3AyUPsVkWr28a73agH8PAvJ5ZnWDZYB4Iv0/PQ0wD01RBBT4I85BrpYRE nwnfcLVIB/61fBBlKm8Lt//WBC+Sjy1Bas5TLH7V8PJOTjcNPtjQgKKYvzb33h/q 2aN3YNBTed9GJL5bChevjfKRSBU6O6tifA0Pfm3wqS0xdX7GdICOIiMAssudN90J G3j6Mj/uf+8yPSllASgA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3wa124gy88-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 10:50:12 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B33D840048; Fri, 16 Feb 2024 10:50:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 13158237D7B; Fri, 16 Feb 2024 10:49:24 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:23 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 08/12] ARM: dts: stm32: Use exti interrupt-map on stm32mp151 Date: Fri, 16 Feb 2024 10:47:53 +0100 Message-ID: <20240216094758.916722-9-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Stop using the internal table of the exti driver and use the more flexible interrupt-map feature in DT. Convert the driver's table for stm32mp151 to the interrupt-map property in DT. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp151.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index fa4cbd312e5a..33c460cacb04 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -1223,7 +1223,58 @@ exti: interrupt-controller@5000d000 { compatible =3D "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells =3D <2>; + #address-cells =3D <0>; reg =3D <0x5000d000 0x400>; + + exti-interrupt-map { + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-map-mask =3D <0xffffffff 0>; + interrupt-map =3D + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <54 0 &intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <65 0 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <73 0 &intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" Stop using the table inside the EXTI driver and list in DT the mapping between EXTI events and its parent interrupts. Convert the driver's table for stm32mp151 to the DT property interrupts-extended. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp151.dtsi | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index fa4cbd312e5a1..bcb3ed94b2656 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -1224,6 +1224,81 @@ exti: interrupt-controller@5000d000 { interrupt-controller; #interrupt-cells =3D <2>; reg =3D <0x5000d000 0x400>; + interrupts-extended =3D + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_40 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <0>, + <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" Stop using the table inside the EXTI driver and list in DT the mapping between EXTI events and its parent interrupts. By switching away from using the internal table, there is no need anymore to use the specific compatible "st,stm32mp13-exti", which was introduced to select the proper internal table. Convert the driver's table for stm32mp131 to the DT property interrupts-extended. Switch the compatible string to the generic "st,stm32mp1-exti", in place of the specific "st,stm32mp13-exti". Older DT using compatible "st,stm32mp13-exti" will still work as the driver remains backward compatible. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp131.dtsi | 74 +++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index 3900f32da797b..c432fe109cbec 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1093,10 +1093,82 @@ rcc: rcc@50000000 { }; =20 exti: interrupt-controller@5000d000 { - compatible =3D "st,stm32mp13-exti", "syscon"; + compatible =3D "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells =3D <2>; reg =3D <0x5000d000 0x400>; + interrupts-extended =3D + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_40 */ + <0>, + <0>, + <0>, + <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" Stop using the internal table of the exti driver and use the more flexible interrupt-map feature in DT. By switching away from using the internal table, there is no need anymore to use the specific compatible "st,stm32mp13-exti", which was introduced to select the proper internal table. Convert the driver table to interrupt-map property. Switch the compatible string to the generic "st,stm32mp1-exti", in place of the specific "st,stm32mp13-exti". Older DT using compatible "st,stm32mp13-exti" will still work as the driver remains backward compatible. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp131.dtsi | 49 +++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index b04d24c939c3..14bd1c9bedd9 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1093,10 +1093,57 @@ rcc: rcc@50000000 { }; =20 exti: interrupt-controller@5000d000 { - compatible =3D "st,stm32mp13-exti", "syscon"; + compatible =3D "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells =3D <2>; + #address-cells =3D <0>; reg =3D <0x5000d000 0x400>; + + exti-interrupt-map { + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-map-mask =3D <0xffffffff 0>; + interrupt-map =3D + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <44 0 &intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" From: Christian Bruel The GIC of STM32MP25 includes v2m extension for PCIEe MSI support. Add the v2m sub-node to the GIC interrupt controller and adapt the other properties accordingly. Signed-off-by: Christian Bruel Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 96859d098ef8..5c9095382cc7 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -81,12 +81,20 @@ scmi_reset: protocol@16 { intc: interrupt-controller@4ac00000 { compatible =3D "arm,cortex-a7-gic"; #interrupt-cells =3D <3>; - #address-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <2>; interrupt-controller; reg =3D <0x0 0x4ac10000 0x0 0x1000>, <0x0 0x4ac20000 0x0 0x2000>, <0x0 0x4ac40000 0x0 0x2000>, <0x0 0x4ac60000 0x0 0x2000>; + ranges; + + v2m0: v2m@48090000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; =20 psci { --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E065673510; 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charset="utf-8" Update the device-tree stm32mp251.dtsi by adding the nodes for exti1 and exti2 interrupt controllers. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 172 +++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 5dd4f3580a60f..1426446ca1b11 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -168,6 +168,99 @@ package_otp@1e8 { }; }; =20 + exti1: interrupt-controller@44220000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + reg =3D <0x44220000 0x400>; + interrupts-extended =3D + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_80 */ + <0>, + <0>, + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; @@ -322,5 +415,84 @@ gpioz: gpio@46200000 { }; =20 }; + + exti2: interrupt-controller@46230000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + reg =3D <0x46230000 0x400>; + interrupts-extended =3D + <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <0>, + <0>, + <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ + }; }; }; --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7029D208B0; Mon, 15 Apr 2024 13:52:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189175; cv=none; b=hhq7O8fQBrVd8lm2GfRuam0scOp1eEI13zUTneS8n4NJDoXJJirgKHb9fwaavs6FR06IFeOpC8z75JW+kjCd3zGlbadtDGHToYl1nSoHxcrj7UcEZBDlfdhKF1YZVYjbJKg3pWC28XPvM9NHKYUEau8xY8XgS5SpHaRglOdxA0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713189175; c=relaxed/simple; bh=U+4pgle3dsFiaWJNGuuL2e5Su5y14I72sd1m/tBMuo0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DJADNS2RazbutOMBHo5T1gj4qjzolsoKKzazPOtTMWCcIugOguKN0UBS0YcF9Uidbl8KU4HIG/EwxSnJJrvgWxnkgGL2VfITJJiRCJ3NUraM6DNLuhceBrVj+DPzjd2c1lVzhNHwbUwPkZ1hIDvo8IHpERPAS7rTmaCKmszgCNU= ARC-Authentication-Results: i=1; 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charset="utf-8" Add exti1 as interrupt parent for the two pin controllers. Add the additional required property st,syscfg. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 1426446ca1b11..e7d1614dc744c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -271,6 +271,8 @@ pinctrl: pinctrl@44240000 { #size-cells =3D <1>; compatible =3D "st,stm32mp257-pinctrl"; ranges =3D <0 0x44240000 0xa0400>; + interrupt-parent =3D <&exti1>; + st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; =20 gpioa: gpio@44240000 { @@ -400,6 +402,8 @@ pinctrl_z: pinctrl@46200000 { #size-cells =3D <1>; compatible =3D "st,stm32mp257-z-pinctrl"; ranges =3D <0 0x46200000 0x400>; + interrupt-parent =3D <&exti1>; + st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; =20 gpioz: gpio@46200000 { --=20 2.34.1 From nobody Fri Dec 19 05:27:49 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C5311C282; 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charset="utf-8" Update the device-tree stm32mp251.dtsi by adding the nodes for exti1 and exti2 interrupt controllers. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 140 +++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 5c9095382cc7..4253f5bcd000 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -164,6 +164,86 @@ package_otp@1e8 { }; }; =20 + exti1: interrupt-controller@44220000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + reg =3D <0x44220000 0x400>; + + exti-interrupt-map { + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-map-mask =3D <0xffffffff 0>; + interrupt-map =3D + <0 0 &intc 0 0 GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <18 0 &intc 0 0 GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc 0 0 GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc 0 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <36 0 &intc 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <38 0 &intc 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <39 0 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <41 0 &intc 0 0 GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <42 0 &intc 0 0 GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <44 0 &intc 0 0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <45 0 &intc 0 0 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <59 0 &intc 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <72 0 &intc 0 0 GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <73 0 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <74 0 &intc 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <75 0 &intc 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <76 0 &intc 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <77 0 &intc 0 0 GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <78 0 &intc 0 0 GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <79 0 &intc 0 0 GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <83 0 &intc 0 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <84 0 &intc 0 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; @@ -318,5 +398,65 @@ gpioz: gpio@46200000 { }; =20 }; + + exti2: interrupt-controller@46230000 { + compatible =3D "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + reg =3D <0x46230000 0x400>; + + exti-interrupt-map { + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-map-mask =3D <0xffffffff 0>; + interrupt-map =3D + <0 0 &intc 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <51 0 &intc 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <62 0 &intc 0 0 GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <65 0 &intc 0 0 GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <66 0 &intc 0 0 GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" Add exti1 as interrupt parent for the two pin controllers. Add the additional required property st,syscfg. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 4253f5bcd000..6d46450afd4d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -254,6 +254,8 @@ pinctrl: pinctrl@44240000 { #size-cells =3D <1>; compatible =3D "st,stm32mp257-pinctrl"; ranges =3D <0 0x44240000 0xa0400>; + interrupt-parent =3D <&exti1>; + st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; =20 gpioa: gpio@44240000 { @@ -383,6 +385,8 @@ pinctrl_z: pinctrl@46200000 { #size-cells =3D <1>; compatible =3D "st,stm32mp257-z-pinctrl"; ranges =3D <0 0x46200000 0x400>; + interrupt-parent =3D <&exti1>; + st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; =20 gpioz: gpio@46200000 { --=20 2.34.1