From nobody Sun Feb 8 06:00:06 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F7B1130ADA; Thu, 15 Feb 2024 14:20:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708006819; cv=none; b=VbyDRIfWDXP850LP9gooQloeam+dsXpOybHuC8wvQy0sKeSvFR4zx5hUuGZzl31RJEnXRx55MIzeS1W8Pa9oYBSYwpNnZFnQGBQVG+QgB1IHuwz+et0qA+JcXbpFeJNmiGFGI1g7HcBLlWp2LgRVBjWiB3cXBzDlOvoh3YI7IVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708006819; c=relaxed/simple; bh=PullOvSOvstiiYMgcHnwd9VygvmFZsrOtFt1fJGokB8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=nv2BCoS8e02/bxoWJ7AyVHsIgk17SiorGFPn5RumaSqs4NlQw9UYzxP42RgAyRjKV2jh1MzAtrIaaDbZXrLJGDnbLU/EWmlyGhzXaibtaf9DZ859ixqtQKbybdu+sohu/B4sacoWHVveyRSEYdfQLJmEnVOr11vwbVFpoBF4Pds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SJeGbuhm; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SJeGbuhm" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41FEJxtx023347; Thu, 15 Feb 2024 08:19:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1708006799; bh=u5Efv4NH6LtRrGCMOj0uLzoSpUJhq4ciZ4y37cudC9g=; h=From:To:CC:Subject:Date; b=SJeGbuhmmiKwNumDR9Ol4SGBOoTiuhxWP07VL++Zr7U2cnkukDtwhM+lOFmKYoHGL 3/Rcn8B2tZ32xNWzrK3qKctRM3pqfh2jFth+cD3QLLvQWvJ2IM3zgMcWBZNsCQPZLt KVadkClvyklkmzKPA5WTrwxKaR8C32W2H3DPazDg= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41FEJxZb016848 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 08:19:59 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 08:19:59 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 08:19:58 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41FEJwiL057677; Thu, 15 Feb 2024 08:19:58 -0600 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Peter Rosin CC: , , , Andrew Davis Subject: [PATCH] arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux Date: Thu, 15 Feb 2024 08:19:57 -0600 Message-ID: <20240215141957.13775-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Change offset in mux-reg-masks property for hbmc_mux node since reg-mux property is used in compatible. While here, update the reg region to include 4 bytes as this is a 32bit register. Fixes: 2765149273f4 ("mux: mmio: use reg property when parent device is not= a syscon") Suggested-by: Peter Rosin Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 40caa86e600fe..4618b697fbc47 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -353,9 +353,9 @@ fss: bus@47000000 { =20 hbmc_mux: mux-controller@47000004 { compatible =3D "reg-mux"; - reg =3D <0x00 0x47000004 0x00 0x2>; + reg =3D <0x00 0x47000004 0x00 0x4>; #mux-control-cells =3D <1>; - mux-reg-masks =3D <0x4 0x2>; /* HBMC select */ + mux-reg-masks =3D <0x0 0x2>; /* HBMC select */ }; =20 hbmc: hyperbus@47034000 { --=20 2.39.2