From nobody Wed Dec 17 05:57:23 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBB831DDDB; Thu, 15 Feb 2024 10:30:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707993058; cv=none; b=nUwGwN+K+Zhc6gDT2QnaEl2JpzhIOTZTAENibAZtE2tnnaxVTB8m40yzQs7fWIt9c4r10re02y4yAe0QkfbkTe2GVvUGIoucNWXyhz7okOJLU/hGKtLheAHhPM27USVx09RUNyToZYHwCl4JpxqO4eyy3WGqpKdSpV8KCGfB2Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707993058; c=relaxed/simple; bh=lFCW+S4RlRFZM8WxmSRzupQnZ8R5azS/EIsucaneiRE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GX22u9Q82gmGeslJxR76lOrcgibb0AS2KfPwlSQX9iPK2Z5c5YYkmtZ+4jZ2W/SY+zorIGzxNoxTkm5jS2a3pGyXqOFid0uml74w9uIJSgtnz3TUfL+jRXCRPfbizbcwatHvVsYC2GsUvV+fdcwWJwRnDQcMfqx4rR5W11pCh58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=D0vwUR8R; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="D0vwUR8R" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41FAUfpt095113; Thu, 15 Feb 2024 04:30:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707993041; bh=xUh4OTnhvZ4QilgxMoyStbN6234r5hgOwbudObkOCDE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D0vwUR8Rm2uES/7J2/lEnjZ/qAkKfrFxsbtM8sWj5NQEGqTLVBzjbUe//cuCeuiCE W4LXTYHJMUwDQWQNf7ZQoONKAAEzjUY81fScQyfng2WIWs1WvWripfpP1S7uwTX2Fr X6oHbmhrTD9/YCrorW7kq0Luz1PA+hBx5jDAq3OY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41FAUfsx041766 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 04:30:41 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 04:30:40 -0600 Received: from fllvsmtp7.itg.ti.com (10.64.40.31) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 04:30:40 -0600 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by fllvsmtp7.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41FAUeSI004604; Thu, 15 Feb 2024 04:30:40 -0600 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 41FAUedS031772; Thu, 15 Feb 2024 04:30:40 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Andrew Lunn , Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , "Tero Kristo" , , , "Roger Quadros" , Suman Anna , Grygorii Strashko , MD Danish Anwar Subject: [PATCH v5 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes Date: Thu, 15 Feb 2024 16:00:34 +0530 Message-ID: <20240215103036.2825096-2-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215103036.2825096-1-danishanwar@ti.com> References: <20240215103036.2825096-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Suman Anna The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko Signed-off-by: Suman Anna Reviewed-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index ddd382a0d735..c678366623b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1225,6 +1225,18 @@ icssg0_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg0_iep0: iep@2e000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2e000 0x1000>; + clocks =3D <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2f000 0x1000>; + clocks =3D <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible =3D "ti,pruss-mii", "syscon"; reg =3D <0x32000 0x100>; @@ -1366,6 +1378,18 @@ icssg1_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg1_iep0: iep@2e000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2e000 0x1000>; + clocks =3D <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2f000 0x1000>; + clocks =3D <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible =3D "ti,pruss-mii", "syscon"; reg =3D <0x32000 0x100>; --=20 2.34.1 From nobody Wed Dec 17 05:57:23 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81B8E78676; Thu, 15 Feb 2024 10:30:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707993056; cv=none; b=VMagfTc0Ew5nakPksKOVY8zuzq1XMzlL7wLV4Fe4GNdMZitxBLZLEB9kp+5hvCU4q9H5SuMYDO8sd+hZ2OSsdYo1vjWRLP/qNQJm8HTtg6frIGBYFgSk2L2ui+K3wrZFNU6TGrSCmSPjZw0YooHLl91yr5kE7kODV0Yl+UVBnRg= ARC-Message-Signature: i=1; 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Thu, 15 Feb 2024 04:30:42 -0600 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by fllvsmtp8.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41FAUg9Y123701; Thu, 15 Feb 2024 04:30:42 -0600 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 41FAUfiT031779; Thu, 15 Feb 2024 04:30:42 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Andrew Lunn , Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , Tero Kristo , , , Roger Quadros , MD Danish Anwar Subject: [PATCH v5 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support Date: Thu, 15 Feb 2024 16:00:35 +0530 Message-ID: <20240215103036.2825096-3-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215103036.2825096-1-danishanwar@ti.com> References: <20240215103036.2825096-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) port is kept disable and ICSSG1 is enabled in single MAC mode by default. Reviewed-by: Ravi Gunasekaran Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 5c546ae76d3e..daa925106856 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -32,6 +32,7 @@ aliases { mmc1 =3D &sdhci1; ethernet0 =3D &cpsw_port1; ethernet1 =3D &cpsw_port2; + ethernet2 =3D &icssg1_emac0; }; =20 memory@80000000 { @@ -229,6 +230,64 @@ transceiver2: can-phy1 { max-bitrate =3D <5000000>; standby-gpios =3D <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible =3D "ti,am642-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>; + sram =3D <&oc_sram>; + ti,prus =3D <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&= tx_pru1_1>; + firmware-name =3D "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt =3D <&icssg1_mii_g_rt>; + ti,mii-rt =3D <&icssg1_mii_rt>; + ti,iep =3D <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent =3D <&icssg1_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + dmas =3D <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg1_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg1_phy1>; + phy-mode =3D "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg =3D <1>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + status =3D "disabled"; + }; + }; + }; }; =20 &main_pmx0 { @@ -383,6 +442,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 = */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins =3D < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD= 0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD= 1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD= 2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD= 3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_R= XC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX= _CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_= TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_T= D1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_T= D2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_= TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_T= XC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_T= X_CTL */ + >; + }; }; =20 &main_uart0 { @@ -725,3 +808,15 @@ &main_mcan1 { pinctrl-0 =3D <&main_mcan1_pins_default>; phys =3D <&transceiver2>; }; + +&icssg1_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg =3D <0xf>; + tx-internal-delay-ps =3D <250>; + rx-internal-delay-ps =3D <2000>; + }; +}; --=20 2.34.1 From nobody Wed Dec 17 05:57:23 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 033EE77F2E; Thu, 15 Feb 2024 10:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707993055; cv=none; b=BDMnK8lQtKHb38nVlz7nATYA+LQqKaLNYAHZpiaXPNAg5rE3Z9tQ4yF73U31fXeli9dbMXRuPcZL8veIYzLOnrJEmxc9EDyFE0UQaIetg5Y7jG4XpT8qlknhvEjdMxlMr6L/ckxSNSs5IBNCd0kH0mWutDClpAmK4YgaVdDeYTs= ARC-Message-Signature: i=1; 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Thu, 15 Feb 2024 04:30:44 -0600 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41FAUirx060404; Thu, 15 Feb 2024 04:30:44 -0600 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 41FAUhdZ031785; Thu, 15 Feb 2024 04:30:44 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Andrew Lunn , Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , Tero Kristo , , , Roger Quadros , MD Danish Anwar Subject: [PATCH v5 3/3] arm64: dts: ti: k3-am642-evm: add overlay for ICSSG1 2nd port Date: Thu, 15 Feb 2024 16:00:36 +0530 Message-ID: <20240215103036.2825096-4-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215103036.2825096-1-danishanwar@ti.com> References: <20240215103036.2825096-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Add label name 'mdio_mux_1' for 'mdio-mux-1' node so that the node 'mdio-mux-1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Reviewed-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/Makefile | 5 ++ .../dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 79 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 4a570dffb638..2d255f31b3a6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg1-dualemac.dtbo =20 # Boards with AM65x SoC k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-base-board-rock= tech-rk101-panel.dtbo @@ -106,6 +107,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am642-evm-icssg1-dualemac-dtbs :=3D \ + k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ @@ -122,6 +125,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am642-evm-icssg1-dualemac.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb =20 @@ -131,6 +135,7 @@ DTC_FLAGS_k3-am625-sk +=3D -@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ +DTC_FLAGS_k3-am642-evm +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso b/arc= h/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 000000000000..af2fd3e7448b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 =3D "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible =3D "mdio-mux-multiplexer"; + mux-controls =3D <&mdio_mux>; + mdio-parent-bus =3D <&icssg1_mdio>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + mdio@0 { + reg =3D <0x0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg1_phy2: ethernet-phy@3 { + reg =3D <3>; + tx-internal-delay-ps =3D <250>; + rx-internal-delay-ps =3D <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL= */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0= */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 = */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 = */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3= */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC = */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_C= TL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 =3D <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status =3D "disabled"; +}; + +&mdio_mux_1 { + status =3D "disabled"; +}; + +&icssg1_eth { + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default= >; +}; + +&icssg1_emac1 { + status =3D "okay"; + phy-handle =3D <&icssg1_phy2>; + phy-mode =3D "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index daa925106856..03dac3adebde 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -199,7 +199,7 @@ mdio_mux: mux-controller { mux-gpios =3D <&exp1 12 GPIO_ACTIVE_HIGH>; }; =20 - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible =3D "mdio-mux-multiplexer"; mux-controls =3D <&mdio_mux>; mdio-parent-bus =3D <&cpsw3g_mdio>; --=20 2.34.1