From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EE7669D20 for ; Thu, 15 Feb 2024 10:11:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991892; cv=none; b=ix+xMLBn/3Aj3nduUb32phQM/KLbT+FU4P+FS6Wf5PQHbjREmimpQLq9cJuCLRtJ1Ymrl6bJ2/l/+O2Fh2or5q2a01EW87C8mrKsmdpil76d9gGeeXZa++dmDyVK6RW6OO2ZZe7lNJQk4v8qRDGe9GuX6Vq8kiXRdh26G8YX/jU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991892; c=relaxed/simple; bh=2K0Qe0+Y9Ky3oImutyQ/r4aStFsoJzNLaI0LOxUc26U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iqMP8Vsj1Spm7qMiUgBSGjHCYpgBcyXOYgzHiPXVWzuJF0aZiEFyBkm9H0VOasBKrxFGq7F3uqQdgkjPXU8GwHt+UETFwsLPtVydFZjvtmCUIm+wxdcxRsVs0Btb2Ij6YlmerPfmGzVOnjYUfcusloxlmFyxgIBDsbsmkKfar/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=mgUhkzgD; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mgUhkzgD" X-UUID: 924c372acbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=o7dMHDyYlKWxpD3CFPLXVYn1RcqkLJwusXwZ46FWLUw=; b=mgUhkzgDPI3PhNxBYgJe/ZMbcJ49HnHUmjENgV1QhkM+i0mOaZCbxkrgNgJ+2Mk91nPdCZhejkg5DIjoaGytoT8ZCBihOM4ICzh8U1M8zKTyp4/3N5z2xVsZzy8Yo66O1hYtmSHIzLyvOt/6CzDQaA6PUFcXOneGWK1M5pFSZpw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:d8f8ba44-cbbc-4343-94ae-e9a66f7f55c2,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:b54d528f-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 924c372acbea11eea2298b7352fd921d-20240215 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 68608691; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:21 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 01/13] soc: mediatek: Disable 9-bit alpha in ETHDR Date: Thu, 15 Feb 2024 18:11:07 +0800 Message-ID: <20240215101119.12629-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.084300-8.000000 X-TMASE-MatchedRID: Rj8ugvyJmEO+Yp4vsvc0tLMsPmSZxbpksvllF/5zpT3jsTquy0JRi0fp kQx2u0Ks+qmOSYkzMxl1VEmx7sTk/25/NyTKlG694bl1FkKDELcoteqd/zXaI/ufvd3T2+v3dHv iJhofy1Hi8zVgXoAltsIJ+4gwXrEtJ0RPnyOnrZJwhH7yAuWrPPJZnPx9vad3szm63XzKi/h9jP F3getekOuu3S58dvEz2cmO8/NMzsW9I44FsV4xl6RiSHghYnKatreCV5++y/GAhOcaQrQ0U1GyR coeF18qmKP0zzpTAeGwod8xOMKmvA1Aka/KIp/p X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.084300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 1B42D6AF1AC7EC4A5BDE7B4B622C00193883788785C070178D5B5D961F7FCE572000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ETHDR 9-bit alpha should be disabled by default, otherwise alpha blending will not work. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index afb2c40c85c15..00eff18a3bcea 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -236,6 +236,7 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int = idx, bool alpha_sel, u16 =20 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4,= ~0, alpha << 16 | alpha, cmdq_pkt); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, c= mdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C1269D24 for ; Thu, 15 Feb 2024 10:11:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991891; cv=none; b=sAH70Yki/Wl552SH9XRK80J7Z92KD+zWx7VRrLsn7XPrHtU6T80i10xL1Qsi1zsBnnaeKXzC/ega+Yeusero3mNwrAdKpjyT1gZWEBa1lSHhAD0F+yk+uCxUP+h1NjH2/o5AdUHX+CocV6qZaleYF/2ZMxL1oGV10Sjw0GdB/Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991891; c=relaxed/simple; bh=gWHBDgSOTYFMxv/jwjWssvJfrKCERyo80TlI8JemzRU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DrpgwQd3Zr5S5TVbvD3kR0p4TpopFXHGRUBoslT8uAZ3iCXtRpeFmfu/1X/WoGIr3VdLnWFLjfVYabxsxttSUiRsrMag1xEJci0P5lZDUzq7gcdI7MyHTjFNGY43cVHDGVQAsbH9pi4jYmgv4rMCt3lYJbvY3ebsRqyBGGG92WU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Z2vpxI5T; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z2vpxI5T" X-UUID: 92515160cbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j2PUb2FOAEIMk7MkRhuGPiTn5JVd27Vx1Ioy8tgssgE=; b=Z2vpxI5TVF59snb5I0tYrFLp3FZ9GWz1388FxRUGGP9Fr3p+ZltBxsPC9CWJ800OEBcorXCtwZ5ab0YEgb5zJam7z+stpvxFvptU6qeS3ZdiR9yNigOcosGngijG5y7c+y55/8ZhAU2lQyFuYMXtCoxmt7P3poydgRQWg0GLksE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:39786f34-e60f-42a8-b9f1-e64855859b06,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6f543d0,CLOUDID:5a636b80-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 92515160cbea11eea2298b7352fd921d-20240215 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1044946201; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:21 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 02/13] drm/mediatek: Add OVL compatible name for MT8195 Date: Thu, 15 Feb 2024 18:11:08 +0800 Message-ID: <20240215101119.12629-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.645500-8.000000 X-TMASE-MatchedRID: GIpmbigRs3bREKzvS64+oRWCVBr+Ay986SXuwUgGH0hbKBBN5zqG8AYB 5gsbo0L8o5qw/iFKtvYBtjkcfRMmqZH0YXYnbGozFEUknJ/kEl7dB/CxWTRRu+rAZ8KTspSzEi3 RtA+MN2j5QetUecY4pjewEY3isXHskmcADZfERrb7YScvHGI+s/9aJ3Fk8P+JAthyou0E3ktMyX ZOCOvF4KWtbghw5BC9F0aD5ljt43pMcHZD6gqu7wxMjfifIXfowkvVoA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.645500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 5F9259228736A3FBB0D90F4767931191BAC68F2D83900545EC1D59DE3F1F260F2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OVL compatible name for MT8195. Without this commit, DRM won't work after modifying the device tree. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index cc746de91834c..890e1e93a2227 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -762,6 +762,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8195-disp-ovl", + .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8B7B69D0D for ; Thu, 15 Feb 2024 10:11:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991889; cv=none; b=Thq3vn2J8AMZWDQYCM1yox808q9mswLuf57cZPSVtMsBrjoeRnkL8KSaiJdPatoZpVzy87qYTnyHgpabGYa+OohX0s9GZ6bl8TWDFum1CJfy/URASp8fduKUH7jPawFxr3UEzDlRvTwiFZvDZWZKdVawW4cfZzD5lTssBclnkP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991889; c=relaxed/simple; bh=Tcf7gGmH1pUx273AfxUf0JZ683ChpZg2rGqMNjoeJqo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Y9QXW+cu8T6eeMHFstvisswDKtX77ujegIXLnMbUo/SoOJ6wZG9G8TbL0TozBtGW/llpegMZFRk0AOWDEv2HS9YXVrJngcYVv3kkPWdDqiO50bf0cBl9Jg1JNnyMLbVyuNkNtqVvoWrK2+BcaNBFJMT1NreoRNFM02Ew2taAFJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=R+2DYQMu; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="R+2DYQMu" X-UUID: 925a641ccbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0UW764IqKZlZdsFXqAecqzBj01NU6yDWNFVceMLD5+8=; b=R+2DYQMuhXLqZd12mJbCDvmcnLX0mCMIUyrOLl3v4PKwvNRTnaVPTm6jh8v03DZipvLa1Ii7+Nh41qvFChWANquBx0RiaWEpcAwqy6hXbcKTaR3fO9tszUyhtuLXgtAEWr4oPY2wu1his9PaHoRWPaH/fx8/xT6ff4yqo6l2rUA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:cc6cc8f3-e1ea-4d82-a108-3e58c60053a8,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:b64d528f-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 925a641ccbea11eea2298b7352fd921d-20240215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 88760807; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:21 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 03/13] drm/mediatek: Add missing plane settings when async update Date: Thu, 15 Feb 2024 18:11:09 +0800 Message-ID: <20240215101119.12629-4-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.918200-8.000000 X-TMASE-MatchedRID: 1uypKmLkdmcgNXYDo2rRhsLcTtMlPIaVKx5ICGp/WtGdCqKtxM6bh64N WivjR4eGLYexjI/F2s67aBKK8e6y8yUtdpGicV4RA9lly13c/gHt/okBLaEo+NwQ5VDi3O9Bo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqt47Is4r3/A5IJ6yLwsxgF/630/ZW9qu348SPRFJwtcxhpr/ zo9DQwBPIqHmvLgj9d/1p729Dtsi3b8InIzH6cbZJKBVkiWQLYwZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5p3LlElBHTlw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.918200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8B041C672F0B02B6BD49352870BD20393DEE1D2E9FBC513DD2A7637DE91263552000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix an issue that plane coordinate was not saved when calling async update. Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic up= date") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/med= iatek/mtk_drm_plane.c index ddc9355b06d51..f10d4cc6c2234 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -227,6 +227,8 @@ static void mtk_plane_atomic_async_update(struct drm_pl= ane *plane, plane->state->src_y =3D new_state->src_y; plane->state->src_h =3D new_state->src_h; plane->state->src_w =3D new_state->src_w; + plane->state->dst.x1 =3D new_state->dst.x1; + plane->state->dst.y1 =3D new_state->dst.y1; =20 mtk_plane_update_new_state(new_state, new_plane_state); swap(plane->state->fb, new_state->fb); --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D73806A356 for ; Thu, 15 Feb 2024 10:11:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; cv=none; b=mwobVs/RY4sOmMJdN97gBXudyAwUIPGlkvZUDIR8r6zg1MmUmbPybcKxieYMm1A9zRAvPNh1QIl9fjHRgi4E2iFsy+wIgpaccAWy/oG0uPZOxh2Qn8knoKD/6pDVvx3UezBmKtsXNQFDh0TM9BKvJl2kjzg0NHRBXhWaSq4DFqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; c=relaxed/simple; bh=oVScb3QsrAhkut/wVNKk0Gm6+3u3IV95GPV0PD1mYSA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XinpvftT/XnjADRdZ9Qszw/DnD+2yWQqrPqfRzJtWBsPwLo8cnQvUcCygtnYt+WTjF6e9R7H7nHIZn9cFD7s1pNo43Izq+uUmya//G4JLC7OBXuuVHT/B1jMVKklANBymu7iRScoY3Gml0Ca7NR9RzgRzbeVR5PRakFJ0SmLf+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Jg9Ts9v/; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Jg9Ts9v/" X-UUID: 925cf3a8cbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=y5O9N7gBJ9YynX66Tx+xiBM4fZt9lzNxS+JsnlX7gZc=; b=Jg9Ts9v/wAJn20EFSLEfBEenp/cveHgQ9xbxlAZM4IM2yVkeghDe2jThdigU2k2RtjT1ZWiI38LJ/sCymwfzjAfDlm6YT7z7t89Wl3z8rXKNOZiqEAGKiGv5O5fL0qmF3o+4LSBE9qZzHuL8pD27vnf+K/PCQ9yOxy/b19fgXWU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:a889ad8b-d6df-43b2-a105-d374a6b9e3e8,IP:0,U RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-50 X-CID-META: VersionHash:6f543d0,CLOUDID:0d70eb83-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:1,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 925cf3a8cbea11eea2298b7352fd921d-20240215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 533599165; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:21 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 04/13] drm/mediatek: Fix errors when reporting rotation capability Date: Thu, 15 Feb 2024 18:11:10 +0800 Message-ID: <20240215101119.12629-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.636000-8.000000 X-TMASE-MatchedRID: qKC9Lion//KU2fVedEQUO2NW0DAjL5p+Wot5Z16+u77vnm3ZesFzgvKC 81FnsF5IlTJXKqh1ne2rjfxn0AirrC2W7Y+Npd9Rh2VzUlo4HVNPZ8WbDkfxU56fSoF3Lt+M6bg Zy139hG9UOKk2VxzSJ1ixvQr0+Z/MOnfMHqHi4mn0mf9msa5zwdspPGnf5a0gmyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1vgPmisnFUWbXwI/jONLDvC7HnNEcltGLYnt8a3k1TsX/KqpkYjIexsC+k sT6a9fy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.636000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E90F10E76A8687E0E18E0F690897B51CE0CC013172CA94CC015DE292832A8D4D2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create rotation property according to the hardware capability. Since currently OVL of all chips support same rotation, no need to define it in the driver data. Fixes: 84d805753983 ("drm/mediatek: Support reflect-y plane rotation") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 19 +++++++------------ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +- 5 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 4a5661334fb1a..cd5ca5359b0f0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -126,6 +126,7 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *= dev, void (*vblank_cb)(vo void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev); void mtk_ovl_adaptor_enable_vblank(struct device *dev); void mtk_ovl_adaptor_disable_vblank(struct device *dev); +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev); void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 5aaf4342cdbda..c42fce38a35eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -289,6 +289,10 @@ unsigned int mtk_ovl_layer_nr(struct device *dev) =20 unsigned int mtk_ovl_supported_rotations(struct device *dev) { + /* + * although currently OVL can only do reflection, + * reflect x + reflect y =3D rotate 180 + */ return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } @@ -297,27 +301,18 @@ int mtk_ovl_layer_check(struct device *dev, unsigned = int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state =3D &mtk_state->base; - unsigned int rotation =3D 0; =20 - rotation =3D drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &=3D ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) !=3D 0) + /* check if any unsupported rotation is set */ + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; =20 /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. */ - if (state->fb->format->is_yuv && rotation !=3D 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; =20 - state->rotation =3D rotation; - return 0; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 6d4334955e3d3..d4a13a1402148 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -379,6 +379,15 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device = *dev, void (*vblank_cb)(vo vblank_cb, vblank_cb_data); } =20 +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev) +{ + /* + * should still return DRM_MODE_ROTATE_0 if rotation is not supported, + * or IGT will fail. + */ + return DRM_MODE_ROTATE_0; +} + void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 94590227c56a9..b47be6955d9b8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -417,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .get_formats =3D mtk_ovl_adaptor_get_formats, .get_num_formats =3D mtk_ovl_adaptor_get_num_formats, .mode_valid =3D mtk_ovl_adaptor_mode_valid, + .supported_rotations =3D mtk_ovl_adaptor_supported_rotations, }; =20 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/med= iatek/mtk_drm_plane.c index f10d4cc6c2234..2dc28a79f7603 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -338,7 +338,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, return err; 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 05/13] drm/mediatek: Set DRM mode configs accordingly Date: Thu, 15 Feb 2024 18:11:11 +0800 Message-ID: <20240215101119.12629-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set DRM mode configs limitation according to the hardware capabilities and pass the IGT checks as below: - The test "graphics.IgtKms.kms_plane" requires a frame buffer with width of 4512 pixels (> 4096). - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is defined, and run the test with cursor size from 1x1 to 512x512. Please notice that the test conditions may change as IGT is updated. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 890e1e93a2227..8cf157ec66ba6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -296,6 +296,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .conn_routes =3D mt8188_mtk_ddp_main_routes, .num_conn_routes =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, + .max_pitch =3D GENMASK(15, 0), + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -310,6 +313,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { .main_path =3D mt8195_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num =3D 2, + .max_pitch =3D GENMASK(15, 0), + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { @@ -317,6 +323,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 1_driver_data =3D { .ext_len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id =3D 1, .mmsys_dev_num =3D 2, + .max_pitch =3D GENMASK(15, 0), + .min_width =3D 2, /* 2-pixel align when ethdr is bypassed */ + .min_height =3D 1, }; =20 static const struct of_device_id mtk_drm_of_ids[] =3D { @@ -495,6 +504,18 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j =3D 0; j < private->data->mmsys_dev_num; j++) { priv_n =3D private->all_drm_private[j]; =20 + if (priv_n->data->max_pitch) { + /* Save 4 bytes for the color depth (pitch =3D width * bpp) */ + drm->mode_config.max_width =3D priv_n->data->max_pitch >> 2; + drm->mode_config.max_height =3D priv_n->data->max_pitch >> 2; + } + + if (priv_n->data->min_width) + drm->mode_config.min_width =3D priv_n->data->min_width; + + if (priv_n->data->min_height) + drm->mode_config.min_height =3D priv_n->data->min_height; + if (i =3D=3D CRTC_MAIN && priv_n->data->main_len) { ret =3D mtk_drm_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, @@ -522,6 +543,10 @@ static int mtk_drm_kms_init(struct drm_device *drm) } } =20 + /* IGT will check if the cursor size is configured */ + drm->mode_config.cursor_width =3D drm->mode_config.max_width; + drm->mode_config.cursor_height =3D drm->mode_config.max_height; + /* Use OVL device for all DMA memory allocations */ crtc =3D drm_crtc_from_index(drm, 0); if (crtc) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 33fadb08dc1c7..414764b4546ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,9 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + + u32 max_pitch; + int min_width, min_height; }; =20 struct mtk_drm_private { --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFDF069D18 for ; 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 06/13] drm/mediatek: Turn off the layers with zero width or height Date: Thu, 15 Feb 2024 18:11:12 +0800 Message-ID: <20240215101119.12629-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 777b7bc86a0a3 ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: fa97fe71f6f93 ("drm/mediatek: Add ETHDR support for MT8195") Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index d4a13a1402148..68a20312ac6f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -157,7 +157,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 07/13] drm/mediatek: Support alpha blending in display driver Date: Thu, 15 Feb 2024 18:11:13 +0800 Message-ID: <20240215101119.12629-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.987900-8.000000 X-TMASE-MatchedRID: x3Ubk3t+gcxo4JO2ZJOtUUKcYi5Qw/RVU+A7YkpDJ1haW2Ktn+I8/sz/ PYuNxvNIMWQ2vFVnCzvKeFqUCjYQAeRdshfO+/2p3y1ZMjVHx6my+WUX/nOlPQ2Y8xyy93kWkny 2PUPL6eBNbf7uoLznK8/PCmgLkWHoJS12kaJxXhED2WXLXdz+AQrefVId6fzVEvoxTu3fj1soEO 70Ha1CScb+TbMWrxk0gDLqnrRlXrYyF7rbsD7xod0H8LFZNFG7bkV4e2xSge55qDTYeZOJ41ARS 62TwUbAHZ5gm6COQK9P+VLujR8OVT6Qrn3xh/cy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.987900-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 0CDCBDF2AFBA346F7A109E9699FAC315776E24D3610380DA250F2C3C7367766B2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by adding correct blend mode property when the planes init. Before this patch, only the "Coverage" mode (default) is supported. For more information, there are three pixel blend modes in DRM driver: "None", "Pre-multiplied", and "Coverage". To understand the difference between these modes, let's take a look at the following two approaches to do alpha blending: 1. Straight: dst.RGB =3D src.RGB * src.A + dst.RGB * (1 - src.A) This is straightforward and easy to understand, when the source layer is compositing with the destination layer, it's alpha will affect the result. This is also known as "post-multiplied", or "Coverage" mode. 2. Pre-multiplied: dst.RGB =3D src.RGB + dst.RGB * (1 - src.A) Since the source RGB have already multiplied its alpha, only destination RGB need to multiply it. This is the "Pre-multiplied" mode in DRM. For the "None" blend mode in DRM, it means the pixel alpha is ignored when compositing the layers, only the constant alpha for the composited layer will take effects. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/med= iatek/mtk_drm_plane.c index 2dc28a79f7603..4e0206c45efd7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -346,6 +346,17 @@ int mtk_plane_init(struct drm_device *dev, struct drm_= plane *plane, DRM_INFO("Create rotation property failed\n"); } =20 + err =3D drm_plane_create_alpha_property(plane); + if (err) + DRM_ERROR("failed to create property: alpha\n"); + + err =3D drm_plane_create_blend_mode_property(plane, + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE)); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 return 0; --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6FFA6A353 for ; Thu, 15 Feb 2024 10:11:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; cv=none; b=f9CtwmudMHIKX+bsFfuovVKOeS34CNc6vy+vx3jjtkPf8x5EUTH871KwG4/8FJHntpmlOZKWEv8ZIC7PzMI3CWmsGrtKzCjMbN0tIrNSyx5o57P83OIh4bCOipa++tECMAoe6j/xNgAQyVyZ99dfgo4mvQcKV+HxR9jaKFGy5ME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; c=relaxed/simple; bh=knpYdobtWb7ITxxiCz3H4yM/DTY+kqjqmY2nna6TlWk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YB3OiA/BBO5wASjSqhJ17zzcJNb3Gnz8XdVQsCVXtD0Phic9uR/x+s5FWt/gTcI4IUwLohjGnnwJqTfFBLR3cumvnxz5XHKqz6qvUkmJn8ApKJvjCQOAp3sVarWTGdQWxVSAux1FsSRQrjytCO416oc+xa2XpzeBBWg7cU6FmW8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SoMuA3mG; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SoMuA3mG" X-UUID: 925f70b0cbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Bh54CrUmjht+EttVRp4xxlMaCLQOTJACukUzbcq6Rlo=; b=SoMuA3mGg+nzcM0151VvhGh9JCTtQgeJjApmC4YJJahEKBLPOhoQiiXb4C0Noj9Xz6Q2gXbGqmeIjvQLZkRQPy9Id17Z76m98zFeryJC8NOtPtfxdJfslKWlth1i32mbdDCqs3VSs2/DdG+RhVogQ52Rg7mLj73RFZfJ/0DoXYE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:9b489ef2-f81d-46ba-a19e-d423302d86d3,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6f543d0,CLOUDID:b94d528f-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 925f70b0cbea11eea2298b7352fd921d-20240215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 652071112; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:22 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 08/13] drm/mediatek: Support alpha blending in OVL Date: Thu, 15 Feb 2024 18:11:14 +0800 Message-ID: <20240215101119.12629-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--11.422500-8.000000 X-TMASE-MatchedRID: IVz/1v+EsXqc95xD+Eo4wGwbuvhCHs3cIfZjRfGTydgE6M1YtcX6vCtt gmG94b4GsoaiX/cNXYAnOAFYLaUTjQDNPxu11HXj4pdq9sdj8LW2McZY43zJ423D6f6IpbLIADR MoifoBflorIKifKWWgpFekOtgEgco1h970BFpuVIMH4SsGvRsA3cF/0kiqyh4eNDQ2odiEiHEZK HidzhUXGFAOEChoDSdWSIk5NxwrX50tvaBTTwwfMDORqgKKiYqPmpaNflBE4lshKp86qG4XKPFj JEFr+olwXCBO/GKkVqOhzOa6g8KraBhGN9wL6699f58OWKW5VIJPReTTpGttRDnu7o0L82DtHJp cJibaSI= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--11.422500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8FAECF8407891910EDE444F1DC316FB84B0D2E7E74C1867CF75EE1E2F1AE81C92000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support "Pre-multiplied" and "None" blend mode on MediaTek's chips. Before this patch, only the "Coverage" mode is supported. Please refer to the description of the commit "drm/mediatek: Support alpha blending in display driver" for more information. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 83 +++++++++++++++++++++---- 1 file changed, 72 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index c42fce38a35eb..98c989fddcc08 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -39,6 +39,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -52,13 +53,16 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) =20 +#define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_RGB_SWAP BIT(25) #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT= _MAN) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -72,6 +76,22 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) =20 +static inline bool is_10bit_rgb(u32 fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static const u32 mt8173_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -89,12 +109,20 @@ static const u32 mt8173_formats[] =3D { static const u32 mt8195_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, DRM_FORMAT_BGRA1010102, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_RGB565, @@ -254,9 +282,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, i= nt idx, u32 format, reg =3D readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); reg &=3D ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); =20 - if (format =3D=3D DRM_FORMAT_RGBA1010102 || - format =3D=3D DRM_FORMAT_BGRA1010102 || - format =3D=3D DRM_FORMAT_ARGB2101010) + if (is_10bit_rgb(format)) bit_depth =3D OVL_CON_CLRFMT_10_BIT; =20 reg |=3D OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); @@ -274,7 +300,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w !=3D 0 && h !=3D 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_= OVL_ROI_BGCLR); + + /* + * The background color should be opaque black (ARGB), + * otherwise there will be no effect with alpha blend + */ + mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); =20 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); @@ -352,7 +384,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int= idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -371,17 +404,37 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + return OVL_CON_BYTE_SWAP | + (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888); + case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888; + case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + return OVL_CON_RGB_SWAP | + (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888); + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; @@ -403,6 +456,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int blend_mode =3D state->base.pixel_blend_mode; + unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -420,9 +475,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } + + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) + ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; @@ -439,8 +500,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq= _reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pi= xel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 518F169DE0 for ; Thu, 15 Feb 2024 10:11:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 09/13] drm/mediatek: Support alpha blending in Mixer Date: Thu, 15 Feb 2024 18:11:15 +0800 Message-ID: <20240215101119.12629-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.610000-8.000000 X-TMASE-MatchedRID: x3Ubk3t+gcyc95xD+Eo4wGwbuvhCHs3cIfZjRfGTydgE6M1YtcX6vCtt gmG94b4GsoaiX/cNXYAnOAFYLaUTjQDNPxu11HXjhK8o4aoss8oK3n1SHen81f0TP/kikeqnij7 d44eIVPgo8SIkxCqNtQ2D76bNs2ltQF24kZp9Ww91e7Xbb6Im2greImldQ5BD8cWgFw6wp7MsX2 NvG8rX7UT88A7P9JJ2gAYZl0IbohgfE8yM4pjsDwtuKBGekqUpI/NGWt0UYPABwR31Oy+hyZ1BE 5qIRp0uul8kmJIfbswQ5ZNI9t/XNsLAQYGtsIDO X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.610000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A41FF608559A818A0AEFA4BEB52C7D501EC40F52B3E4200902B2B24E3CD23DF32000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support "Pre-multiplied" and "None" blend mode on MediaTek's chips. Before this patch, only the "Coverage" mode is supported. Please refer to the description of the commit "drm/mediatek: Support alpha blending in display driver" for more information. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 69872b77922eb..e95331c068151 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -35,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, struct mtk_plane_pending_state *pending =3D &state->pending; unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); - unsigned int alpha_con =3D 0; + unsigned int mix_con =3D NON_PREMULTI_SOURCE; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -170,19 +173,28 @@ void mtk_ethdr_layer_config(struct device *dev, unsig= ned int idx, return; } =20 - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; + mix_con |=3D MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - DEFAULT_9BIT_ALPHA, + if (state->base.pixel_blend_mode !=3D DRM_MODE_BLEND_COVERAGE) + mix_con |=3D PREMULTI_SOURCE; + + if (state->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_= ALPHA, pending->x & 1 ? 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 10/13] drm/mediatek: Support CRC in display driver Date: Thu, 15 Feb 2024 18:11:16 +0800 Message-ID: <20240215101119.12629-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register CRC related function pointers to support CRC retrieval. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 239 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 39 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 + 3 files changed, 281 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index 14cf75fa217f9..6cb1ed419dee7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -68,6 +68,9 @@ struct mtk_drm_crtc { /* lock for display hardware access */ struct mutex hw_lock; bool config_updating; + + struct mtk_ddp_comp *crc_provider; + unsigned int frames; }; =20 struct mtk_crtc_state { @@ -635,6 +638,14 @@ static void mtk_crtc_ddp_irq(void *data) struct drm_crtc *crtc =3D data; struct mtk_drm_crtc *mtk_crtc =3D to_mtk_crtc(crtc); struct mtk_drm_private *priv =3D crtc->dev->dev_private; + struct mtk_ddp_comp *comp =3D mtk_crtc->crc_provider; + + /* + * crc providers should make sure the crc is always correct + * by resetting it in .crc_read() + */ + if (crtc->crc.opened) + comp->funcs->crc_read(comp->dev); =20 #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) @@ -646,6 +657,24 @@ static void mtk_crtc_ddp_irq(void *data) if (!priv->data->shadow_register) mtk_crtc_ddp_config(crtc, NULL); #endif + + /* + * drm_crtc_add_crc_entry() could take more than 50ms to finish + * put it at the end of the isr + */ + if (crtc->crc.opened) { + /* + * skip the first crc because the first frame is configured by + * mtk_crtc_ddp_hw_init() when atomic enable + */ + if (++mtk_crtc->frames > 1) { + drm_crtc_add_crc_entry(crtc, true, + drm_crtc_vblank_count(crtc), + comp->funcs->crc_entry(comp->dev)); + } + } else { + mtk_crtc->frames =3D 0; + } mtk_drm_finish_page_flip(mtk_crtc); } =20 @@ -704,6 +733,40 @@ static void mtk_drm_crtc_update_output(struct drm_crtc= *crtc, } } =20 +static int mtk_drm_crtc_set_crc_source(struct drm_crtc *crtc, const char *= src) +{ + if (src && strcmp(src, "auto") !=3D 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + return 0; +} + +static int mtk_drm_crtc_verify_crc_source(struct drm_crtc *crtc, + const char *src, + size_t *cnt) +{ + struct mtk_drm_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp =3D mtk_crtc->crc_provider; + + if (!comp) { + DRM_ERROR("%s(crtc-%d): no crc provider\n", + __func__, drm_crtc_index(crtc)); + return -ENOENT; + } + + if (src && strcmp(src, "auto") !=3D 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + + *cnt =3D comp->funcs->crc_cnt(comp->dev); + + return 0; +} + int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plan= e, struct mtk_plane_state *state) { @@ -841,6 +904,8 @@ static const struct drm_crtc_funcs mtk_crtc_funcs =3D { .atomic_destroy_state =3D mtk_drm_crtc_destroy_state, .enable_vblank =3D mtk_drm_crtc_enable_vblank, .disable_vblank =3D mtk_drm_crtc_disable_vblank, + .set_crc_source =3D mtk_drm_crtc_set_crc_source, + .verify_crc_source =3D mtk_drm_crtc_verify_crc_source, }; =20 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs =3D { @@ -1033,6 +1098,11 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, =20 if (comp->funcs->ctm_set) has_ctm =3D true; + + if (comp->funcs->crc_cnt && + comp->funcs->crc_entry && + comp->funcs->crc_read) + mtk_crtc->crc_provider =3D comp; } =20 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, @@ -1137,3 +1207,172 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, =20 return 0; } + +void mtk_drm_crc_init(struct mtk_drm_crc *crc, + const u32 *crc_offset_table, size_t crc_count, + u32 reset_offset, u32 reset_mask) +{ + crc->ofs =3D crc_offset_table; + crc->cnt =3D crc_count; + crc->rst_ofs =3D reset_offset; + crc->rst_msk =3D reset_mask; + crc->va =3D kcalloc(crc->cnt, sizeof(*crc->va), GFP_KERNEL); + if (!crc->va) { + DRM_ERROR("failed to allocate memory for crc\n"); + crc->cnt =3D 0; + } +} + +void mtk_drm_crc_read(struct mtk_drm_crc *crc, void __iomem *reg) +{ + if (!crc->cnt || !crc->ofs || !crc->va) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + /* sync to see the most up-to-date copy of the DMA buffer */ + dma_sync_single_for_cpu(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); +#else + /* read crc with cpu for the platforms without cmdq */ + { + u32 n; + + for (n =3D 0; n < crc->cnt; n++) + crc->va[n] =3D readl(reg + crc->ofs[n]); + + n =3D readl(reg + crc->rst_ofs); + + /* pull reset bit */ + n |=3D crc->rst_msk; + writel(n, reg + crc->rst_ofs); + + /* release reset bit */ + n &=3D ~crc->rst_msk; + writel(n, reg + crc->rst_ofs); + } +#endif +} + +void mtk_drm_crc_destroy(struct mtk_drm_crc *crc) +{ + if (!crc->cnt) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (crc->pa) { + dma_unmap_single(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_TO_DEVICE); + crc->pa =3D 0; + } + if (crc->cmdq_client.chan) { + mtk_drm_cmdq_pkt_destroy(&crc->cmdq_handle); + mbox_free_channel(crc->cmdq_client.chan); + crc->cmdq_client.chan =3D NULL; + } +#endif + kfree(crc->va); + crc->va =3D NULL; + crc->cnt =3D 0; +} + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +void mtk_drm_crc_cmdq_create(struct device *dev, struct mtk_drm_crc *crc) +{ + int i; + + if (!crc->cnt) { + dev_warn(dev, "%s: not support\n", __func__); + goto cleanup; + } + + if (!crc->ofs) { + dev_warn(dev, "%s: not defined\n", __func__); + goto cleanup; + } + + crc->cmdq_client.client.dev =3D dev; + crc->cmdq_client.client.tx_block =3D false; + crc->cmdq_client.client.knows_txdone =3D true; + crc->cmdq_client.client.rx_callback =3D NULL; + crc->cmdq_client.chan =3D mbox_request_channel(&crc->cmdq_client.client, = 0); + if (IS_ERR(crc->cmdq_client.chan)) { + dev_warn(dev, "%s: failed to create mailbox client\n", __func__); + crc->cmdq_client.chan =3D NULL; + goto cleanup; + } + + if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc->cmdq_handle, PAGE_SI= ZE)) { + dev_warn(dev, "%s: failed to create cmdq packet\n", __func__); + goto cleanup; + } + + if (!crc->va) { + dev_warn(dev, "%s: no memory\n", __func__); + goto cleanup; + } + + /* map the entry to get a dma address for cmdq to store the crc */ + crc->pa =3D dma_map_single(crc->cmdq_client.chan->mbox->dev, + crc->va, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); + + if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc->pa)) { + dev_err(dev, "%s: failed to map dma\n", __func__); + goto cleanup; + } + + if (crc->cmdq_event) + cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true); + + for (i =3D 0; i < crc->cnt; i++) { + /* put crc to spr1 register */ + cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg->subsys, + crc->cmdq_reg->offset + crc->ofs[i], + CMDQ_THR_SPR_IDX1); + + /* copy spr1 register to physical address of the crc */ + cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_HIGH(crc->pa + i * sizeof(*crc->va))); + cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(crc->pa + i * sizeof(*crc->va)), + CMDQ_THR_SPR_IDX1); + } + /* reset crc */ + mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* clear reset bit */ + mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* jump to head of the cmdq packet */ + cmdq_pkt_jump(&crc->cmdq_handle, crc->cmdq_handle.pa_base); + + return; +cleanup: + mtk_drm_crc_destroy(crc); +} + +void mtk_drm_crc_cmdq_start(struct mtk_drm_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + dma_sync_single_for_device(crc->cmdq_client.chan->mbox->dev, + crc->cmdq_handle.pa_base, + crc->cmdq_handle.cmd_buf_size, + DMA_TO_DEVICE); + mbox_send_message(crc->cmdq_client.chan, &crc->cmdq_handle); + mbox_client_txdone(crc->cmdq_client.chan, 0); +} + +void mtk_drm_crc_cmdq_stop(struct mtk_drm_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + mbox_flush(crc->cmdq_client.chan, 2000); +} +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.h index 3c224595fa714..0683ec4bc26f6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -15,6 +15,45 @@ #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 =20 +/** + * struct mtk_drm_crc - crc related information + * @ofs: register offset of crc + * @rst_ofs: register offset of crc reset + * @rst_msk: register mask of crc reset + * @cnt: count of crc + * @va: pointer to the start of crc array + * @pa: physical address of the crc for gce to access + * @cmdq_event: the event to trigger the cmdq + * @cmdq_reg: address of the register that cmdq is going to access + * @cmdq_client: handler to control cmdq (mbox channel, thread ...etc.) + * @cmdq_handle: cmdq packet to store the commands + */ +struct mtk_drm_crc { + const u32 *ofs; + u32 rst_ofs; + u32 rst_msk; + size_t cnt; + u32 *va; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + dma_addr_t pa; + u32 cmdq_event; + struct cmdq_client_reg *cmdq_reg; + struct cmdq_client cmdq_client; + struct cmdq_pkt cmdq_handle; +#endif +}; + +void mtk_drm_crc_init(struct mtk_drm_crc *crc, + const u32 *crc_offset_table, size_t crc_count, + u32 reset_offset, u32 reset_mask); +void mtk_drm_crc_read(struct mtk_drm_crc *crc, void __iomem *reg); +void mtk_drm_crc_destroy(struct mtk_drm_crc *crc); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +void mtk_drm_crc_cmdq_create(struct device *dev, struct mtk_drm_crc *crc); +void mtk_drm_crc_cmdq_start(struct mtk_drm_crc *crc); +void mtk_drm_crc_cmdq_stop(struct mtk_drm_crc *crc); +#endif + void mtk_drm_crtc_commit(struct drm_crtc *crtc); int mtk_drm_crtc_create(struct drm_device *drm_dev, const unsigned int *path, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 215b7234ff13c..231017470607e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -87,6 +87,9 @@ struct mtk_ddp_comp_funcs { void (*remove)(struct device *dev, struct mtk_mutex *mutex); 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Thu, 15 Feb 2024 18:11:24 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:23 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 11/13] drm/mediatek: Support CRC in OVL Date: Thu, 15 Feb 2024 18:11:17 +0800 Message-ID: <20240215101119.12629-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We choose OVL as the CRC generator from other hardware components that are also capable of calculating CRCs, since its frame done event triggers vblanks, it can be used as a signal to know when is safe to retrieve CRC of the frame. Please note that position of the hardware component that is chosen as CRC generator in the display path is significant. For example, while OVL is the first module in VDOSYS0, its CRC won't be affected by the modules after it, which means effects applied by PQ, Gamma, Dither or any other components after OVL won't be calculated in CRC generation. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 197 +++++++++++++++++++- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 + 3 files changed, 193 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index cd5ca5359b0f0..7ef8dbb07c2db 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -104,6 +104,9 @@ void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); +size_t mtk_ovl_crc_cnt(struct device *dev); +u32 *mtk_ovl_crc_entry(struct device *dev); +void mtk_ovl_crc_read(struct device *dev); =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 98c989fddcc08..cf35783ad4b02 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -25,12 +25,20 @@ #define OVL_FME_CPL_INT BIT(1) #define DISP_REG_OVL_INTSTA 0x0008 #define DISP_REG_OVL_EN 0x000c +#define OVL_EN BIT(0) +#define OVL_OP_8BIT_MODE BIT(4) +#define OVL_HG_FOVL_CK_ON BIT(8) +#define OVL_HF_FOVL_CK_ON BIT(10) +#define DISP_REG_OVL_TRIG 0x0010 +#define OVL_CRC_EN BIT(8) +#define OVL_CRC_CLR BIT(9) #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 #define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define OVL_LAYER_AFBC_EN(n) BIT(4+n) +#define OVL_OUTPUT_CLAMP BIT(26) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) @@ -43,7 +51,26 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CRC 0x0270 +#define OVL_CRC_OUT_MASK GENMASK(30, 0) #define DISP_REG_OVL_CLRFMT_EXT 0x02D0 +#define DISP_REG_OVL_CLRFMT_EXT1 0x02D8 +#define OVL_CLRFMT_EXT1_CSC_EN(n) (1 << (((n) * 4) + 1)) +#define DISP_REG_OVL_Y2R_PARA_R0(n) (0x0134 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_RMY (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_G0(n) (0x013c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_GMU (GENMASK(30, 16)) +#define DISP_REG_OVL_Y2R_PARA_B1(n) (0x0148 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_BMV (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_0(n) (0x014c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_YA (GENMASK(10, 0)) +#define OVL_Y2R_PARA_C_CF_UA (GENMASK(26, 16)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_1(n) (0x0150 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_VA (GENMASK(10, 0)) +#define DISP_REG_OVL_Y2R_PRE_ADD2(n) (0x0154 + 0x28 * (n)) +#define DISP_REG_OVL_R2R_R0(n) (0x0500 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_G1(n) (0x0510 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_B2(n) (0x0520 + 0x40 * (n)) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -56,6 +83,8 @@ #define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) #define OVL_CON_RGB_SWAP BIT(25) +#define OVL_CON_MTX_AUTO_DIS BIT(26) +#define OVL_CON_MTX_EN BIT(27) #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) @@ -63,6 +92,7 @@ #define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT= _MAN) +#define OVL_CON_MTX_PROGRAMMABLE (8 << 16) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -130,6 +160,10 @@ static const u32 mt8195_formats[] =3D { DRM_FORMAT_YUYV, }; =20 +static const u32 mt8195_ovl_crc_ofs[] =3D { + DISP_REG_OVL_CRC, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -140,12 +174,15 @@ struct mtk_disp_ovl_data { const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; + const u32 *crc_ofs; + size_t crc_cnt; }; =20 /* * struct mtk_disp_ovl - DISP_OVL driver structure * @crtc: associated crtc to report vblank events to * @data: platform data + * @crc: crc related information */ struct mtk_disp_ovl { struct drm_crtc *crtc; @@ -155,8 +192,30 @@ struct mtk_disp_ovl { const struct mtk_disp_ovl_data *data; void (*vblank_cb)(void *data); void *vblank_cb_data; + struct mtk_drm_crc crc; }; =20 +size_t mtk_ovl_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->crc.cnt; +} + +u32 *mtk_ovl_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->crc.va; +} + +void mtk_ovl_crc_read(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + mtk_drm_crc_read(&ovl->crc, ovl->regs); +} + static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv =3D dev_id; @@ -236,21 +295,40 @@ void mtk_ovl_clk_disable(struct device *dev) void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); =20 - if (ovl->data->smi_id_en) { - unsigned int reg; + if (ovl->data->smi_id_en) + reg |=3D OVL_LAYER_SMI_ID_EN; =20 - reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); - reg =3D reg | OVL_LAYER_SMI_ID_EN; - writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + /* + * When doing Y2R conversion, it's common to get an output + * that is larger than 10 bits (negative numbers). + * Enable this bit to clamp the output to 10 bits per channel + * (should always be enabled) + */ + reg |=3D OVL_OUTPUT_CLAMP; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + + reg =3D OVL_EN; + if (ovl->data->crc_cnt) { + /* enable crc and its related clocks */ + writel_relaxed(OVL_CRC_EN, ovl->regs + DISP_REG_OVL_TRIG); + reg |=3D OVL_OP_8BIT_MODE | OVL_HG_FOVL_CK_ON | OVL_HF_FOVL_CK_ON; } - writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_EN); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_start(&ovl->crc); +#endif } =20 void mtk_ovl_stop(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); =20 +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_stop(&ovl->crc); +#endif writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); if (ovl->data->smi_id_en) { unsigned int reg; @@ -485,6 +563,83 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, (state->base.fb && !state->base.fb->format->has_alpha)) ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 + /* + * OVL only supports 8 bits data in CRC calculation, transform 10-bit + * RGB to 8-bit RGB by leveraging the ability of the Y2R (YUV-to-RGB) + * hardware to multiply coefficients, although there is nothing to do + * with the YUV format. + */ + if (ovl->data->supports_clrfmt_ext) { + u32 y2r_coef =3D 0, y2r_offset =3D 0, r2r_coef =3D 0, csc_en =3D 0; + + if (is_10bit_rgb(fmt)) { + con |=3D OVL_CON_MTX_AUTO_DIS | OVL_CON_MTX_EN | OVL_CON_MTX_PROGRAMMAB= LE; + + /* + * Y2R coefficient setting + * bit 13 is 2^1, bit 12 is 2^0, bit 11 is 2^-1, + * bit 10 is 2^-2 =3D 0.25 + */ + y2r_coef =3D BIT(10); + + /* -1 in 10bit */ + y2r_offset =3D GENMASK(10, 0) - 1; + + /* + * R2R coefficient setting + * bit 19 is 2^1, bit 18 is 2^0, bit 17 is 2^-1, + * bit 20 is 2^2 =3D 4 + */ + r2r_coef =3D BIT(20); + + /* CSC_EN is for R2R */ + csc_en =3D OVL_CLRFMT_EXT1_CSC_EN(idx); + + /* + * 1. YUV input data - 1 and shift right for 2 bits to remove it + * [R'] [0.25 0 0] [Y in - 1] + * [G'] =3D [ 0 0.25 0] * [U in - 1] + * [B'] [ 0 0 0.25] [V in - 1] + * + * 2. shift left for 2 bit letting the last 2 bits become 0 + * [R out] [ 4 0 0] [R'] + * [G out] =3D [ 0 4 0] * [G'] + * [B out] [ 0 0 4] [B'] + */ + } + + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_R0(idx), + OVL_Y2R_PARA_C_CF_RMY); + mtk_ddp_write_mask(cmdq_pkt, (y2r_coef << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_G0(idx), + OVL_Y2R_PARA_C_CF_GMU); + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_B1(idx), + OVL_Y2R_PARA_C_CF_BMV); + + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_YA); + mtk_ddp_write_mask(cmdq_pkt, (y2r_offset << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_UA); + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_1(idx), + OVL_Y2R_PARA_C_CF_VA); + + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_R0(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_G1(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_B2(idx)); + + mtk_ddp_write_mask(cmdq_pkt, csc_en, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT1, + OVL_CLRFMT_EXT1_CSC_EN(idx)); + } + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; addr +=3D (pending->height - 1) * pending->pitch; @@ -591,15 +746,31 @@ static int mtk_disp_ovl_probe(struct platform_device = *pdev) dev_err(dev, "failed to ioremap ovl\n"); return PTR_ERR(priv->regs); } + + priv->data =3D of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + if (priv->data->crc_cnt) { + mtk_drm_crc_init(&priv->crc, + priv->data->crc_ofs, priv->data->crc_cnt, + DISP_REG_OVL_TRIG, OVL_CRC_CLR); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret =3D cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); -#endif - - priv->data =3D of_device_get_match_data(dev); - platform_set_drvdata(pdev, priv); =20 + if (priv->data->crc_cnt) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", 0, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg =3D &priv->cmdq_reg; + mtk_drm_crc_cmdq_create(dev, &priv->crc); + } +#endif ret =3D devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, IRQF_TRIGGER_NONE, dev_name(dev), priv); if (ret < 0) { @@ -620,6 +791,10 @@ static int mtk_disp_ovl_probe(struct platform_device *= pdev) =20 static void mtk_disp_ovl_remove(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + mtk_drm_crc_destroy(&ovl->crc); component_del(&pdev->dev, &mtk_disp_ovl_component_ops); pm_runtime_disable(&pdev->dev); } @@ -690,6 +865,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .formats =3D mt8195_formats, .num_formats =3D ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext =3D true, + .crc_ofs =3D mt8195_ovl_crc_ofs, + .crc_cnt =3D ARRAY_SIZE(mt8195_ovl_crc_ofs), }; =20 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index b47be6955d9b8..ea04b2769ae8b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -349,6 +349,9 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .clk_enable =3D mtk_ovl_clk_enable, .clk_disable =3D mtk_ovl_clk_disable, .config =3D mtk_ovl_config, + .crc_cnt =3D mtk_ovl_crc_cnt, + .crc_entry =3D mtk_ovl_crc_entry, + .crc_read =3D mtk_ovl_crc_read, .start =3D mtk_ovl_start, .stop =3D mtk_ovl_stop, .register_vblank_cb =3D mtk_ovl_register_vblank_cb, --=20 2.18.0 From nobody Thu Nov 14 04:52:45 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7888F69D1E for ; Thu, 15 Feb 2024 10:11:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 12/13] drm/mediatek: Support CRC in OVL adaptor Date: Thu, 15 Feb 2024 18:11:18 +0800 Message-ID: <20240215101119.12629-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We choose Mixer as CRC generator in OVL adaptor since its frame done event will trigger vblanks, we can know when is safe to retrieve CRC of the frame. In OVL adaptor, there's no image procession after Mixer, unlike the OVL in VDOSYS0, Mixer's CRC will include all the effects that are applied to the frame. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 21 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 62 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 5 ++ 5 files changed, 94 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 7ef8dbb07c2db..7ff4a5f8d7926 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -138,6 +138,9 @@ const u32 *mtk_ovl_adaptor_get_formats(struct device *d= ev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, const struct drm_display_mode *mode); +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev); +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev); +void mtk_ovl_adaptor_crc_read(struct device *dev); =20 void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 68a20312ac6f1..61a8cf9b686ab 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -206,6 +206,27 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, = unsigned int idx, mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); } =20 +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0= ]); +} + +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHD= R0]); +} + +void mtk_ovl_adaptor_crc_read(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index ea04b2769ae8b..43368eb342e2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -404,6 +404,9 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .clk_enable =3D mtk_ovl_adaptor_clk_enable, .clk_disable =3D mtk_ovl_adaptor_clk_disable, .config =3D mtk_ovl_adaptor_config, + .crc_cnt =3D mtk_ovl_adaptor_crc_cnt, + .crc_entry =3D mtk_ovl_adaptor_crc_entry, + .crc_read =3D mtk_ovl_adaptor_crc_read, .start =3D mtk_ovl_adaptor_start, .stop =3D mtk_ovl_adaptor_stop, .layer_nr =3D mtk_ovl_adaptor_layer_nr, diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index e95331c068151..30eb2c3d95c0b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -24,6 +24,9 @@ #define MIX_FME_CPL_INTEN BIT(1) #define MIX_INTSTA 0x8 #define MIX_EN 0xc +#define MIX_TRIG 0x10 +#define MIX_TRIG_CRC_EN BIT(8) +#define MIX_TRIG_CRC_RST BIT(9) #define MIX_RST 0x14 #define MIX_ROI_SIZE 0x18 #define MIX_DATAPATH_CON 0x1c @@ -39,6 +42,11 @@ #define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) + +/* CRC register offsets for odd and even lines */ +#define MIX_CRC_ODD 0x110 +#define MIX_CRC_EVEN 0x114 + #define MIX_FUNC_DCM0 0x120 #define MIX_FUNC_DCM1 0x124 #define MIX_FUNC_DCM_ENABLE 0xffffffff @@ -82,6 +90,7 @@ struct mtk_ethdr { void *vblank_cb_data; int irq; struct reset_control *reset_ctl; + struct mtk_drm_crc crc; }; =20 static const char * const ethdr_clk_str[] =3D { @@ -100,6 +109,32 @@ static const char * const ethdr_clk_str[] =3D { "vdo_be_async", }; =20 +static const u32 ethdr_crc_ofs[] =3D { + MIX_CRC_ODD, + MIX_CRC_EVEN, +}; + +size_t mtk_ethdr_crc_cnt(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + return priv->crc.cnt; +} + +u32 *mtk_ethdr_crc_entry(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + return priv->crc.va; +} + +void mtk_ethdr_crc_read(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + mtk_drm_crc_read(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs); +} + void mtk_ethdr_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *), void *vblank_cb_data) @@ -256,6 +291,13 @@ void mtk_ethdr_start(struct device *dev) struct mtk_ethdr_comp *mixer =3D &priv->ethdr_comp[ETHDR_MIXER]; =20 writel(1, mixer->regs + MIX_EN); + + if (priv->crc.cnt) { + writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_start(&priv->crc); +#endif + } } =20 void mtk_ethdr_stop(struct device *dev) @@ -263,6 +305,9 @@ void mtk_ethdr_stop(struct device *dev) struct mtk_ethdr *priv =3D dev_get_drvdata(dev); struct mtk_ethdr_comp *mixer =3D &priv->ethdr_comp[ETHDR_MIXER]; =20 +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_stop(&priv->crc); +#endif writel(0, mixer->regs + MIX_EN); writel(1, mixer->regs + MIX_RST); reset_control_reset(priv->reset_ctl); @@ -317,6 +362,10 @@ static int mtk_ethdr_probe(struct platform_device *pde= v) if (!priv) return -ENOMEM; =20 + mtk_drm_crc_init(&priv->crc, + ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs), + MIX_TRIG, MIX_TRIG_CRC_RST); + for (i =3D 0; i < ETHDR_ID_MAX; i++) { priv->ethdr_comp[i].dev =3D dev; priv->ethdr_comp[i].regs =3D of_iomap(dev->of_node, i); @@ -325,6 +374,16 @@ static int mtk_ethdr_probe(struct platform_device *pde= v) &priv->ethdr_comp[i].cmdq_base, i); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + + if (i =3D=3D ETHDR_MIXER) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", i, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg =3D &priv->ethdr_comp[i].cmdq_base; + mtk_drm_crc_cmdq_create(dev, &priv->crc); + } #endif dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i); } @@ -365,6 +424,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) =20 static int mtk_ethdr_remove(struct platform_device *pdev) { + struct mtk_ethdr *priv =3D dev_get_drvdata(&pdev->dev); + + mtk_drm_crc_destroy(&priv->crc); component_del(&pdev->dev, &mtk_ethdr_component_ops); return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediate= k/mtk_ethdr.h index 81af9edea3f74..d17d7256bd120 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -22,4 +22,9 @@ void mtk_ethdr_register_vblank_cb(struct device *dev, void mtk_ethdr_unregister_vblank_cb(struct device *dev); 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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 13/13] drm/mediatek: Add comments for the structures Date: Thu, 15 Feb 2024 18:11:19 +0800 Message-ID: <20240215101119.12629-14-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.975300-8.000000 X-TMASE-MatchedRID: Gep7kObvpEO4pD9RIlWSGmNW0DAjL5p+Wot5Z16+u76OUV82NDH4AnB4 4IkzjfYyThbvLLI8RvMwZQM0AWPWgNwrRLDk2cbi9Jn/ZrGuc8EK3iJpXUOQQ/NhzIgXtFJVPMA rurUD4iIZuRDUp90meSglNnWlJnT+XZXnjooQdcj/VoEOchXiKfngX/aL8PCNUE1mmrDSX3/ZGr fobCG633WrcTrQpH0eKmWOtem/9LIspGg/D8oKmYdlc1JaOB1TXru95hSuhjRaW2Ktn+I8/jEGF jeZwyRUnbrivw+lJ4g/Z/74EQY5HV+bIMgmNlCEq0j38LygEqSHqtBkN6Eg9o3V8N0KgLoaLikh fBJEpmlIbT6B+f046SEX93Xmp5MMIg67HHizFeGXZ9FWlXKjpGYoy6wSP7IF33Nl3elSfso57kF jOTI5JcAWmWwzJ75gJeq6/Pd92m7MHUInqqZ02o9hRjNfZeOXMVx/3ZYby7/FJnEpmt9OE+aX92 YgSYLB6u/xkAmsI959Vk7adRpFX0CbGlypKMBDjc2CQSoA3RH25PfmnPqD743xexyACqYgo8WMk QWv6iXBcIE78YqRWo6HM5rqDwqtJzhY1fP3Cl+1sj10naDFSiTlA/5e44yH/1zXNPJNdJ+Cc4gt Ze+DZw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.975300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 590B25C83335607A233B4FE573EE9F7EC9BDA74535F899966DD674CB5D6EFD4B2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add comments for the structures to improve readability. Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 22 ++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 32 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 +++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 +++++++ 5 files changed, 99 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index cf35783ad4b02..b92c5c3c590a0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -164,6 +164,20 @@ static const u32 mt8195_ovl_crc_ofs[] =3D { DISP_REG_OVL_CRC, }; =20 +/** + * struct mtk_disp_ovl_data - ovl driver data + * @addr: offset of the first layer (layer-0) + * @gmc_bits: gmc (gating memory clock) bit masks for adjusting positivity= for ovl + * @layer_nr: layer numbers that ovl supports + * @fmt_rgb565_is_0: whether or not rgb565 is represented as 0 + * @smi_id_en: determine if smi needs to be enabled + * @supports_afbc: determine if ovl supports afbc + * @formats: format table that ovl supports + * @num_formats: number of formats that ovl supports + * @supports_clrfmt_ext: whether the ovl supports clear format (for alpha = blend) + * @crc_ofs: crc offset table + * @crc_cnt: count of crc registers (could be more than one bank) + */ struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -178,10 +192,15 @@ struct mtk_disp_ovl_data { size_t crc_cnt; }; =20 -/* +/** * struct mtk_disp_ovl - DISP_OVL driver structure * @crtc: associated crtc to report vblank events to + * @clk: clock of the ovl + * @regs: base address of the ovl register that can be accessed by cpu + * @cmdq_reg: register related info for cmdq (subsys, offset ...etc.) * @data: platform data + * @vblank_cb: callback function when vblank irq happened + * @vblank_cb_data: data to the callback function * @crc: crc related information */ struct mtk_disp_ovl { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index 6cb1ed419dee7..b4f7b3d3bbeb6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -28,14 +28,30 @@ * struct mtk_drm_crtc - MediaTek specific crtc structure. * @base: crtc object. * @enabled: records whether crtc_enable succeeded + * @pending_needs_vblank: determine if we need to handle vblank event + * @event: the vblank event to handle * @planes: array of 4 drm_plane structures, one for each overlay plane + * @layer_nr: layer numbers that the crtc supports * @pending_planes: whether any plane has pending changes to be applied + * @pending_async_planes: if there is any pending async update + * @cmdq_client: a handler to control cmdq (mbox channel, thread ...etc.) + * @cmdq_handle: cmdq packet to store the commands + * @cmdq_event: cmdq event that the thread is waiting for + * @cmdq_vblank_cnt: vblank count that is dedicated for the cmdq thread + * @cb_blocking_queue: wait queue to determine if cmdq is blocked * @mmsys_dev: pointer to the mmsys device for configuration registers + * @dma_dev: pointer to the dma device (usually rdma) * @mutex: handle to one of the ten disp_mutex streams - * @ddp_comp_nr: number of components in ddp_comp + * @ddp_comp_nr_ori: number of the components excludes the route (origin) + * @max_ddp_comp_nr: maximum number of the components in routes + * @ddp_comp_nr: number of the components in the current path * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this c= rtc - * - * TODO: Needs update: this header is missing a bunch of member descriptio= ns. + * @conn_route_nr: number of the components in route + * @conn_routes: route to the connector + * @hw_lock: mutex lock to avoid race condition when layer config + * @config_updating: determine if the layer configuration is done + * @crc_provider: get crc provider of the crtc + * @frames: count the frames that are added to crc entry */ struct mtk_drm_crtc { struct drm_crtc base; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 231017470607e..dcf8466b8f857 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -48,6 +48,38 @@ enum mtk_ddp_comp_type { =20 struct mtk_ddp_comp; struct cmdq_pkt; + +/* struct mtk_ddp_comp_funcs - function pointers of the ddp components + * @clk_enable: enable the clocks of the component + * @clk_disable: disable the clocks of the component + * @config: configure the component + * @start: start (enable) the component + * @stop: stop (disable) the component + * @register_vblank_cb: to register a callback function when vblank irq oc= curs + * @unregister_vblank_cb: to unregister the callback function from the vbl= ank irq + * @enable_vblank: enable vblank irq + * @disable_vblank: disable vblank irq + * @supported_rotations: return rotation capability of the component + * @layer_nr: how many layers the component supports + * @layer_check: to check if the state of the layer is valid for the compo= nent + * @layer_config: to configure the component according to the state of the= layer + * @gamma_set: to set gamma for the component + * @bgclr_in_on: turn on background color + * @bgclr_in_off: turn off background color + * @ctm_set: set color transformation matrix + * @dma_dev_get: return the device that uses direct memory access + * @get_formats: get the format that is currently in use by the component + * @get_num_formats: get number of the formats that the component supports + * @connect: connect the sub modules of the component + * @disconnect: disconnect the sub modules of the component + * @add: add the device to the component (mount them in the mutex) + * @remove: remove the device from the component (unmount them from the mu= tex) + * @encoder_index: get the encoder index of the component + * @crc: return the start of crc array + * @crc_cnt: how many CRCs the component supports + * @crc_entry: get the pointer to the crc entry + * @crc_read: call this function to read crc from the hardware component + */ struct mtk_ddp_comp_funcs { int (*power_on)(struct device *dev); void (*power_off)(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 414764b4546ba..8ee1f36a6c2b8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -33,6 +33,23 @@ struct mtk_drm_route { const unsigned int route_ddp; }; =20 +/** + * struct mtk_mmsys_driver_data - capabilities for the mmsys + * @main_path: path of the main display + * @main_len: length of the main display path + * @ext_path: path of the external display + * @ext_len: length of the external display path + * @third_path: path of the third display + * @third_len: length of the third display path + * @conn_routes: routing table of all the possible connectors + * @conn_routes_num: number of the routing table for the connectors + * @shadow_register: whether or not shadow register is enabled + * @mmsys_id: multi-media system ID + * @mmsys_dev_num: number of devices for in the mmsys as a whole + * @max_pitch: maximum pitch in bytes that the mmsys supports + * @min_width: minimum fb pixel width on this device + * @min_height: minimum fb pixel height on this device + */ struct mtk_mmsys_driver_data { const unsigned int *main_path; unsigned int main_len; diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 30eb2c3d95c0b..eae72deacfd2c 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -82,6 +82,17 @@ struct mtk_ethdr_comp { struct cmdq_client_reg cmdq_base; }; =20 +/** + * struct mtk_ethdr - ethdr driver data + * @ethdr_comp: components of ethdr(mixer) + * @ethdr_clk: clocks of ethdr components + * @mmsys_dev: mmsys device that ethdr binds to + * @vblank_cb: callback function when vblank irq occurs + * @vblank_cb_data: data fo vblank callback + * @irq: irq that triggers irq handler + * @reset_ctl: reset control of ethdr + * @crc: crc information + */ struct mtk_ethdr { struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX]; struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM]; --=20 2.18.0