From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 141F5175B1; Thu, 15 Feb 2024 08:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987347; cv=none; b=R5pLgHqK25JoZAm98i0QDso0kNfzNWmY0oB+MMO/c3iYEUNhTU5K5OOsa9IxSRiLvTzGhicH+RDoxN0GNP9qQ5H3aux7mBwviI4nv+HeccC1MwDE/YUTa4GRGcAP83ThJpPaq/X9FjjU2twpTeuM7iPvU8LKOHN+tz8J5ucYtqQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987347; c=relaxed/simple; bh=4htfbBS51jnreuB8iFhcsTcQXTRQPWShEDKrBb5JIzk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PFBiDH7dbyuqAtoGJ7pU1dB8Ft6Zb4DcwPiAsXHWaL1mHde92jcyFR+2afkKG7lOFVsmTJUfM+j0FNHS2Qcq8/E6nJVreHh+vKdWLH52WUClGqEnNvE7ZyK4i5oM1Qg2BEgsUyFKT2q0jn7ubaK9tTQsidpMWkWS12/7q0amUxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nLukmeL/; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nLukmeL/" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tSin090471; Thu, 15 Feb 2024 02:55:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987328; bh=KDgekC80YFSLo7k3ZuMZRvrm6iESaFQD1d3E5cj0jHI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nLukmeL/01MsyXQUMtm2KYjL1i6Pv2DSOyRRnUDW8Q3m3yageYtvRf4KFaTtYTdot v9TjH0ZC3OqbyHEKI3e0xsjgjFzSsCc+sP4kcHHvLg/O7/McxRQIKvBUIFiQ8GWFGC qswtx1SY7HYuPxggsDaTmyD5CmjSBH6JKF++xjYs= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tSXF069376 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:28 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:27 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:27 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7k008333; Thu, 15 Feb 2024 02:55:24 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:10 +0530 Message-ID: <20240215085518.552692-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 361365bb5523..5631735c9b7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MC= ASP2_AXR1.I2C3_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status =3D "okay"; --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 141C31759D; Thu, 15 Feb 2024 08:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987346; cv=none; b=bvgyEzaNqPklwuw0JaH7G/bbuVVru0x+E8xy6VqobbeelYWBAv7wRo6eTl4V6FnsevLnqMBa9ICw6SP5WJ3WnfWMVy3++aRTiPY3/nM5b5UEpBZ6D9V5Qg92K8PBAGwMHxC8HX5xgpBZiTL073wj40hrzw0GKg+4vdgjAGMSOio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987346; c=relaxed/simple; bh=XDtMgDz3rfnkmExmQ6PmozYP7ACi/TpQ0LAtAzowkpE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HXHIBj85tOEQQq9wd8ahV6uBiA5XPu9DC7qREVpHL7qoM/BNzV00Xnd78KXCy4g7wjNnOKddpMzKKpnMCYHXd6e6AQgFVeZMOgWzRHf0g4EMV/xI26NTSniXqO8bj5vZ/34aYQYDzhWEHTzBXaubJxRaSyykt6f/fOQuXEFvoNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=gFYYWw2k; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gFYYWw2k" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tW3I090489; Thu, 15 Feb 2024 02:55:32 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987332; bh=x/k1nR+0Oofrre15QvBy2e7fuQCsoXlHJGCKKMdrXLU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gFYYWw2khhv091RLpAu8nLxJQbolvlGgzi8Agr6mlTPGGt8Cv+TMuwd7kJiKHZ16s pgG+MBZyNNrNbVqmHOHCPP2NKu1S2u354Givzoyl8ozqIdcqjr+TotwhAAnlWkGis0 mfGz3DLQeoOBDzedk9msZfAszBmfJrp0AqbSEvDM= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tW5P059488 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:32 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:31 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:31 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7l008333; Thu, 15 Feb 2024 02:55:28 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:11 +0530 Message-ID: <20240215085518.552692-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 57e7cb8ea2b8..bb2558b68381 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -297,6 +297,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -761,6 +768,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC56418AE0; Thu, 15 Feb 2024 08:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987351; cv=none; b=tW+VO0ypz0uRvv+rnhJEQJA5uoNsP3hNdXmB/0Eu11X97jZQ+dG6eg8rBDapxnDk0w2x0hmTZuSSIHol2K0HSXvyCy7QSLDCfxGDKfW1gCBVn3m1STqyEgJpYKVmBQFiIDTxZoexKSqQod4JPI9DwTPKY3L8VK6yREje2156i0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987351; c=relaxed/simple; bh=aZC43jcmh1e3Ips3tqM5BiR8qN4/wtdGcRR6NcsziYk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jRLd1mfnggr+9sYFMVpkXM0bgT4wGh1xVon5vJiot2xSPQbThSwZXE5stHPJsdAY2iUjuJPYTgAKKb1KziCxO25b6+DOeuEnb1CLH4i6KcMxO7gMNef3WNaP7Rbe2xkSbntJVxEWh1hdZI8aMEMFwHbK8kmtBkma48fdoA4CrAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=e+Hsyz3z; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="e+Hsyz3z" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tamg090498; Thu, 15 Feb 2024 02:55:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987336; bh=qA03AiPQ76ODZlkdfgCJ4bbvmcQFxo0DGUcdzk429lc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=e+Hsyz3z8eKzad6dllpoHFvUyttxh3l3ftgylBfnEHadfKDf6GupgxKJ9tKN3Uznx vj9RwKUZg1kxoj0iTIfOQ8jMaz0i6CXJsNMHwJA+/uaghvR0WDSJJf8KBYdaKHCWVk AStsuHhlrRaR+5SZV5LmGniB8/8aViCSauh5//CE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tamJ059589 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:36 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:35 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:36 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7m008333; Thu, 15 Feb 2024 02:55:32 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:12 +0530 Message-ID: <20240215085518.552692-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index f48155dd16a3..d743f023cdd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; }; =20 &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + status =3D "okay"; + + exp3: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_i2c4 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CB8617BA7; Thu, 15 Feb 2024 08:55:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987349; cv=none; b=gj56u51qEPg7nvVgvVuL9dXpuuNPwHooiTY2dCNz8SEbvjYrnM6q8icgZzf6Lc2i2up420tHsuO4G0tzWarH//1ghb1CYF2OxeKIlVmnL11ZYlvGPvv69v0scCe9vtWnJofTWG9GerbfuDh5Ur5EDSrS/8D6tr+nFtXb8xUvS8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987349; c=relaxed/simple; bh=KC2c1YczNYz0dqqBXE+kxiEBxIAtI4xTHfr1LBwVRKs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=McH45ZI8mlBiBZqSPD6gc8jKRb7dK3eGqE77MaRHa8anlePqA/W8JWmzh6QlyI8pzO34y3XktqJLO2NVyHgVEMDyTORjHctel/9Tjoziy99boUHukWQA7JLy21wPo34C8kiJE1C/1aBt3cdvmdBg4gjK845MHxVeCkYKPjFfY34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Ar/c+M6e; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ar/c+M6e" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8teon090518; Thu, 15 Feb 2024 02:55:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987340; bh=5f06S+zYcwCeq2tvXJVvkkRoi5yjPpWJZR1EyBYAnic=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ar/c+M6eDPK0g2XxckEmAojlja85ulb4yU2eHpEICfhHmDBA9UbxVV9HEqhkx5kPV whZoldPQvwqMKZORklikSrhNcqven6MBD7d6OSBd8iABSMC98c1QDB6nKoqvpKIf1k y5AfEcKHPx+gd6PW1vfu1ogH09lZCXKvcQ4/KlKo= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8teK3005008 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:40 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:40 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:40 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7n008333; Thu, 15 Feb 2024 02:55:36 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:13 +0530 Message-ID: <20240215085518.552692-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 5f0a43a69333..46cf90bb3eb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -322,6 +322,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; + }; =20 &main_pmx0 { @@ -341,6 +349,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_S= CL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SD= A */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -775,6 +790,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp2: gpio@21 { + compatible =3D "ti,tca6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B261B966; Thu, 15 Feb 2024 08:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987354; cv=none; b=YLO+3E+ZTmoNAzqmxofv763r3PigGQUhjTBskZViHmH6YNNQ7TtZ309LF+2C5cA+c/y7jkpuAKKoLKF3xpLoe3SZN4YQ38gjhdVyvJqd2MnU4Xgcvm5GRPEIfiyLjstk6dm9gurqDarJDXa9Vls9wzNjEGtMV5A4padu0KSo1/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987354; c=relaxed/simple; bh=9R3RlAEkv5tEnvMbUFpbKdtp8NCsxDjpOTdVVZNIGXg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qHO6YRbob+Jccjx+WKSJ7gYXFr9hhLlDUNjm13PkcOsgPdaH7FpVYNy0PIm2H6jW1esLkwe+OfVHowqzeo+KVqGO+qULDSKhEraN49BLFI3PuKXZ4u0y9yjnAe2q/P0s4JbE2SpsQswcMKPVuh6YZnIAE6+uI08YrUFk6N66rnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=df8q64KX; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="df8q64KX" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tiF7069239; Thu, 15 Feb 2024 02:55:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987344; bh=WftwmOV6VJghVZe5M9HH30MtAUbPXmvOMWm7w3lYE+c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=df8q64KXHgMSy360SY5t+N7EFLDv1JnhhnGPXCuA3xqKGnX1JbI/8jd0U+dunlkNX 7gZ0tONmDq7/wohkoHiA0udJO8lEReS1cO7QVV9wSEHri/wmWwythqNB5/qCSil0p6 quko885R6YvS0JMUkYAN8gG99QWy9bh0CmMiku1w= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tidM005058 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:44 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:44 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:44 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7o008333; Thu, 15 Feb 2024 02:55:40 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Thu, 15 Feb 2024 14:25:14 +0530 Message-ID: <20240215085518.552692-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 6950b1ff124f..5dbc85bc5038 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_csi_mux_sel_pins_default>; + }; }; =20 &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB= 1_DRVVBUS */ >; }; =20 + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins =3D < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg =3D <0x70>; =20 /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0>; }; =20 /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5588D1BC3A; Thu, 15 Feb 2024 08:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987358; cv=none; b=nf8Z6F8D3d2iGlXGRy+WSyVLEH4VkPTglt2vnqW0KPANW5XN1+bSuTPU9rUDfkhmKuL3ATa21PHBhUBJcjreNvLJovjfoD9NkXaeOs/WxKyUjiN5ZY4wVlZ92HmAuvdmlNbBpHVD4+1Liwzfl7oOx8svaM07+SV0KM4887pUw5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987358; c=relaxed/simple; bh=2LuzAj83T0Ukw1lY+n18b5eU1N5KKNiKZLnAXjo+tUw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q1DQdJ1T3Zc9pblO3stSEtdztKru/bxtWJ7tA+IVf3hUTV3fOkkci4e+GwQ4wCs6bKjVV/bPoUm87yZy738ijr25bb4XIQJn01hR+exfCJZxylx45MEtOfWavxtlbThXc4UrGYVdMj1T+tz332S8DuNObngF28BvQ/d8knHVpd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=rlxAKeC8; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rlxAKeC8" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tmvc069361; Thu, 15 Feb 2024 02:55:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987348; bh=hle8B4wOVmCnu+NYK66b75xWUwcEbuBSDmVLCNAJScI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rlxAKeC85VYJe8tY7WGT23mD307aoEbJXP84Rl3Cf+yAsMO948nvpgd8jupgujbb1 D8rHaOXcKLTGHKQwimNxZ9+MXKPZ9xDR4o1DoRnBtxOZX9VdkS+C+YLveINmtt72jh 5PhHX5jD6BlVW+kA/77p7rwOk/vMGSZnL4qCBI1A= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tmtn059755 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:48 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:48 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:48 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7p008333; Thu, 15 Feb 2024 02:55:44 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:15 +0530 Message-ID: <20240215085518.552692-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 062a6fca5a31..841752d20de1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask =3D <0x0000001f>; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_udmap 0x4940>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4504000 0x0 0x1000>; + clocks =3D <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_udmap 0x4960>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4514000 0x0 0x1000>; + clocks =3D <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4580000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4590000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible =3D "ti,j721e-wiz-16g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A521BDE0; Thu, 15 Feb 2024 08:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987366; cv=none; b=uGTZW4CukfDAuJSbHLK+hvRiIog/k8Pyseovrd3oI3fq+MpPc9La5gbIiqcWUhj4Lc2b/KsRM9MXw7Qt3crLTQ8wme92iS834EvcfzUQD4X/B1XTwHBcZsfbfEqEWBagbZ31xDgcu6ac76qL74oZALBIDy860NlKwRwCv2dLEUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987366; c=relaxed/simple; bh=wNv4a6Md8eOgqP+Ve8O8gkO4YdqeO12NW2BZ0s1DMMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CzlCN0WrIUNScJ6iMloDjAiV/yn3f7zRNYqJvDy+fQGdJJ2M5bxcTchRXvvg491O+tEiySmOx/CgmbXacLDM13x3UGZwwXvvokYeccrfABLO5QLmCZNlNvNqaB/ilJm+cEaka7QXhqOwYV34N7Wc+VapODA2VIDzrijx3H05POQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wRPnb62B; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wRPnb62B" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8trCe076934; Thu, 15 Feb 2024 02:55:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987353; bh=qS7ma5QtwgNFRPziAmeuyTE5bj091f6X4+AXhzup8IM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wRPnb62Bj+cgrYp+FMtjlc0/MvwHru+8BwgdKn/NAKfv04EOrc41bAqwkYlxR59mp zvd3NJya3KmyNqD1I0RxcRRqagKnte2hJxuHec/K8jGWsZ7xXcwOZoWYmhWysHdbRw UyfiPWa8Razxv5R5iwa7oyDPpoVqsKTbsDjxNVMY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tr6K060027 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:53 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:52 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7q008333; Thu, 15 Feb 2024 02:55:48 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:16 +0530 Message-ID: <20240215085518.552692-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index dcaa4da0d678..9063aa609993 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <225>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x1000>; + clocks =3D <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x1000>; + clocks =3D <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible =3D "ti,j721s2-wiz-10g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8E891BDE1; Thu, 15 Feb 2024 08:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987367; cv=none; b=LvdejX4Wofm+lwRSSjG1JIJziMrwbOA/WrUgXFVMQlm8LRYkiNS/MiNNCJFu00tW1RGoXjVpR50K6i7LXTyp02Lw+CBd80FhUSQjwU51guAC6WXfkGcue+Q9G17kgqxneKRcNaEZ5UgKU72stX1YH1xzQxpA6kdQJTzaiDqg0VY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987367; c=relaxed/simple; bh=4pPR5YA7SPsk9ZPhh/9gcPJX/rPyLNRGggwMs/0rGgc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U2RrsD3xd9OphK9ECX075gIPgQcf0JwX4XgUR8lzHLvra6crbOdUa/Ol2ALYm50tcncZivRZoarG3paKsE2wX/aofjAfvyA60z3ow2u+m0vwSskHiLJcaZv6CLKYZcusfHaJETE2j3ODAWu0KsGlvv7ZpgHPPqcnkaV7lZpqsUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=q+BTr4pH; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="q+BTr4pH" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tvFU069376; Thu, 15 Feb 2024 02:55:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987357; bh=XjJHu3kpCQ6vIKijB7J4jG4GPq+oMP0RA/oDCOyUjhM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q+BTr4pHWJiiv/qXTtmmfVqzkCiFs1g15vTm2SZIb4zYHlRSP6b2FvXIwReVTGzZk dZlVyZ15fcMxWlwWqcz8JEl5ARyFo7+f8cD6LSmCaq6v1gC081gj2D8LFPREFlfQlD O+OiFq6HWhmtlkyDpvuMnWK3E43Jz1FFD/MsASTY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8tvPn060153 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:55:57 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:55:57 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:55:57 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7r008333; Thu, 15 Feb 2024 02:55:53 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:17 +0530 Message-ID: <20240215085518.552692-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 3cb964982792..42e4ca1d0b65 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status =3D "disabled"; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x00001000>; + clocks =3D <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x00001000>; + clocks =3D <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x4980 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04524000 0x00 0x00001000>; + clocks =3D <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy2>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi2_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi2_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi2_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi2_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy2: phy@45a0000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible =3D "ti,j721e-sdhci-8bit"; reg =3D <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <281>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { --=20 2.34.1 From nobody Wed Dec 24 03:33:13 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4AAF1C2BD; Thu, 15 Feb 2024 08:56:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987374; cv=none; b=tXGF6Hp4woe5uIhQdVGrOOW2BJGKVP3wQLILG0W/aZDeMa6EpbewVexCrZYGlzZrtSNYvsiBLudWQcwNf3cZLOH4tEHfbX7OA01pDpvV+dDL3oJP1CUEvLwszHSC/bev6ZTQxyz4odDYX7W3N2cvtMpZJxJ+Jtq/vhF1g3Ry6lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707987374; c=relaxed/simple; bh=gpqQRRDPQBPXaAkoedqV4bTe9pjWXhRY3M39Q7k4e+A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EBTxgqon+LQ6j97E75Ph17+Mqypc2xQX8O1pnv36F+lgy5V8GlTSXoubY6+pj5uISnz6/adIwsSroNI8NiC/nUYs0aqlKKMepj7aTyga4jwjgq/hw+PmpBOC881ocAsK1L25cICdC0ftzAWVNw7NtCLY2i9HG53H4ZTphFwfgtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=cSHQDJLD; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cSHQDJLD" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41F8u1QX090559; Thu, 15 Feb 2024 02:56:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707987361; bh=QGK+gjRP4X2BkVV/ukKldEjKRwEktFPDzNaOM4M1prU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cSHQDJLDGzMu5RLPHtu29ckpAYBdoBesDGzdkGvFBrOM++pgOdy3Beb4dLKG/jxCV EI61FmgJfRqvJ6GCpLXUdHBtSqeGrnCQo9zsaILY6yB+hb3DK8yiiEyfMTSKr6VIYO v+CzLbuDWBtpZz83fDhJuqvZPECe76dww3287iA4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41F8u1ep005368 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Feb 2024 02:56:01 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Feb 2024 02:56:01 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Feb 2024 02:56:01 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7s008333; Thu, 15 Feb 2024 02:55:57 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 9/9] arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 Date: Thu, 15 Feb 2024 14:25:18 +0530 Message-ID: <20240215085518.552692-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V3->V4: * Add additional port information in overlays to fix DTC warning: Warning (graph_child_address): graph node has single child node, #address-cells/#size-cells are not necessary=20 V1->V2: * Rename overlays to indicate first platform (j721e-sk) supported and dual camera. * Add missed build test, fix missing newline. arch/arm64/boot/dts/ti/Makefile | 13 ++ .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 165 ++++++++++++++++++ 2 files changed, 178 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 4a570dffb638..e019efd3ce94 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219.dtbo =20 # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb @@ -106,8 +107,14 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am68-sk-base-board-csi2-dual-imx219-dtbs :=3D k3-am68-sk-base-board.dtb= \ + k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-csi2-dual-imx219-dtbs :=3D k3-am69-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -122,7 +129,10 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ + k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb =20 # Enable support for device-tree overlays @@ -132,5 +142,8 @@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-am68-sk-base-board +=3D -@ +DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ +DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arc= h/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 000000000000..47bb5480b5b0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; + +&csi_mux { + idle-state =3D <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_0: imx219-0@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_1: imx219-1@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; --=20 2.34.1