From nobody Mon Feb 9 02:51:19 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9731182DF for ; Thu, 15 Feb 2024 09:20:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988840; cv=none; b=XncwCxPcDivnmhzHG3NziIlwVm3u81b4tcDYiDRASgqik4C/CXaKRs/QOXaxU7b76SQABlzyLXeT8mqWf+H9LqAuqWS+3oxCDKoNc+vCN+uvZr1jA6cJKBWbwVWoIBJmANeR1gbpse7u9a34mY7TtS1T8ldkf3vpWKE7FnIuy40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988840; c=relaxed/simple; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iqzjlN32FAI+iQI/D0OA/tF4HN7NZJLv7Bx+85B+bN91X8fdGzO8gzHRg+zvDI4sT16duPTc9zyAtmmm84mMRi1JxjQsUXMqgDl9z9figKKf/QLAYrI4v4NurCvoa/uv7lz+Bimkm9eyZDItTSC7j20d1n13S3Cdpt5h/WRuIXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W6h4hsPC; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W6h4hsPC" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4121a8635a2so2310025e9.3 for ; Thu, 15 Feb 2024 01:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988837; x=1708593637; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=W6h4hsPC+DkUixiozRIH8dQFAJb5uUI9XGrcpsH5V1Hvo4HZoBjDtFdJLGtT+N/1i2 ALm96oM5grXu2jYJvEG9OQ8/QNwTNDbQyQepn2fTp5CEcOxHCzyGVooC6t7cCUQVEmlb I2EB3cd6D1GIdVl29uDDEW8/n2JrcqbgflZsaiQCXr+5J2V6vHnbTa6hwPQb6BpdAu/T yHg3rkVBEIQzvjk/qJWEHWePDpJQyhvxpL9jAxa31mIJV7+whs99oXjZzE9GBvPxiK8P kDY/SF6wZ/jZG67zU3uYo7iP6/Cd1TXVjpDLeNVpacltWidpv+g/KF1i+US8WGbrVG63 xnSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988837; x=1708593637; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=rlNmFVr+3AXNw6S7YahGLuDlm0hvaU4f4EoLNjeZHwMObrBwliQHnrmtJITM+XEuqz Z/iJ4eoDVHm1cNYu6IBVdBzV1vA2zY+PGW+HVoTcailNs+m8BO7LepFyqICjqizUL6zf ORUkJdpIHE7/L2q43HaYN3W9kLNUvRxOkKT1/oGvAU+RJGSWk2wVJG/oMaSqwxClhqqp y0EvQoQvKxbW7GOhtJHpVo/qfvBPmekRgXl9fgJe4C44aKojBwFcfsU5T2e7jsJpYGK7 ckNsIGWd1vzouD4/RwE0R6lfDCBIiNDMvErZbRD+U8qnOPJoW3zPcCE0mZN1Pv6Qq3DN P/tw== X-Forwarded-Encrypted: i=1; AJvYcCWWDPt593owcfCwHV/XMp/svJbprywnuLFtgbGBdChaHwaRBhrWaT2ONXJSXhbhBwZNopjqEb0PRUS/luM+Fm8e4oxi2wUNlUpW5oyW X-Gm-Message-State: AOJu0YxASYDYpQNxaxvaqiVIV2e8nv7R8Jz1jAaFLgHTw0rAyy755Goq V1C6iONpV8h5SMPU+Nn0UoMMvpvB1GVIOLu/lvTIgR92HFMSlWPsN9+HkS/6gFg= X-Google-Smtp-Source: AGHT+IGrvfbJ1uUDMa21ZnoJEdi5tRVea1OtDbDqHW32HWnjFevw0x1eHUUlkCjL4h415agx3thpXA== X-Received: by 2002:a5d:5751:0:b0:33b:3cb0:3081 with SMTP id q17-20020a5d5751000000b0033b3cb03081mr995363wrw.6.1707988837100; Thu, 15 Feb 2024 01:20:37 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:36 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:27 +0100 Subject: [PATCH v2 5/6] arm64: dts: qcom: sm8650: add GPU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240215-topic-sm8650-gpu-v2-5-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5727; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddcRfimUONnmrWNCX250+syb3LF/WRnexivnTqi rWBuVceJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XXAAKCRB33NvayMhJ0Z6nD/ 9fbuMf2jo4kFuN4Na5g4SaGhBo9f5t7RS2YyuolvNgbmiOCWUxBT2WnpRWGLXxfed+y2oP7H4byB0T 9xy7Yb+566tShTaC9KwLQfkZcVS+86cXGQwocurs7RX9mJPuvnp8B6C0kEGcG7WcFC0CzPijpHwzo0 uvosOjOze6t+bxceWJXwCp01m7aZWVdbSVXFORderPanxV8VYSUI3FJByB2Meb5XjvoBJDQM/E43hE ZcQYcCimF1FVVgn0B+/vrQ6QGB6UJ1McO3Gp1UjM0iz+Wd5v1GjIng3k/lmiRVUULg8aMqbhRIGk6L uT6021tW0ixDYZGfOxr4UnoveSCRlTbmVk/sc2vFj1NBJHygWxSX6VggeEoUmIeOge95mwAxd4zzXq 0n9GX+7HArdNA4ud4AtphXsicXhLoGncRtd9hw/47IZmrT54tI0cqycl9KRjGl5SuUMdoNLp4zt10y UAoDcWClAcfzGd0ajfZYXXdIQb3I1wam5Ao5A4YBgQD6WYL4Jvn5TPQ/V3kWp/jvwyRN4gevsstM8v vkKoq3wyVxvmyBXxulhkHS/Os7qd0/6R04JE8Uj8dQb8nA+lC/sIaqLVg1Yn8Y4jCg5i7ay32cDSMA WFhAmjzAuYwbvGXjQEoIILRaZGUC9M7BhCsGo6jCR8m0QCN253r8w8sEjfnw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-43051401", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts =3D ; + + iommus =3D <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 =3D <&gpu_opp_table>; + + qcom,gmu =3D <&gmu>; + + status =3D "disabled"; + + zap-shader { + memory-region =3D <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-680000000 { + opp-hz =3D /bits/ 64 <680000000>; + opp-level =3D ; + }; + + opp-629000000 { + opp-hz =3D /bits/ 64 <629000000>; + opp-level =3D ; + }; + + opp-578000000 { + opp-hz =3D /bits/ 64 <578000000>; + opp-level =3D ; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + + opp-422000000 { + opp-hz =3D /bits/ 64 <422000000>; + opp-level =3D ; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + opp-level =3D ; + }; + + opp-310000000 { + opp-hz =3D /bits/ 64 <310000000>; + opp-level =3D ; + }; + + opp-231000000 { + opp-hz =3D /bits/ 64 <231000000>; + opp-level =3D ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names =3D "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + iommus =3D <&adreno_smmu 5 0x0>; + + qcom,qmp =3D <&aoss_qmp>; + + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-625000000 { + opp-hz =3D /bits/ 64 <625000000>; + opp-level =3D ; + }; + + opp-260000000 { + opp-hz =3D /bits/ 64 <260000000>; + opp-level =3D ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,sm8650-gpucc"; reg =3D <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells =3D <1>; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names =3D "hlos", + "bus", + "iface", + "ahb"; + power-domains =3D <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible =3D "qcom,sm8650-ipa", "qcom,sm8550-ipa"; =20 --=20 2.34.1