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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id ca23-20020a170906a3d700b00a3caccb8f66sm1980163ejb.44.2024.02.13.22.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 22:13:17 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Daniel Lezcano , Thomas Gleixner , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Krzysztof Kozlowski Subject: [PATCH V4 2/3] dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock Date: Wed, 14 Feb 2024 07:12:32 +0100 Message-Id: <20240214061233.24645-3-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240214061233.24645-1-zajec5@gmail.com> References: <20240214061233.24645-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Dropped "syscon" as it was incorrectly used 3. Adjusted nodename, "compatible" and "reg" in example Signed-off-by: Rafa=C5=82 Mi=C5=82ecki Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../arm/mediatek/mediatek,pciesys.txt | 25 ----------- .../clock/mediatek,mt7622-pciesys.yaml | 45 +++++++++++++++++++ 2 files changed, 45 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,pciesys.txt create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7622= -pciesys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesy= s.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt deleted file mode 100644 index d179a61536f4..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek PCIESYS controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -The MediaTek PCIESYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-pciesys", "syscon" - - "mediatek,mt7629-pciesys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The PCIESYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -pciesys: pciesys@1a100800 { - compatible =3D "mediatek,mt7622-pciesys", "syscon"; - reg =3D <0 0x1a100800 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesy= s.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.ya= ml new file mode 100644 index 000000000000..c77111d10f90 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIESYS clock and reset controller + +description: + The MediaTek PCIESYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + enum: + - mediatek,mt7622-pciesys + - mediatek,mt7629-pciesys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*= -clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a100800 { + compatible =3D "mediatek,mt7622-pciesys"; + reg =3D <0x1a100800 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.35.3