From nobody Sun Feb 8 14:10:36 2026 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DAED6215D for ; Tue, 13 Feb 2024 22:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707863971; cv=none; b=U06lp7a1wQAcfNxldjZk5S98XkCnSlcvAa9jbLgC23fHMpJFgTdbheWp/ZadcJ+jA+ub3Sk19DhR6QufC7xA8KWp7Ml72n9At5CNCMXWvzTQfT/MSQEw7JnrF7ATAE20yi5wbHqFrd8r2jHtHSUfbFUIdgj8MHDRdosOQu8jO2A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707863971; c=relaxed/simple; bh=+mPsQFxDyv4xoZGkFnZUtpvg7QmtVFk4n4nJyEwpkmo=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=qedC6VBBssU5bKAfdM+VPnl5TWg/MHjP97ebxUd5CAyLKtVB9JiwH6dIz+DzITJpoHWd2fy3qCHzwYcrYRxReSQEWawTWxf+Alg/V9+b0zDmJVnCo/wOyMcxqrkmQgaSMDgXzC94o1b/WLSU8b+OOTrrJF8N7K8dWab24kFhJcE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--ericchancf.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=rUAdsbKX; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--ericchancf.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="rUAdsbKX" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-dccc49ef73eso1489048276.2 for ; Tue, 13 Feb 2024 14:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707863969; x=1708468769; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=rUAdsbKXLZRpY9xdVPalRKYiAmqYyyN9uacDwmGWKmLQGNPES71HYbjbvLkdo0I+l2 m1UXE3KM2qx2ybn1IHZhfiieOOJF1amwq1FzLpWI0H+XC2zghD3hyhlK58uRKKRxiUs8 hw1d0v7VhlLB/713stWkRRsdQgCHD0BDlnlF4L1AmVnUTgyjyYRkyw2Pmamfu3PerlLD sYN9cbXElfgUEuyWXAgd2zwSlZYx6iDh9wtgE2gnRWPdxs95PUywUvLatb3rra19c7LH sVB9++gyd0q3wcEvB72o6SDvOt678IIFzvYLFreZRuNNBPjjTJduJQChafZZzahIZwlO gIfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707863969; x=1708468769; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=lUX379CwOhkSOSVZBkSm1LTQsG4HzXTAAceH7tG+Ttu26HRw8wXR2UZG1MdbpJUB6f TaVm/LF5BZVGbX2YL2lEWmINMiYQRjlTIUkQ8cF1kWtr6xKHSFEn2mB52RLUPZgdwJXa QzAMk6EF4Ym+Qf1uBdbbdIoQcqKB3EOMBEg95PWT0KeVDNQMutoRjyJ6xGjCPvuCCcMT UMGPan+Bs8CiSymqDJD/hCFvSVNPRLb8uycMUJQufHvLsZ8IUcQ3q1BPbEx9lOCgqw+o OCEfuk7Lo7+iCE4P2UBvKJbHaHULW/EI1JupH1UDmgnSjQW4x8++gacrgUhEsLTOtLya I3Mw== X-Forwarded-Encrypted: i=1; AJvYcCU3YBYH/Yk63hF5gSGD201vn/XiNCJijE1OCILxqFRzjVwmzG9+TKdZAeI8Qu/lE9T3rVXxISj/MKVC6UaAN9hQa83mLdsjhc5tAi05 X-Gm-Message-State: AOJu0Yz64WNy2DSF0WcxHV+HdOuVff6rCStynqrBoMMdcP9B0QBX09lz wk6VB4T/xvLL58jvONspHpvp6twlDiBN3B0GUkTywF/nxNFGPWGIn2POU0CRlTexE0XoM1iaMuX IdGLMJuV+GlE5WyjmuA== X-Google-Smtp-Source: AGHT+IEIi+wYTmQJyxcKODqt/e4zjlJ+9u4VEaVmzXIRBnTsS/drWHfQ9rn0ZFxxYlAcorE8rSRQo+ev1twJewgu X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1027:b0:dc6:dd76:34cc with SMTP id x7-20020a056902102700b00dc6dd7634ccmr45468ybt.1.1707863969224; Tue, 13 Feb 2024 14:39:29 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:23 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223923.2597036-1-ericchancf@google.com> Subject: [PATCH v5 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomi= c.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless= (atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unle= ss(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_nega= tive(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_posi= tive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(= atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_ne= gative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_po= sitive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positiv= e(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif =20 #endif /* _ASM_RISCV_FENCE_H */ --=20 2.43.0.687.g38aa6559b0-goog