From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EFFD627E9 for ; Tue, 13 Feb 2024 21:05:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858339; cv=none; b=Vj0rHRFCiVv7o9kkGDaBAT/csu1dH8ZCET0SJUlQwEXTPsTXNNize/irBtPyAb/u6R0v+sFvVCR64C6Ogg6w9Nezf15JuIaAqzcZsMuA3KkjBzuBS2Xy/1Qr2jT/AMR0nE/4W0GAzP3GNlDlJpB3i6jEZjMy9IYr2yC2GxyY5WA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858339; c=relaxed/simple; bh=WWNdNmpp30no7bggG3A5bq2RFzUx1lR4502O9QeYXug=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ueSxwy980HfIV2vm9DfO8m7ZBuwVTIRInJM7hHra8ehvKpbwuclFjfLAcJZCYrOhslCQ2K2oryzoMjCUH+oe6ps6Zo8Y4vsUBbU/F7gjCaJr4vhSw8B30XyVSwVJXSfRYwmV97h72b5B2qb0FJZfY/6YgNfHRFZ81Ad9l/tSqIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cTju2dmk; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=I+qTAjla; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cTju2dmk"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="I+qTAjla" Message-ID: <20240213210251.543948812@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BEi9L5Qul8R2TWefVL07Inw18MPYGX4wh2IRJRnS66Q=; b=cTju2dmkf7cErodEfKHanlKbi+YpT0izgdl4s5nNxXdQ5PvF2tN5Lahv18RJXa9mXQYpNF QXSL3jzrKjSaMNFUMEqdgpSZwh8Kpq+xGLfz1+/r6fURdaFI0oCfdEFf/3SaydgE5DLqKc g94lzKx9RvushZJuPyT4g6k3UpEldNvr4WfCZdILaZzSa0ZPOPnXBVaDuNrECWf/BW//Y8 TTG5EC5rHV5St9BxwkcHSRRdbc5riVbz1RhuvwH9t7661iJ7583IGqZD5X0BkZk9Oa5Vva oP3T072VeorCceXq8BGeFFmG+V+IQpgta75xIBbNYprGyTzVLznMwH3udnwubg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BEi9L5Qul8R2TWefVL07Inw18MPYGX4wh2IRJRnS66Q=; b=I+qTAjlapHvSy24e4D3hPtXtrcB2fvrO6u6QjOkPSQfb6ZwK9ulKeZALFdkwbX19nVm90S zlqUCnDRtVtRjBBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 01/30] x86/cpu/topology: Move registration out of APIC code References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:35 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The APIC/CPU registration sits in the middle of the APIC code. In fact this is a topology evaluation function and has nothing to do with the inner workings of the local APIC. Move it out into a file which reflects what this is about. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 2=20 arch/x86/kernel/apic/apic.c | 185 ------------------------------------= ----- arch/x86/kernel/cpu/Makefile | 12 +- arch/x86/kernel/cpu/topology.c | 184 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 195 insertions(+), 188 deletions(-) create mode 100644 arch/x86/kernel/cpu/topology.c --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -171,6 +171,8 @@ extern bool apic_needs_pit(void); =20 extern void apic_send_IPI_allbutself(unsigned int vector); =20 +extern void topology_register_boot_apic(u32 apic_id); + #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } #define local_apic_timer_c2_ok 1 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -68,26 +68,12 @@ =20 #include "local.h" =20 -unsigned int num_processors; - -unsigned disabled_cpus; - /* Processor that is doing the boot up */ u32 boot_cpu_physical_apicid __ro_after_init =3D BAD_APICID; EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); =20 u8 boot_cpu_apic_version __ro_after_init; =20 -/* Bitmap of physically present CPUs. */ -DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); - -/* - * Processor to be disabled specified by kernel parameter - * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to - * avoid undefined behaviour caused by sending INIT from AP to BSP. - */ -static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; - /* * This variable controls which CPUs receive external NMIs. By default, * external NMIs are delivered only to the BSP. @@ -107,14 +93,6 @@ static inline bool apic_accessible(void) return x2apic_mode || apic_mmio_base; } =20 -/* - * Map cpu index to physical APIC ID - */ -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); - #ifdef CONFIG_X86_32 /* Local APIC was disabled by the BIOS and enabled by the kernel */ static int enabled_via_apicbase __ro_after_init; @@ -1676,8 +1654,6 @@ void apic_ap_setup(void) end_local_APIC_setup(); } =20 -static __init void cpu_set_boot_apic(void); - static __init void apic_read_boot_cpu_id(bool x2apic) { /* @@ -1692,7 +1668,8 @@ static __init void apic_read_boot_cpu_id boot_cpu_physical_apicid =3D read_apic_id(); boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } - cpu_set_boot_apic(); + topology_register_boot_apic(boot_cpu_physical_apicid); + x86_32_probe_bigsmp_early(); } =20 #ifdef CONFIG_X86_X2APIC @@ -2291,155 +2268,6 @@ void disconnect_bsp_APIC(int virt_wire_s apic_write(APIC_LVT1, value); } =20 -/* - * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated - * contiguously, it equals to current allocated max logical CPU ID plus 1. - * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, - * so the maximum of nr_logical_cpuids is nr_cpu_ids. - * - * NOTE: Reserve 0 for BSP. - */ -static int nr_logical_cpuids =3D 1; - -/* - * Used to store mapping between logical CPU IDs and APIC IDs. - */ -u32 cpuid_to_apicid[] =3D { [0 ... NR_CPUS - 1] =3D BAD_APICID, }; - -bool arch_match_cpu_phys_id(int cpu, u64 phys_id) -{ - return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; -} - -#ifdef CONFIG_SMP -static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) -{ - /* Isolate the SMT bit(s) in the APICID and check for 0 */ - u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; - - if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) - cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); -} - -/* - * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid - * during early boot. Initialize the primary thread mask before SMP - * bringup. - */ -static int __init smp_init_primary_thread_mask(void) -{ - unsigned int cpu; - - /* - * XEN/PV provides either none or useless topology information. - * Pretend that all vCPUs are primary threads. - */ - if (xen_pv_domain()) { - cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); - return 0; - } - - for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) - cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); - return 0; -} -early_initcall(smp_init_primary_thread_mask); -#else -static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } -#endif - -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(int apicid) -{ - int i; - - /* - * cpuid <-> apicid mapping is persistent, so when a cpu is up, - * check if the kernel has allocated a cpuid for it. - */ - for (i =3D 0; i < nr_logical_cpuids; i++) { - if (cpuid_to_apicid[i] =3D=3D apicid) - return i; - } - - /* Allocate a new cpuid. */ - if (nr_logical_cpuids >=3D nr_cpu_ids) { - WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " - "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apicid); - return -EINVAL; - } - - cpuid_to_apicid[nr_logical_cpuids] =3D apicid; - return nr_logical_cpuids++; -} - -static void cpu_update_apic(int cpu, u32 apicid) -{ -#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; -#endif - set_cpu_possible(cpu, true); - set_bit(apicid, phys_cpu_present_map); - set_cpu_present(cpu, true); - num_processors++; - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apicid); -} - -static __init void cpu_set_boot_apic(void) -{ - cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; - cpu_update_apic(0, boot_cpu_physical_apicid); - x86_32_probe_bigsmp_early(); -} - -int generic_processor_info(int apicid) -{ - int cpu, max =3D nr_cpu_ids; - - /* The boot CPU must be set before MADT/MPTABLE parsing happens */ - if (cpuid_to_apicid[0] =3D=3D BAD_APICID) - panic("Boot CPU APIC not registered yet\n"); - - if (apicid =3D=3D boot_cpu_physical_apicid) - return 0; - - if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -EINVAL; - } - - cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - - cpu_update_apic(cpu, apicid); - return cpu; -} - - void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { @@ -2828,15 +2656,6 @@ static int __init lapic_insert_resource( */ late_initcall(lapic_insert_resource); =20 -static int __init apic_set_disabled_cpu_apicid(char *arg) -{ - if (!arg || !get_option(&arg, &disabled_cpu_apicid)) - return -EINVAL; - - return 0; -} -early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); - static int __init apic_set_extnmi(char *arg) { if (!arg) --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -26,14 +26,16 @@ obj-y +=3D bugs.o obj-y +=3D aperfmperf.o obj-y +=3D cpuid-deps.o obj-y +=3D umwait.o +obj-y +=3D capflags.o powerflags.o =20 -obj-$(CONFIG_PROC_FS) +=3D proc.o -obj-y +=3D capflags.o powerflags.o +obj-$(CONFIG_X86_LOCAL_APIC) +=3D topology.o =20 -obj-$(CONFIG_IA32_FEAT_CTL) +=3D feat_ctl.o +obj-$(CONFIG_PROC_FS) +=3D proc.o + +obj-$(CONFIG_IA32_FEAT_CTL) +=3D feat_ctl.o ifdef CONFIG_CPU_SUP_INTEL -obj-y +=3D intel.o intel_pconfig.o tsx.o -obj-$(CONFIG_PM) +=3D intel_epb.o +obj-y +=3D intel.o intel_pconfig.o tsx.o +obj-$(CONFIG_PM) +=3D intel_epb.o endif obj-$(CONFIG_CPU_SUP_AMD) +=3D amd.o obj-$(CONFIG_CPU_SUP_HYGON) +=3D hygon.o --- /dev/null +++ b/arch/x86/kernel/cpu/topology.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +#include + +#include +#include +#include + +/* + * Map cpu index to physical APIC ID + */ +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); +EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); +EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); + +/* Bitmap of physically present CPUs. */ +DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC) __read_mostly; + +/* Used for CPU number allocation and parallel CPU bringup */ +u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; + +/* + * Processor to be disabled specified by kernel parameter + * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to + * avoid undefined behaviour caused by sending INIT from AP to BSP. + */ +static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; + +unsigned int num_processors; +unsigned disabled_cpus; + +/* + * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated + * contiguously, it equals to current allocated max logical CPU ID plus 1. + * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, + * so the maximum of nr_logical_cpuids is nr_cpu_ids. + * + * NOTE: Reserve 0 for BSP. + */ +static int nr_logical_cpuids =3D 1; + +bool arch_match_cpu_phys_id(int cpu, u64 phys_id) +{ + return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; +} + +#ifdef CONFIG_SMP +static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) +{ + /* Isolate the SMT bit(s) in the APICID and check for 0 */ + u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; + + if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) + cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); +} + +/* + * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid + * during early boot. Initialize the primary thread mask before SMP + * bringup. + */ +static int __init smp_init_primary_thread_mask(void) +{ + unsigned int cpu; + + /* + * XEN/PV provides either none or useless topology information. + * Pretend that all vCPUs are primary threads. + */ + if (xen_pv_domain()) { + cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); + return 0; + } + + for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) + cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); + return 0; +} +early_initcall(smp_init_primary_thread_mask); +#else +static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } +#endif + +/* + * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds + * and cpuid_to_apicid[] synchronized. + */ +static int allocate_logical_cpuid(int apicid) +{ + int i; + + /* + * cpuid <-> apicid mapping is persistent, so when a cpu is up, + * check if the kernel has allocated a cpuid for it. + */ + for (i =3D 0; i < nr_logical_cpuids; i++) { + if (cpuid_to_apicid[i] =3D=3D apicid) + return i; + } + + /* Allocate a new cpuid. */ + if (nr_logical_cpuids >=3D nr_cpu_ids) { + WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " + "Processor %d/0x%x and the rest are ignored.\n", + nr_cpu_ids, nr_logical_cpuids, apicid); + return -EINVAL; + } + + cpuid_to_apicid[nr_logical_cpuids] =3D apicid; + return nr_logical_cpuids++; +} + +static void cpu_update_apic(int cpu, u32 apicid) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; +#endif + set_cpu_possible(cpu, true); + set_bit(apicid, phys_cpu_present_map); + set_cpu_present(cpu, true); + num_processors++; + + if (system_state !=3D SYSTEM_BOOTING) + cpu_mark_primary_thread(cpu, apicid); +} + +void __init topology_register_boot_apic(u32 apic_id) +{ + cpuid_to_apicid[0] =3D apic_id; + cpu_update_apic(0, apic_id); +} + +int generic_processor_info(int apicid) +{ + int cpu, max =3D nr_cpu_ids; + + /* The boot CPU must be set before MADT/MPTABLE parsing happens */ + if (cpuid_to_apicid[0] =3D=3D BAD_APICID) + panic("Boot CPU APIC not registered yet\n"); + + if (apicid =3D=3D boot_cpu_physical_apicid) + return 0; + + if (disabled_cpu_apicid =3D=3D apicid) { + int thiscpu =3D num_processors + disabled_cpus; + + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); + + disabled_cpus++; + return -ENODEV; + } + + if (num_processors >=3D nr_cpu_ids) { + int thiscpu =3D max + disabled_cpus; + + pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " + "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); + + disabled_cpus++; + return -EINVAL; + } + + cpu =3D allocate_logical_cpuid(apicid); + if (cpu < 0) { + disabled_cpus++; + return -EINVAL; + } + + cpu_update_apic(cpu, apicid); + return cpu; +} + +static int __init apic_set_disabled_cpu_apicid(char *arg) +{ + if (!arg || !get_option(&arg, &disabled_cpu_apicid)) + return -EINVAL; + + return 0; +} +early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D66162807 for ; Tue, 13 Feb 2024 21:05:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858340; cv=none; b=Qm/GOXJH+cr+Es7kI+uPabnTxtyzQkIJKz92tRa2kJb9B157TkILHOe0F7M+aUfsFB+XZG0d/pVxUxiL8P/BizVWYug9nmYV2sDxS6T6L0EQgVIXvXe/XFMlDZpnG69KRetN7/Mv/2xP3eO3EnkH3d1nJ9Kl8DEOkv88pQT3Ysg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858340; c=relaxed/simple; bh=sDs7RvIn02Lmy+oNh0MGYv+YqHG81vDMgrLJBwfgZfM=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=Ex4zTbZeUiAgdBtzAWO0jtVY7oQQF3UuMkNwQV6J44GozJq0BG8FpET5WVovkzU3cVT4EMysFu4+mkjCuqYfnsNf7X2fur/iwt0PYmXAb5JLFbs06L6y7iPLhOMts/LfcFFKMkxs3Kkgge6v7cX/U7+PmmsLTFaqlFRlbedddzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nzSJUvqK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fcZWcQ9I; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nzSJUvqK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fcZWcQ9I" Message-ID: <20240213210251.605007456@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6gy/+SDaPiJlc3v0/1odqe8c5XxnqRbgBVGqNF2CHsE=; b=nzSJUvqK1nGr17J4uXPhroi2mfTEsVVEGeIoveyxQt/07m2A5bFtSMG/9fHkscKD5mO+Lv L7ylETGmPaxdEQDsm6woOZaLXNuSq/4Y44SuBHXFQxqLv6L8++O7l7xTpI4Kj25K+oKH2E UQaG4ko9eeXZbklxAkH4UD4Bfr74BmmlBZ+wWyFsgjL0qRSQIMhNsHnspyW4Ho3pCOnV1f gZdXcww5NX5SoAr6MXUaW2QMABvjtvxzBaifOwmTt4NwUdbFtM3yAUyv1DXEZWdNh+o74s KlDyLWZj/NyYYTN2kEWbuSZcsYC64p+fG4fdGAcqRKrULjni8m0B68sqMZstpA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6gy/+SDaPiJlc3v0/1odqe8c5XxnqRbgBVGqNF2CHsE=; b=fcZWcQ9IlUikvP/7EIH8GsD0hSoy5g8QePXhP1uOrMhNNBPzkyzV4HFod0X4kWQlZD7zvp A2uGaeuUvw7KZ6Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 02/30] x86/cpu/topology: Provide separate APIC registration functions References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:36 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner generic_processor_info() aside of being a complete misnomer is used for both early boot registration and ACPI CPU hotplug. While it's arguable that this can share some code, it results in code which is hard to understand and kept around post init for no real reason. Also the call sites do lots of manual fiddling in topology related variables instead of having proper interfaces for the purpose which handle the topology internals correctly. Provide topology_register_apic(), topology_hotplug_apic() and topology_hotunplug_apic() which have the extra magic of the call sites incorporated and for now are wrappers around generic_processor_info(). Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 3 + arch/x86/kernel/cpu/topology.c | 113 ++++++++++++++++++++++++++++++++++--= ----- 2 files changed, 98 insertions(+), 18 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -171,7 +171,10 @@ extern bool apic_needs_pit(void); =20 extern void apic_send_IPI_allbutself(unsigned int vector); =20 +extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); extern void topology_register_boot_apic(u32 apic_id); +extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); +extern void topology_hotunplug_apic(unsigned int cpu); =20 #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -84,32 +84,38 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(int apicid) +static int topo_lookup_cpuid(u32 apic_id) { int i; =20 - /* - * cpuid <-> apicid mapping is persistent, so when a cpu is up, - * check if the kernel has allocated a cpuid for it. - */ + /* CPU# to APICID mapping is persistent once it is established */ for (i =3D 0; i < nr_logical_cpuids; i++) { - if (cpuid_to_apicid[i] =3D=3D apicid) + if (cpuid_to_apicid[i] =3D=3D apic_id) return i; } + return -ENODEV; +} + +/* + * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds + * and cpuid_to_apicid[] synchronized. + */ +static int allocate_logical_cpuid(u32 apic_id) +{ + int cpu =3D topo_lookup_cpuid(apic_id); + + if (cpu >=3D 0) + return cpu; =20 /* Allocate a new cpuid. */ if (nr_logical_cpuids >=3D nr_cpu_ids) { WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apicid); + nr_cpu_ids, nr_logical_cpuids, apic_id); return -EINVAL; } =20 - cpuid_to_apicid[nr_logical_cpuids] =3D apicid; + cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; return nr_logical_cpuids++; } =20 @@ -127,12 +133,6 @@ static void cpu_update_apic(int cpu, u32 cpu_mark_primary_thread(cpu, apicid); } =20 -void __init topology_register_boot_apic(u32 apic_id) -{ - cpuid_to_apicid[0] =3D apic_id; - cpu_update_apic(0, apic_id); -} - int generic_processor_info(int apicid) { int cpu, max =3D nr_cpu_ids; @@ -174,6 +174,83 @@ int generic_processor_info(int apicid) return cpu; } =20 +/** + * topology_register_apic - Register an APIC in early topology maps + * @apic_id: The APIC ID to set up + * @acpi_id: The ACPI ID associated to the APIC + * @present: True if the corresponding CPU is present + */ +void __init topology_register_apic(u32 apic_id, u32 acpi_id, bool present) +{ + int cpu; + + if (apic_id >=3D MAX_LOCAL_APIC) { + pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); + return; + } + + if (!present) { + disabled_cpus++; + return; + } + + cpu =3D generic_processor_info(apic_id); + if (cpu >=3D 0) + early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; +} + +/** + * topology_register_boot_apic - Register the boot CPU APIC + * @apic_id: The APIC ID to set up + * + * Separate so CPU #0 can be assigned + */ +void __init topology_register_boot_apic(u32 apic_id) +{ + cpuid_to_apicid[0] =3D apic_id; + cpu_update_apic(0, apic_id); +} + +#ifdef CONFIG_ACPI_HOTPLUG_CPU +/** + * topology_hotplug_apic - Handle a physical hotplugged APIC after boot + * @apic_id: The APIC ID to set up + * @acpi_id: The ACPI ID associated to the APIC + */ +int topology_hotplug_apic(u32 apic_id, u32 acpi_id) +{ + int cpu; + + if (apic_id >=3D MAX_LOCAL_APIC) + return -EINVAL; + + cpu =3D topo_lookup_cpuid(apic_id); + if (cpu < 0) { + cpu =3D generic_processor_info(apic_id); + if (cpu >=3D 0) + per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + } + return cpu; +} + +/** + * topology_hotunplug_apic - Remove a physical hotplugged APIC after boot + * @cpu: The CPU number for which the APIC ID is removed + */ +void topology_hotunplug_apic(unsigned int cpu) +{ + u32 apic_id =3D cpuid_to_apicid[cpu]; + + if (apic_id =3D=3D BAD_APICID) + return; + + per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; + clear_bit(apic_id, phys_cpu_present_map); + set_cpu_present(cpu, false); + num_processors--; +} +#endif + static int __init apic_set_disabled_cpu_apicid(char *arg) { if (!arg || !get_option(&arg, &disabled_cpu_apicid)) From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ED8462810 for ; Tue, 13 Feb 2024 21:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858341; cv=none; b=blOOjGTyWJS4ENibPDv5I396yvstWs09BswbD/tqNlrgYEfUkj9olA72niQPgF6Tk3IkzNFtcz/AJkhgi5d7JBcJgfnehul/+HhffnkfVDDQiVGg9JfIH9IlMJw5RtNdCoCgWVLXNVbMmLsZZPmt2hlwq8g5oYZKNZUTG9fSlB0= ARC-Message-Signature: i=1; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 03/30] x86/acpi: Use new APIC registration functions References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:37 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Use the new topology registration functions and make the early boot code path __init. No functional change intended. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/acpi/boot.c | 44 +++++++--------------------------------= ----- 1 file changed, 7 insertions(+), 37 deletions(-) --- --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -164,33 +164,9 @@ static int __init acpi_parse_madt(struct return 0; } =20 -/** - * acpi_register_lapic - register a local apic and generates a logic cpu n= umber - * @id: local apic id to register - * @acpiid: ACPI id to register - * @enabled: this cpu is enabled or not - * - * Returns the logic cpu number which maps to the local apic - */ -static int acpi_register_lapic(int id, u32 acpiid, u8 enabled) +static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) { - int cpu; - - if (id >=3D MAX_LOCAL_APIC) { - pr_info("skipped apicid that is too big\n"); - return -EINVAL; - } - - if (!enabled) { - ++disabled_cpus; - return -EINVAL; - } - - cpu =3D generic_processor_info(id); - if (cpu >=3D 0) - early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpiid; - - return cpu; + topology_register_apic(apic_id, acpi_id, present); } =20 static bool __init acpi_is_processor_usable(u32 lapic_flags) @@ -844,12 +820,10 @@ static int acpi_map_cpu2node(acpi_handle return 0; } =20 -int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 acpi_id, - int *pcpu) +int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 acpi_id, int= *pcpu) { - int cpu; + int cpu =3D topology_hotplug_apic(physid, acpi_id); =20 - cpu =3D acpi_register_lapic(physid, acpi_id, ACPI_MADT_ENABLED); if (cpu < 0) { pr_info("Unable to map lapic to logical cpu number\n"); return cpu; @@ -868,15 +842,11 @@ int acpi_unmap_cpu(int cpu) #ifdef CONFIG_ACPI_NUMA set_apicid_to_node(per_cpu(x86_cpu_to_apicid, cpu), NUMA_NO_NODE); #endif - - per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; - set_cpu_present(cpu, false); - num_processors--; - - return (0); + topology_hotunplug_apic(cpu); + return 0; } EXPORT_SYMBOL(acpi_unmap_cpu); -#endif /* CONFIG_ACPI_HOTPLUG_CPU */ +#endif /* CONFIG_ACPI_HOTPLUG_CPU */ =20 int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base) { From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC56B7A715 for ; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 04/30] x86/jailhouse: Use new APIC registration function References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:39 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No functional change intended. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/jailhouse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -102,7 +102,7 @@ static void __init jailhouse_parse_smp_c register_lapic_address(0xfee00000); =20 for (cpu =3D 0; cpu < setup_data.v1.num_cpus; cpu++) - generic_processor_info(setup_data.v1.cpu_ids[cpu]); + topology_register_apic(setup_data.v1.cpu_ids[cpu], CPU_ACPIID_INVALID, t= rue); =20 smp_found_config =3D 1; From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86E5E6281A for ; Tue, 13 Feb 2024 21:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858345; cv=none; b=HO0arEU2HIzNDpQyYCoZC7imsxFpoEGGLV2hONB6O7jri/o7ZN6RCfoe1AfPvRZrH4B1xHgSF+h+DEKkPFZ6TpXWV4h+9ITJLPAUSK7IqhR2JFYoh/+PJHXcJZHUjryAEZsMWHReXOCuEDUqUYsp5PCLqIGFP00Uk6Zey9uRSeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858345; c=relaxed/simple; bh=H+sFDbIcixHvFwoCWW7yHeVhJ3NEd3vsw/iUdXIypEI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=lzub9jU/Xgi1x6lwK7Qov0klvDsZvrm/KHZnh7D1u+2WMO2Dns4AgpVGPcQPuoqVnYZgwwiCBAhbwpF9aVjCmUikBu46u7WRe60mFn5SaQbzpK4uzZRk3qdM9Fw82yGaVa9mOlX1ObvjYf3XkVD1O/ViaT8c21Ztxd7BwBp61GA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SLxYehef; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1s+/pqMo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SLxYehef"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1s+/pqMo" Message-ID: <20240213210251.776009244@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s6fgiMIEgPG7owWaaV7G3Dyc3ZHmfeJa/L4kuQIYeNY=; b=SLxYehefZ3oWP5c9SW7HtdB6e1H2ETs7uQFvNCqJ47Zzdip/Mk7nJ7QsFLuHEzqWlYtLN5 aKnFOaqWhiJGfpo3ec5JM/d0k7FwKniKT7Nrz83UscojjuNV2QrnG/FarjVg2W72JLGl4L LvR+pdUhGhG3rTzjvYlPoz4/hYD1uSOgPZrevKMr9n4BlC9LYkw4SOoh3roe+ZCTYPNA80 KSiSSHs+CtMhq52TRBhleL7BYDt76enW7Td4OI2S2Fml+AZLJRwWC/nwjeoXJ+p4bgKz7i amhQ+MbMAL5SkcdgzpoCNsqCBPXdTPadskjyKoLiSrQoMLN+8wtz3kADKaraBA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s6fgiMIEgPG7owWaaV7G3Dyc3ZHmfeJa/L4kuQIYeNY=; b=1s+/pqMo3AlYkf+YkEiiQfhZMvo8yhh6aO2HwAJg0GH4T1VoHGl09WdPxJ7Cg4i9C55qbj L0sN4RBo0iQau3Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 05/30] x86/of: Use new APIC registration functions References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:40 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No functional change intended. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/devicetree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -136,7 +136,7 @@ static void __init dtb_cpu_setup(void) pr_warn("%pOF: missing local APIC ID\n", dn); continue; } - generic_processor_info(apic_id); + topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); } } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 026C17C09E for ; Tue, 13 Feb 2024 21:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858345; cv=none; b=bMcaWqVNuV41pt2XWg0if/9CBHoCFm5VorTyRYG9xizvF9JVp005L/TzvDlJlacj15VeomIybp1eZN9ua1OEovHrlYpQh+yqV6gqcMxReOK7vFbVsWI/evgkpU+voHj8miOngx3LpLuFNc90o/lwdMFoWaAFIAdC7QkMACwO2X8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858345; c=relaxed/simple; bh=2f2NQCXjq+Qw8tOS36sojhoEEm2F5eey1xvfWfOcfQA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=jCNC318lNlRCWYc1ROWVRUnoZB0drAB/N35RLtf7JpM3SaeYWa50c/T3IXmyrh5W9edWJ8PNjVwgVHHMYwFWnI+MQrwdQEnuKAjWgYr1qKWmwi93VUGC5+0+43ifdFv0VKryWY4MR48foZ7UtXukwrW5znR/6+ziPe6ZI4EPhK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PmjxtYAv; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=of649M5e; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PmjxtYAv"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="of649M5e" Message-ID: <20240213210251.830955273@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QKxEGyGg+k5hdg4U9ew42w42evdPmIVY0idUHE//9Eo=; b=PmjxtYAv/KDE7FBsI2oGtSa/LXG7fn32Z0EncKnxIjzchDGpDv8SvNcpgg2Dn22KGvvSZY ZY65lMjWRx1CoEwScUSRVRGnTxeCTYbxy0WLxenC7Pwu2fG0CI19GtNA5hWW+XfO/DHBRk WfZny675wTx6m4CL+nMBOdRQSJG0/j+CVuzUsdWX5ZmxTyWLuEKZzivGFu3A5fqEdeSN6c 5iUGY1bS22MFJTNyW1F+IYFSooyfhLummo57bn4q8AnFmVBJznFlN0/XO2XpNCQa/cmX// i4naTJok4iWC24E8zKkL9vritlJfqjFxDUA7oKj0WSzCXgZvpQcRHlPCz77iUw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QKxEGyGg+k5hdg4U9ew42w42evdPmIVY0idUHE//9Eo=; b=of649M5eUBoq4aB75ZUOHpRFlz8D3kS17KTcuLtDTpVBmcyrQs4OHxaw85lThZhXODeuXD oOiwq5eU5mMKJJDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 06/30] x86/mpparse: Use new APIC registration function References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:42 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Aside of switching over to the new interface, record the number of registered CPUs locally, which allows to make num_processors and disabled_cpus confined to the topology code. No functional change intended. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 2 -- arch/x86/kernel/cpu/topology.c | 2 +- arch/x86/kernel/mpparse.c | 17 +++++++++-------- 3 files changed, 10 insertions(+), 11 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -61,8 +61,6 @@ static inline void e820__memblock_alloc_ #define mpparse_parse_smp_config x86_init_noop #endif =20 -int generic_processor_info(int apicid); - extern DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 static inline void reset_phys_cpu_present_map(u32 apicid) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -133,7 +133,7 @@ static void cpu_update_apic(int cpu, u32 cpu_mark_primary_thread(cpu, apicid); } =20 -int generic_processor_info(int apicid) +static int generic_processor_info(int apicid) { int cpu, max =3D nr_cpu_ids; =20 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -36,6 +36,8 @@ * Checksum an MP configuration block. */ =20 +static unsigned int num_procs __initdata; + static int __init mpf_checksum(unsigned char *mp, int len) { int sum =3D 0; @@ -50,16 +52,15 @@ static void __init MP_processor_info(str { char *bootup_cpu =3D ""; =20 - if (!(m->cpuflag & CPU_ENABLED)) { - disabled_cpus++; + topology_register_apic(m->apicid, CPU_ACPIID_INVALID, m->cpuflag & CPU_EN= ABLED); + if (!(m->cpuflag & CPU_ENABLED)) return; - } =20 if (m->cpuflag & CPU_BOOTPROCESSOR) bootup_cpu =3D " (Bootup-CPU)"; =20 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); - generic_processor_info(m->apicid); + num_procs++; } =20 #ifdef CONFIG_X86_IO_APIC @@ -236,9 +237,9 @@ static int __init smp_read_mpc(struct mp } } =20 - if (!num_processors) + if (!num_procs && !acpi_lapic) pr_err("MPTABLE: no processors registered!\n"); - return num_processors; + return num_procs || acpi_lapic; } =20 #ifdef CONFIG_X86_IO_APIC @@ -529,8 +530,8 @@ static __init void mpparse_get_smp_confi } else BUG(); =20 - if (!early) - pr_info("Processors: %d\n", num_processors); + if (!early && !acpi_lapic) + pr_info("Processors: %d\n", num_procs); /* * Only use the first configuration found. */ From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A51097A715 for ; Tue, 13 Feb 2024 21:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858348; cv=none; b=IOjEUPXk5A10LWJ0u71SpVHXdYm0mhwnvdQdBR7/RO18RxoJgXCNbuW9aavcsuPd+9MiuQRc1ueDldzos3tOvmGW32t1yRpaSf1kop7VQIQeHdMKZQZk8sTKIqS+3hKJ5lyO3TuVubyxL36ebOFlDVp+7IUB+41V7KaolB5BpoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858348; c=relaxed/simple; bh=mSWHUsAxY2vmF0UO1GwGRNnmjm20vOkVOPe+MQZCqus=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=dJU7EijMsP+AHsITCE5QVNrLlHGPxe8prZjNhYvG35K66eY/62A9Krr+45hZBSpgcz6lDTKUSyeatb+B09hYb9yXCId0DNRPVAuC25wWVmdJrKrXdQEYhMdDoexd5Q2OnGCS9gHs4kE341RXDqjHAC/pcF+BzqyqWvVeVFTHLEI= ARC-Authentication-Results: i=1; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 07/30] x86/acpi: Dont invoke topology_register_apic() for XEN PV References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:43 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The MADT table for XEN/PV dom0 is not really useful and registering the APICs is momentarily a pointless exercise because XENPV does not use an APIC at all. It overrides the x86_init.mpparse.parse_smp_config() callback, resets num_processors and counts how many of them are provided by the hypervisor. This is in the way of cleaning up the APIC registration. Prevent MADT registration for XEN/PV temporarily until the rework is completed and XEN/PV can use the MADT again. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/acpi/boot.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -23,6 +23,8 @@ #include #include =20 +#include + #include #include #include @@ -166,7 +168,8 @@ static int __init acpi_parse_madt(struct =20 static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) { - topology_register_apic(apic_id, acpi_id, present); + if (!xen_pv_domain()) + topology_register_apic(apic_id, acpi_id, present); } =20 static bool __init acpi_is_processor_usable(u32 lapic_flags) @@ -1087,7 +1090,8 @@ static int __init early_acpi_parse_madt_ return count; } =20 - register_lapic_address(acpi_lapic_addr); + if (!xen_pv_domain()) + register_lapic_address(acpi_lapic_addr); =20 return count; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E28E57CF06 for ; Tue, 13 Feb 2024 21:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858348; cv=none; b=Yc2OTmmwfhKbHNT3i6225yojbFZEAJQMITr3nxrl8yaMAQlvVIe8V7Wuk0o2iyEvUdHT/JQ341qCW4Ah5nEv/O4QapaZ20mYq3qwN8yi6nRfVFHEs5A27r2YHyJFlfFKKCnMGM7kDIvW7mgqpHuANYTpbIUNENXXX58vq9X2rSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858348; c=relaxed/simple; bh=BKWYJny06EjSOf0YcTioblR9k858pQD/ggIOMn3ec8U=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=bSgaNqgkHMuUqTm5WFPNnyzKkhvdd/xqtom5NWdC64NW0CR6hB3zOKYbGc7DEGU0iqxhG6NENTq8ZuZFJAd2j12I9a+jdvBY1uCT4EE9t6ys5i+u1QerGesXDhvpvsbdBFHfo5x/98pKneoUhOloIcqZafEiz1V1Ezd9hGu3H1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=YKRWzRM5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=C0/07zds; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="YKRWzRM5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="C0/07zds" Message-ID: <20240213210251.940043512@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858345; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0wXS/SNETV4wAhaE3jXhuw2f33pvJhCIS1T6dH7Hlc0=; b=YKRWzRM5Vv6CatVZE6GJiZky0y16vUHRoIYSHeK8wbCLpCApmGLZfJqYZtakDblItvwW2K MM8btWamh1bYtiZcQH43neQ6gLlt7bt92nlfDmlmVn1oP8Dd5GHGHXAFPFQhUufndu78MZ XYkUGMHXXhytlM/qwZckx0MNXBp0QsyTpGqvtH9wH7heTQ40Hni9xWjNqE5xwyA3DgL8S6 o8v9gdfYTd1/IwPev+tvMozhOK+J/vmaQHecRJoJr+5rPy2HoG4ZOWuoRTCeElbTeOAKdc ouhiaScok+OWArebdDi42xmSK0XFlsxBaiPJILnv0M3whTAtPNzXKDEtTZ7wjg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858345; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0wXS/SNETV4wAhaE3jXhuw2f33pvJhCIS1T6dH7Hlc0=; b=C0/07zds2qQFcd9P54O4n2UDteJPiyDNftbhN9DwthLlfW7OTpHNfd2/Ops/AHMD70zoUi cbjz9ZzK+cd34QDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 08/30] x86/xen/smp_pv: Register fake APICs References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:44 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner XENPV does not use the APIC. It's just piggy packing on the infrastructure and fiddles with global variables as it sees fit. These global variables are going away, so let XENPV register pseudo APIC IDs to keep the accounting correct and keep up the illusion that XEN/PV is something sane. Signed-off-by: Thomas Gleixner --- arch/x86/xen/smp_pv.c | 35 +++++++++-------------------------- 1 file changed, 9 insertions(+), 26 deletions(-) --- --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -29,6 +29,7 @@ #include #include #include +#include #include =20 #include @@ -150,34 +151,16 @@ int xen_smp_intr_init_pv(unsigned int cp =20 static void __init xen_pv_smp_config(void) { - int i, rc; - unsigned int subtract =3D 0; + u32 apicid =3D 0; + int i; =20 - num_processors =3D 0; - disabled_cpus =3D 0; - for (i =3D 0; i < nr_cpu_ids; i++) { - rc =3D HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL); - if (rc >=3D 0) { - num_processors++; - set_cpu_possible(i, true); - } else { - set_cpu_possible(i, false); - set_cpu_present(i, false); - subtract++; - } + topology_register_boot_apic(apicid++); + + for (i =3D 1; i < nr_cpu_ids; i++) { + if (HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL) < 0) + break; + topology_register_apic(apicid++, CPU_ACPIID_INVALID, true); } -#ifdef CONFIG_HOTPLUG_CPU - /* This is akin to using 'nr_cpus' on the Linux command line. - * Which is OK as when we use 'dom0_max_vcpus=3DX' we can only - * have up to X, while nr_cpu_ids is greater than X. This - * normally is not a problem, except when CPU hotplugging - * is involved and then there might be more than X CPUs - * in the guest - which will not work as there is no - * hypercall to expand the max number of VCPUs an already - * running guest has. So cap it up to X. */ - if (subtract) - set_nr_cpu_ids(nr_cpu_ids - subtract); -#endif /* Pretend to be a proper enumerated system */ smp_found_config =3D 1; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61FE67D41D for ; Tue, 13 Feb 2024 21:05:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858350; cv=none; b=Y3irA3RT68Gg8pqVtZnB9apxjqAttNRcn+v9BlE+3F35aYCQxnkF9wfYkmIZtNvvOGNqWmBTkALsGl1C2ERVGaW6FuwaxYWsdyuT1WkuGoMPkt8uGsy0HntpN1rWSG/TGe+egX1fabhYoz+rmXOlkaSuAM+xBQ+9DdFv3+27VWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858350; c=relaxed/simple; bh=o725dqFIOZr2sPbP/ZZcIuYm0Aik+XXCE4cbMGhjbD8=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=N4Ev9cj09/yDf6FJT4ZZ708c8Kg2HpY4zQFlLPFd+vcjhEGL01cwRHSy0aEXdFE9GH9TtiEFnYFQmfaWQ47p9E2YgS1W1cd5mxDeqbQxonaXCu1PAXMTYnTmoU4lDNwqu8VHFrUw6fpyahfOkzZ1NcunU2kvLneAgfR2iwnvwmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BFGcof8a; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9MYtQQII; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BFGcof8a"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9MYtQQII" Message-ID: <20240213210251.994756960@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3hjSQJVEGCG5vViUjmCCOY+diMogglZD/H0kl7y0KTM=; b=BFGcof8aocKwVc2WSG9Utw44bpX01HqYuvWLIHdLjbONSKS27YbbYMFu9QRdGpCPeeS211 8UnEvsJ2JVPwjEykrF8S7xsMyjKshvJQB1HUI+2w+IAcsxWOWAC44dqi+5dwm6OcREYaP2 Uu6kyej3rTn2U1gWowYCPce8sm7dycYAFNLaathg2jlcQMOQuugKIe2P9tdeh/Nrwkd1GB oOVP09RXxiJzgISRon7V7A91yw/SHYcczFaE5JZjG9/QJXnFF7Y9xcxCrZg9DKbuz5yXVr bhDsqlZV8zyLsAx9kKzRPQU/290e81vLDznfCYjcVaf/DgbCSA1EE7Ls2b0d3Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3hjSQJVEGCG5vViUjmCCOY+diMogglZD/H0kl7y0KTM=; b=9MYtQQIIpJZ4zASSPb0mzdEyZWq6TtzJwgVz11sUg4joCcaLWBpYdF9htmXaCYdq7mkT/a 6mjx1yEEIcV9gHCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 09/30] x86/cpu/topology: Confine topology information References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:46 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Now that all external fiddling with num_processors and disabled_cpus is gone, move the last user prefill_possible_map() into the topology code too and remove the global visibility of these variables. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/smp.h | 3 - arch/x86/kernel/apic/apic.c | 1=20 arch/x86/kernel/cpu/topology.c | 76 ++++++++++++++++++++++++++++++++++++= +++-- arch/x86/kernel/smpboot.c | 72 ------------------------------------= -- 4 files changed, 74 insertions(+), 78 deletions(-) --- --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -9,7 +9,6 @@ #include =20 extern int smp_num_siblings; -extern unsigned int num_processors; =20 DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); @@ -174,8 +173,6 @@ static inline struct cpumask *cpu_llc_sh } #endif /* CONFIG_SMP */ =20 -extern unsigned disabled_cpus; - #ifdef CONFIG_DEBUG_NMI_SELFTEST extern void nmi_selftest(void); #else --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2054,7 +2054,6 @@ void __init init_apic_mappings(void) pr_info("APIC: disable apic facility\n"); apic_disable(); } - num_processors =3D 1; } } =20 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -29,8 +29,8 @@ u32 cpuid_to_apicid[] __read_mostly =3D { */ static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; =20 -unsigned int num_processors; -unsigned disabled_cpus; +static unsigned int num_processors; +static unsigned int disabled_cpus; =20 /* * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated @@ -174,6 +174,71 @@ static int generic_processor_info(int ap return cpu; } =20 +static int __initdata setup_possible_cpus =3D -1; + +/* + * cpu_possible_mask should be static, it cannot change as cpu's + * are onlined, or offlined. The reason is per-cpu data-structures + * are allocated by some modules at init time, and don't expect to + * do this dynamically on cpu arrival/departure. + * cpu_present_mask on the other hand can change dynamically. + * In case when cpu_hotplug is not compiled, then we resort to current + * behaviour, which is cpu_possible =3D=3D cpu_present. + * - Ashok Raj + * + * Three ways to find out the number of additional hotplug CPUs: + * - If the BIOS specified disabled CPUs in ACPI/mptables use that. + * - The user can overwrite it with possible_cpus=3DNUM + * - Otherwise don't reserve additional CPUs. + * We do this because additional CPUs waste a lot of memory. + * -AK + */ +__init void prefill_possible_map(void) +{ + int i, possible; + + i =3D setup_max_cpus ?: 1; + if (setup_possible_cpus =3D=3D -1) { + possible =3D num_processors; +#ifdef CONFIG_HOTPLUG_CPU + if (setup_max_cpus) + possible +=3D disabled_cpus; +#else + if (possible > i) + possible =3D i; +#endif + } else + possible =3D setup_possible_cpus; + + total_cpus =3D max_t(int, possible, num_processors + disabled_cpus); + + /* nr_cpu_ids could be reduced via nr_cpus=3D */ + if (possible > nr_cpu_ids) { + pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", + possible, nr_cpu_ids); + possible =3D nr_cpu_ids; + } + +#ifdef CONFIG_HOTPLUG_CPU + if (!setup_max_cpus) +#endif + if (possible > i) { + pr_warn("%d Processors exceeds max_cpus limit of %u\n", + possible, setup_max_cpus); + possible =3D i; + } + + set_nr_cpu_ids(possible); + + pr_info("Allowing %d CPUs, %d hotplug CPUs\n", + possible, max_t(int, possible - num_processors, 0)); + + reset_cpu_possible_mask(); + + for (i =3D 0; i < possible; i++) + set_cpu_possible(i, true); +} + /** * topology_register_apic - Register an APIC in early topology maps * @apic_id: The APIC ID to set up @@ -251,6 +316,13 @@ void topology_hotunplug_apic(unsigned in } #endif =20 +static int __init _setup_possible_cpus(char *str) +{ + get_option(&str, &setup_possible_cpus); + return 0; +} +early_param("possible_cpus", _setup_possible_cpus); + static int __init apic_set_disabled_cpu_apicid(char *arg) { if (!arg || !get_option(&arg, &disabled_cpu_apicid)) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1291,78 +1291,6 @@ void __init native_smp_cpus_done(unsigne cache_aps_init(); } =20 -static int __initdata setup_possible_cpus =3D -1; -static int __init _setup_possible_cpus(char *str) -{ - get_option(&str, &setup_possible_cpus); - return 0; -} -early_param("possible_cpus", _setup_possible_cpus); - - -/* - * cpu_possible_mask should be static, it cannot change as cpu's - * are onlined, or offlined. The reason is per-cpu data-structures - * are allocated by some modules at init time, and don't expect to - * do this dynamically on cpu arrival/departure. - * cpu_present_mask on the other hand can change dynamically. - * In case when cpu_hotplug is not compiled, then we resort to current - * behaviour, which is cpu_possible =3D=3D cpu_present. - * - Ashok Raj - * - * Three ways to find out the number of additional hotplug CPUs: - * - If the BIOS specified disabled CPUs in ACPI/mptables use that. - * - The user can overwrite it with possible_cpus=3DNUM - * - Otherwise don't reserve additional CPUs. - * We do this because additional CPUs waste a lot of memory. - * -AK - */ -__init void prefill_possible_map(void) -{ - int i, possible; - - i =3D setup_max_cpus ?: 1; - if (setup_possible_cpus =3D=3D -1) { - possible =3D num_processors; -#ifdef CONFIG_HOTPLUG_CPU - if (setup_max_cpus) - possible +=3D disabled_cpus; -#else - if (possible > i) - possible =3D i; -#endif - } else - possible =3D setup_possible_cpus; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 10/30] x86/cpu/topology: Simplify APIC registration References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:47 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Having the same check whether the number of assigned CPUs has reached the nr_cpu_ids limit twice in the same code path is pointless. Repeating the information that CPUs are ignored over and over is also pointless noise. Remove the redundant check and reduce the noise by using a pr_warn_once(). Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -107,14 +107,6 @@ static int allocate_logical_cpuid(u32 ap if (cpu >=3D 0) return cpu; =20 - /* Allocate a new cpuid. */ - if (nr_logical_cpuids >=3D nr_cpu_ids) { - WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " - "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apic_id); - return -EINVAL; - } - cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; return nr_logical_cpuids++; } @@ -135,7 +127,7 @@ static void cpu_update_apic(int cpu, u32 =20 static int generic_processor_info(int apicid) { - int cpu, max =3D nr_cpu_ids; + int cpu; =20 /* The boot CPU must be set before MADT/MPTABLE parsing happens */ if (cpuid_to_apicid[0] =3D=3D BAD_APICID) @@ -155,21 +147,12 @@ static int generic_processor_info(int ap } =20 if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - + pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); disabled_cpus++; - return -EINVAL; + return -ENOSPC; } =20 cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - cpu_update_apic(cpu, apicid); return cpu; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6B657E113 for ; Tue, 13 Feb 2024 21:05:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858352; cv=none; b=hr6Nx3VVzoYkDe3WqjwtPhNZ99DHWBIF9/dSR3J72t+x0PXk4tT+Yh+adLsxGK5GwatyY90eROYGYy3saQdk5EcudgqiJgheGB7idaliGoW2IMyghskedqSw75wsbukcaA3JN5+XBi98UFr+qazQA7GKOyvEXcQygTY7oxU+LIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858352; c=relaxed/simple; bh=GDWzEPUb9zuFYimCQyWCbLV5rCLk5kjo7hAaaidpubs=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=QwkftzEaSjWUfw3cG0ewIzuc+n8TSdOJX4Zd1Y0jBwZ0I3piU3vQFZz0JWeefGtF/SGZ1oeIklIEPOOcRYdtHHV2TTDhCt0rnagQ0zHdzBrYbKLlU2jXXZkdNml3wh/LNCnh7ZPwTFcOuO9/uoSeTR0i6YTQ8PZaLW2K3XDFnwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2iheBCoV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bKVbQihw; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2iheBCoV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bKVbQihw" Message-ID: <20240213210252.111451909@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OpypAhqmQZrkizNfmx8c+dbmLYdO8pqQFziwZQcde9M=; b=2iheBCoVT54Rj25Lay1jtH5UsC9YLCsmIPT2NYf46+bMtzi0Wz+rfdLM9AKKpH19UO5jjN j8IbFgvC86b+HFEr66JqgVFPimiYGSX2Rv+ZS+EKeuBO/XQoModFlRpHpxSEP+nIz5vFGP kF4grFWoIjJNuar/1b0ekkQCc3wCfav3ZxlaNoqyp9RkK3Z4L6SjckWsNtv4/a8uHwxB6j pAzwmjZDCJK9zSVAqfXtO+jqiJeUmmsGV7KrvIhqRxqTSBw4X1msEf2AQin4hMUhBWuAtE GQsp0cOsRqbjPn0MdDczjuaGOTz4uVAmnuwrtgtZsOVHU3dGxk1MP0pv6DpkcQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OpypAhqmQZrkizNfmx8c+dbmLYdO8pqQFziwZQcde9M=; b=bKVbQihwVarOzruRJQJfPao6FuH7BlEoS2px+Bzn6iuiWar2c/N92TDL65R5iHYelGTapn uo44UmovBMQweRDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 11/30] x86/cpu/topology: Use a data structure for topology info References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:49 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Put the processor accounting into a data structure, which will gain more topology related information in the next steps, and sanitize the accounting. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 59 ++++++++++++++++++++----------------= ----- 1 file changed, 29 insertions(+), 30 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -23,25 +23,24 @@ DECLARE_BITMAP(phys_cpu_present_map, MAX u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; =20 /* + * Keep track of assigned, disabled and rejected CPUs. Present assigned + * with 1 as CPU #0 is reserved for the boot CPU. + */ +static struct { + unsigned int nr_assigned_cpus; + unsigned int nr_disabled_cpus; + unsigned int nr_rejected_cpus; +} topo_info __read_mostly =3D { + .nr_assigned_cpus =3D 1, +}; + +/* * Processor to be disabled specified by kernel parameter * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to * avoid undefined behaviour caused by sending INIT from AP to BSP. */ static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; =20 -static unsigned int num_processors; -static unsigned int disabled_cpus; - -/* - * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated - * contiguously, it equals to current allocated max logical CPU ID plus 1. - * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, - * so the maximum of nr_logical_cpuids is nr_cpu_ids. - * - * NOTE: Reserve 0 for BSP. - */ -static int nr_logical_cpuids =3D 1; - bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -75,7 +74,7 @@ static int __init smp_init_primary_threa return 0; } =20 - for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) + for (cpu =3D 0; cpu < topo_info.nr_assigned_cpus; cpu++) cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); return 0; } @@ -89,7 +88,7 @@ static int topo_lookup_cpuid(u32 apic_id int i; =20 /* CPU# to APICID mapping is persistent once it is established */ - for (i =3D 0; i < nr_logical_cpuids; i++) { + for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { if (cpuid_to_apicid[i] =3D=3D apic_id) return i; } @@ -107,22 +106,21 @@ static int allocate_logical_cpuid(u32 ap if (cpu >=3D 0) return cpu; =20 - cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; - return nr_logical_cpuids++; + return topo_info.nr_assigned_cpus++; } =20 -static void cpu_update_apic(int cpu, u32 apicid) +static void cpu_update_apic(unsigned int cpu, u32 apic_id) { #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; #endif + cpuid_to_apicid[cpu] =3D apic_id; set_cpu_possible(cpu, true); - set_bit(apicid, phys_cpu_present_map); + set_bit(apic_id, phys_cpu_present_map); set_cpu_present(cpu, true); - num_processors++; =20 if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apicid); + cpu_mark_primary_thread(cpu, apic_id); } =20 static int generic_processor_info(int apicid) @@ -137,18 +135,18 @@ static int generic_processor_info(int ap return 0; =20 if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; + int thiscpu =3D topo_info.nr_assigned_cpus + topo_info.nr_disabled_cpus; =20 pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", thiscpu, apicid); =20 - disabled_cpus++; + topo_info.nr_rejected_cpus++; return -ENODEV; } =20 - if (num_processors >=3D nr_cpu_ids) { + if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) { pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); - disabled_cpus++; + topo_info.nr_rejected_cpus++; return -ENOSPC; } =20 @@ -178,14 +176,16 @@ static int __initdata setup_possible_cpu */ __init void prefill_possible_map(void) { + unsigned int num_processors =3D topo_info.nr_assigned_cpus; + unsigned int disabled_cpus =3D topo_info.nr_disabled_cpus; int i, possible; =20 i =3D setup_max_cpus ?: 1; if (setup_possible_cpus =3D=3D -1) { - possible =3D num_processors; + possible =3D topo_info.nr_assigned_cpus; #ifdef CONFIG_HOTPLUG_CPU if (setup_max_cpus) - possible +=3D disabled_cpus; + possible +=3D num_processors; #else if (possible > i) possible =3D i; @@ -238,7 +238,7 @@ void __init topology_register_apic(u32 a } =20 if (!present) { - disabled_cpus++; + topo_info.nr_disabled_cpus++; return; } =20 @@ -295,7 +295,6 @@ void topology_hotunplug_apic(unsigned in per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; clear_bit(apic_id, phys_cpu_present_map); set_cpu_present(cpu, false); - num_processors--; } #endif From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F127E76D for ; Tue, 13 Feb 2024 21:05:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858353; cv=none; b=LFf7/m2VbUPu0VrhKFytED836/bRwoZLYbLAcr8Yoy/5vmVRQm/tq9fJL01Nx7csBo5lQi1/ybIjcAFX5ebfAEsIeNLmaE3TSS1Yvbf5n008PpGgOY2KAkvmckZ2FbZ4FW2O8bDpI3eLJaLSUPu6BVJR/zELCtUR68cZDZRQ0A8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858353; c=relaxed/simple; bh=R/gkXFCa7QGppvkzNKvypYWWUarLK4WF7H1CZllLDnI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=AJlPQdFXtYF+wVpnLKUTQxe4FyZaDIlyEGKRua4nGTJlAcPd3cAPgTIbV/a58T1PfYhWeTouOY1x8PTVkMFPbcNJNV3P1bsJgO/TZY2fLVdnwRyPxDw14rWvMqO5j9dCEIjk2o/xG9eQEwdXWU+G2GvwM9ogPFzoEFWleBVdv78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eTe89Xjw; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rc+ZWqrM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eTe89Xjw"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rc+ZWqrM" Message-ID: <20240213210252.170806023@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858350; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=B36m24M4ceBkId72kqabGdQ4QnOj4P1IRr6RI4djRX0=; b=eTe89XjwswmLTEZXp4GBgTPgUqu7/kJ86OAYnAsJ0r+4KwmEvrE38VqJiul34/OiRpkju1 XOsRW5ceSiPdGrSZBt5yN/m3zWS0of29JRqm4rA5qBmZeeVCfNe+x8IIPpokk2cQJnRe6z bi8Wxu7hm6qrBY39++yWeKw1T34Jey95jMj6J3VVhzbrTOPFwiibqTLk8xNpNRHukiqNXY gA9coNsaqsTVJ7k8GU779PKG/gZxJ7r0O9MfNbdgLzPjJFlRL0zk8vxMxPM095hkRANXzE mupfQj/8lPLAY1/yb/4uqwdu4HWE2BDjGPyHUR8jZw7PktHC1mA/yUj50Uj/1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858350; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=B36m24M4ceBkId72kqabGdQ4QnOj4P1IRr6RI4djRX0=; b=rc+ZWqrMgaPp6cWD5WnAtrvpaWOyNa3PPcd+03tDCUDeVyP3JPmDJhHMkrvuZBvubBi1Rd fIwsmFSB++O5x6BA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 12/30] x86/smpboot: Make error message actually useful References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:50 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner "smpboot: native_kick_ap: bad cpu 33" is absolutely useless information. Replace it with something meaningful which allows to decode the failure condition. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/smpboot.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) --- --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1072,9 +1072,13 @@ int native_kick_ap(unsigned int cpu, str =20 pr_debug("++++++++++++++++++++=3D_---CPU UP %u\n", cpu); =20 - if (apicid =3D=3D BAD_APICID || !test_bit(apicid, phys_cpu_present_map) || - !apic_id_valid(apicid)) { - pr_err("%s: bad cpu %d\n", __func__, cpu); + if (apicid =3D=3D BAD_APICID || !apic_id_valid(apicid)) { + pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); + return -EINVAL; + } + + if (!test_bit(apicid, phys_cpu_present_map)) { + pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apic= id); return -EINVAL; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA98080040 for ; Tue, 13 Feb 2024 21:05:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858355; cv=none; b=qtQkK0A3q7iQdUledmOKoP7cR0+OB/ZDnuxuhh1TyGO+4+ClO/eqmsV7DU93eibfbZBEZecXTzcEsX49dvu88+9IppOdaCUBucJOGCphDtZso9KN/pLQ380O05iBw3vjUaSr5k3o5y78glgbgr50czMAQzP9UzcupV5EmVt53Q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858355; c=relaxed/simple; bh=D/x2pZmXYVi1aeoQgeo6/HbqC0uU3avn6Qrbh4JB+Bc=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=re2Qsao3Na5CBrdN7c9TQUNzixfzL9NHMrbuAilbecNaSKE8KZKB3NAroMQxfkhl2GhOvIragNUjwSKsrnClZF5Jc83sSSosgaMMMHHNklRoSnuIMjonS5f+k2hWs0KK49DaTz8lvB0Q1pwzChz1FM+oarjyknMe48/HK0M6WxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tQx8cm/g; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tsiW4iL/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tQx8cm/g"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tsiW4iL/" Message-ID: <20240213210252.230433953@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=De/C8B6JlgmBVTvJK21S3TwnUST7UJwZGYAmiPz2Plg=; b=tQx8cm/gxd7WIJbLhuAnBwQ/NwKlo+twl+nVOcR8cAk8fSK8NPlLaUWQbRyAm4xrrausC8 RFuxowPH8WKHCZQ0ivRwcMScM+mi+Jt7v9sb5dr7yxOeHbhRr/So8taz6TIkuJimttUcAW EP9z26kaFK54F7QMlC6Rs/URIAk+EY0ly4D9bz6YEVnvB1XKJOsVQO6ZgQd7O2diwVAXwn ufjOhPPV+nH1flP8tLPCsE14QAlIRycw0KpdU2b3viB0y5Zokfy9352tdwzwPSpmPC2T8R 68BK6DAj3sl6HvliUnEmbdXDdcNccfKvRo7prSC1mMv3s08JZ9ZFLukHM5YIRg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=De/C8B6JlgmBVTvJK21S3TwnUST7UJwZGYAmiPz2Plg=; b=tsiW4iL/9VrO7T84ROI94S4EljMFr1gET9WCFtWkLp01zFGHoHDsqs6jkM8izUnf1HVLvt 9Yubkdq0VWUq42Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 13/30] x86/cpu/topology: Sanitize the APIC admission logic References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:52 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Move the actually required content of generic_processor_id() into the call sites and use common helper functions for them. This separates the early boot registration and the ACPI hotplug mechanism completely which allows further cleanups and improvements. Signed-off-by: Thomas Gleixner --- V3: Check for disabled APIC early and exclude the boot APIC ID from the CPUNR exhaustion check. - Sohil, Michael Rename topo_assign_cpunr() to topo_get_cpunr() as the assignment happens elsewhere - Arjan --- arch/x86/kernel/cpu/topology.c | 159 +++++++++++++++++++-----------------= ----- 1 file changed, 77 insertions(+), 82 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -30,8 +30,10 @@ static struct { unsigned int nr_assigned_cpus; unsigned int nr_disabled_cpus; unsigned int nr_rejected_cpus; + u32 boot_cpu_apic_id; } topo_info __read_mostly =3D { .nr_assigned_cpus =3D 1, + .boot_cpu_apic_id =3D BAD_APICID, }; =20 /* @@ -83,78 +85,6 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -static int topo_lookup_cpuid(u32 apic_id) -{ - int i; - - /* CPU# to APICID mapping is persistent once it is established */ - for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { - if (cpuid_to_apicid[i] =3D=3D apic_id) - return i; - } - return -ENODEV; -} - -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(u32 apic_id) -{ - int cpu =3D topo_lookup_cpuid(apic_id); - - if (cpu >=3D 0) - return cpu; - - return topo_info.nr_assigned_cpus++; -} - -static void cpu_update_apic(unsigned int cpu, u32 apic_id) -{ -#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; -#endif - cpuid_to_apicid[cpu] =3D apic_id; - set_cpu_possible(cpu, true); - set_bit(apic_id, phys_cpu_present_map); - set_cpu_present(cpu, true); - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apic_id); -} - -static int generic_processor_info(int apicid) -{ - int cpu; - - /* The boot CPU must be set before MADT/MPTABLE parsing happens */ - if (cpuid_to_apicid[0] =3D=3D BAD_APICID) - panic("Boot CPU APIC not registered yet\n"); - - if (apicid =3D=3D boot_cpu_physical_apicid) - return 0; - - if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D topo_info.nr_assigned_cpus + topo_info.nr_disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - topo_info.nr_rejected_cpus++; - return -ENODEV; - } - - if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) { - pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); - topo_info.nr_rejected_cpus++; - return -ENOSPC; - } - - cpu =3D allocate_logical_cpuid(apicid); - cpu_update_apic(cpu, apicid); - return cpu; -} - static int __initdata setup_possible_cpus =3D -1; =20 /* @@ -222,6 +152,43 @@ static int __initdata setup_possible_cpu set_cpu_possible(i, true); } =20 +static int topo_lookup_cpuid(u32 apic_id) +{ + int i; + + /* CPU# to APICID mapping is persistent once it is established */ + for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { + if (cpuid_to_apicid[i] =3D=3D apic_id) + return i; + } + return -ENODEV; +} + +static int topo_get_cpunr(u32 apic_id) +{ + int cpu =3D topo_lookup_cpuid(apic_id); + + if (cpu >=3D 0) + return cpu; + + return topo_info.nr_assigned_cpus++; +} + +static void topo_set_cpuids(unsigned int cpu, u32 apic_id, u32 acpi_id) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; + early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; +#endif + cpuid_to_apicid[cpu] =3D apic_id; + + set_cpu_possible(cpu, true); + set_cpu_present(cpu, true); + + if (system_state !=3D SYSTEM_BOOTING) + cpu_mark_primary_thread(cpu, apic_id); +} + /** * topology_register_apic - Register an APIC in early topology maps * @apic_id: The APIC ID to set up @@ -234,17 +201,40 @@ void __init topology_register_apic(u32 a =20 if (apic_id >=3D MAX_LOCAL_APIC) { pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); + topo_info.nr_rejected_cpus++; return; } =20 - if (!present) { - topo_info.nr_disabled_cpus++; + if (disabled_cpu_apicid =3D=3D apic_id) { + pr_info("Disabling CPU as requested via 'disable_cpu_apicid=3D0x%x'.\n",= apic_id); + topo_info.nr_rejected_cpus++; return; } =20 - cpu =3D generic_processor_info(apic_id); - if (cpu >=3D 0) - early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + /* CPU numbers exhausted? */ + if (apic_id !=3D topo_info.boot_cpu_apic_id && topo_info.nr_assigned_cpus= >=3D nr_cpu_ids) { + pr_warn_once("CPU limit of %d reached. Ignoring further CPUs\n", nr_cpu_= ids); + topo_info.nr_rejected_cpus++; + return; + } + + if (present) { + set_bit(apic_id, phys_cpu_present_map); + + /* + * Double registration is valid in case of the boot CPU + * APIC because that is registered before the enumeration + * of the APICs via firmware parsers or VM guest + * mechanisms. + */ + if (apic_id =3D=3D topo_info.boot_cpu_apic_id) + cpu =3D 0; + else + cpu =3D topo_get_cpunr(apic_id); + topo_set_cpuids(cpu, apic_id, acpi_id); + } else { + topo_info.nr_disabled_cpus++; + } } =20 /** @@ -255,8 +245,10 @@ void __init topology_register_apic(u32 a */ void __init topology_register_boot_apic(u32 apic_id) { - cpuid_to_apicid[0] =3D apic_id; - cpu_update_apic(0, apic_id); + WARN_ON_ONCE(topo_info.boot_cpu_apic_id !=3D BAD_APICID); + + topo_info.boot_cpu_apic_id =3D apic_id; + topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); } =20 #ifdef CONFIG_ACPI_HOTPLUG_CPU @@ -274,10 +266,13 @@ int topology_hotplug_apic(u32 apic_id, u =20 cpu =3D topo_lookup_cpuid(apic_id); if (cpu < 0) { - cpu =3D generic_processor_info(apic_id); - if (cpu >=3D 0) - per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) + return -ENOSPC; + + cpu =3D topo_assign_cpunr(apic_id); } + set_bit(apic_id, phys_cpu_present_map); + topo_set_cpuids(cpu, apic_id, acpi_id); return cpu; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 503AB80628 for ; Tue, 13 Feb 2024 21:05:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858357; cv=none; b=bYtLBWzccVwn+krnWwiKlrttL6sPS4oKO+OGxygFacWvbp2vTp9DEoBX1kjQVjz9qmHxkxY4wkLFIFRV3CkshaECT+dRN8o/3PqVK4Qi7mxqjjgFT6JEEmi9JEDVjxJ6Pi7NegesFmJp+Ags8T7JbNFS7s6yGF6UYNJcNKV2x+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858357; c=relaxed/simple; bh=/89t/3lOL00dew7b68cAxecRvXLm9HLTc1+2p89ODr4=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=oH7nlT+reADDzfVwlpp+J6wLalBUYnsZ1xOyOs11zq/IMfGE9c/lR/MnnEm1/LLglw39qXf1kPAkB3ygZR/KXOgvaxu9b0Jp7cZ+6rsu4sUgrEYISAgTG1URjs+LIPf0O0geEC4rgJ6eHTsD0gbZwF36o44KK771HdRHEnyW2vQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=REyDI6Ju; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uL6bIlbL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="REyDI6Ju"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uL6bIlbL" Message-ID: <20240213210252.290098853@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858353; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=U2ZN7IfJ+/MPORS30ogA2diW3eN4Yj9P0j/aVErVJyo=; b=REyDI6JuOwGvbnY95ihyC7fLhIS9IQmZCNGgFtbtzteK8un5IbImdg2ZnJb3uOK6r6kWA7 aIXjXb3pwbUvtkr+DRk3NB8ZHQSe4PE+1VBYpxnrhUESkDchsP9e73cECd5V8fwILzvRSv ZiU3/DB4a7s5/sKxs4hItetWkEz+NhLJbop3io5td4+E4dtow/fcU/kXc00rMc66NBP5nn GFUWSZwDoV0A039BkVcT55BEaAnuNSUSZQdRR9slDuYx9DZWGWpmwrumJjbk6+FbKFIJ7b yHncBl/uUO6eKG7x9/hCN0VV+4G0PJeqXZvAqWkoQL6rtzQOpwOo62jEZW5DUA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858353; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=U2ZN7IfJ+/MPORS30ogA2diW3eN4Yj9P0j/aVErVJyo=; b=uL6bIlbLoGYwneN0akI2/Ki/tXv0xBxV4ND2xSunrcXOHDk7CGV9LAIO7XYDqoI8p8qrP9 1ih/vk7dB7XY+XAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 14/30] x86/cpu/topology: Rework possible CPU management References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:53 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Managing possible CPUs is an unreadable and uncomprehensible maze. Aside of that it's backwards because it applies command line limits after registering all APICs. Rewrite it so that it: - Applies the command line limits upfront so that only the allowed amount of APIC IDs can be registered. - Applies eventual late restrictions in an understandable way - Uses simple min_t() calculations which are trivial to follow. - Provides a separate function for resetting to UP mode late in the bringup process. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 + arch/x86/include/asm/cpu.h | 10 -- arch/x86/include/asm/topology.h | 1=20 arch/x86/kernel/cpu/topology.c | 176 ++++++++++++++++++++++++-----------= ----- arch/x86/kernel/setup.c | 9 -- arch/x86/kernel/smpboot.c | 6 - 6 files changed, 118 insertions(+), 89 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -175,6 +175,9 @@ extern void topology_register_apic(u32 a extern void topology_register_boot_apic(u32 apic_id); extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); extern void topology_hotunplug_apic(unsigned int cpu); +extern void topology_apply_cmdline_limits_early(void); +extern void topology_init_possible_cpus(void); +extern void topology_reset_possible_cpus_up(void); =20 #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } @@ -190,6 +193,8 @@ static inline void apic_intr_mode_init(v static inline void lapic_assign_system_vectors(void) { } static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } static inline bool apic_needs_pit(void) { return true; } +static inline void topology_apply_cmdline_limits_early(void) { } +static inline void topology_init_possible_cpus(void) { } #endif /* !CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_X2APIC --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -9,18 +9,10 @@ #include #include =20 -#ifdef CONFIG_SMP - -extern void prefill_possible_map(void); - -#else /* CONFIG_SMP */ - -static inline void prefill_possible_map(void) {} - +#ifndef CONFIG_SMP #define cpu_physical_id(cpu) boot_cpu_physical_apicid #define cpu_acpi_id(cpu) 0 #define safe_smp_processor_id() 0 - #endif /* CONFIG_SMP */ =20 #ifdef CONFIG_HOTPLUG_CPU --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -191,6 +191,7 @@ static inline bool topology_is_primary_t { return cpumask_test_cpu(cpu, cpu_primary_thread_mask); } + #else /* CONFIG_SMP */ #define topology_max_packages() (1) static inline int --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include #include =20 @@ -85,73 +86,6 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -static int __initdata setup_possible_cpus =3D -1; - -/* - * cpu_possible_mask should be static, it cannot change as cpu's - * are onlined, or offlined. The reason is per-cpu data-structures - * are allocated by some modules at init time, and don't expect to - * do this dynamically on cpu arrival/departure. - * cpu_present_mask on the other hand can change dynamically. - * In case when cpu_hotplug is not compiled, then we resort to current - * behaviour, which is cpu_possible =3D=3D cpu_present. - * - Ashok Raj - * - * Three ways to find out the number of additional hotplug CPUs: - * - If the BIOS specified disabled CPUs in ACPI/mptables use that. - * - The user can overwrite it with possible_cpus=3DNUM - * - Otherwise don't reserve additional CPUs. - * We do this because additional CPUs waste a lot of memory. - * -AK - */ -__init void prefill_possible_map(void) -{ - unsigned int num_processors =3D topo_info.nr_assigned_cpus; - unsigned int disabled_cpus =3D topo_info.nr_disabled_cpus; - int i, possible; - - i =3D setup_max_cpus ?: 1; - if (setup_possible_cpus =3D=3D -1) { - possible =3D topo_info.nr_assigned_cpus; -#ifdef CONFIG_HOTPLUG_CPU - if (setup_max_cpus) - possible +=3D num_processors; -#else - if (possible > i) - possible =3D i; -#endif - } else - possible =3D setup_possible_cpus; - - total_cpus =3D max_t(int, possible, num_processors + disabled_cpus); - - /* nr_cpu_ids could be reduced via nr_cpus=3D */ - if (possible > nr_cpu_ids) { - pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", - possible, nr_cpu_ids); - possible =3D nr_cpu_ids; - } - -#ifdef CONFIG_HOTPLUG_CPU - if (!setup_max_cpus) -#endif - if (possible > i) { - pr_warn("%d Processors exceeds max_cpus limit of %u\n", - possible, setup_max_cpus); - possible =3D i; - } - - set_nr_cpu_ids(possible); - - pr_info("Allowing %d CPUs, %d hotplug CPUs\n", - possible, max_t(int, possible - num_processors, 0)); - - reset_cpu_possible_mask(); - - for (i =3D 0; i < possible; i++) - set_cpu_possible(i, true); -} - static int topo_lookup_cpuid(u32 apic_id) { int i; @@ -293,12 +227,114 @@ void topology_hotunplug_apic(unsigned in } #endif =20 -static int __init _setup_possible_cpus(char *str) +#ifdef CONFIG_SMP +static unsigned int max_possible_cpus __initdata =3D NR_CPUS; + +/** + * topology_apply_cmdline_limits_early - Apply topology command line limit= s early + * + * Ensure that command line limits are in effect before firmware parsing + * takes place. + */ +void __init topology_apply_cmdline_limits_early(void) +{ + unsigned int possible =3D nr_cpu_ids; + + /* 'maxcpus=3D0' 'nosmp' 'nolapic' 'disableapic' 'noapic' */ + if (!setup_max_cpus || ioapic_is_disabled || apic_is_disabled) + possible =3D 1; + + /* 'possible_cpus=3DN' */ + possible =3D min_t(unsigned int, max_possible_cpus, possible); + + if (possible < nr_cpu_ids) { + pr_info("Limiting to %u possible CPUs\n", possible); + set_nr_cpu_ids(possible); + } +} + +static __init bool restrict_to_up(void) +{ + if (!smp_found_config || ioapic_is_disabled) + return true; + /* + * XEN PV is special as it does not advertise the local APIC + * properly, but provides a fake topology for it so that the + * infrastructure works. So don't apply the restrictions vs. APIC + * here. + */ + if (xen_pv_domain()) + return false; + + return apic_is_disabled; +} + +void __init topology_init_possible_cpus(void) +{ + unsigned int assigned =3D topo_info.nr_assigned_cpus; + unsigned int disabled =3D topo_info.nr_disabled_cpus; + unsigned int total =3D assigned + disabled; + unsigned int cpu, allowed =3D 1; + + if (!restrict_to_up()) { + if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { + disabled +=3D assigned - nr_cpu_ids; + assigned =3D nr_cpu_ids; + } + allowed =3D min_t(unsigned int, total, nr_cpu_ids); + } + + if (total > allowed) + pr_warn("%u possible CPUs exceed the limit of %u\n", total, allowed); + + assigned =3D min_t(unsigned int, allowed, assigned); + disabled =3D allowed - assigned; + + topo_info.nr_assigned_cpus =3D assigned; + topo_info.nr_disabled_cpus =3D disabled; + + total_cpus =3D allowed; + set_nr_cpu_ids(allowed); + + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); + if (topo_info.nr_rejected_cpus) + pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); + + init_cpu_present(cpumask_of(0)); + init_cpu_possible(cpumask_of(0)); + + for (cpu =3D 0; cpu < allowed; cpu++) { + u32 apicid =3D cpuid_to_apicid[cpu]; + + set_cpu_possible(cpu, true); + + if (apicid =3D=3D BAD_APICID) + continue; + + set_cpu_present(cpu, test_bit(apicid, phys_cpu_present_map)); + } +} + +/* + * Late SMP disable after sizing CPU masks when APIC/IOAPIC setup failed. + */ +void __init topology_reset_possible_cpus_up(void) { - get_option(&str, &setup_possible_cpus); + init_cpu_present(cpumask_of(0)); + init_cpu_possible(cpumask_of(0)); + + bitmap_zero(phys_cpu_present_map, MAX_LOCAL_APIC); + if (topo_info.boot_cpu_apic_id !=3D BAD_APICID) + set_bit(topo_info.boot_cpu_apic_id, phys_cpu_present_map); +} + +static int __init setup_possible_cpus(char *str) +{ + get_option(&str, &max_possible_cpus); return 0; } -early_param("possible_cpus", _setup_possible_cpus); +early_param("possible_cpus", setup_possible_cpus); +#endif =20 static int __init apic_set_disabled_cpu_apicid(char *arg) { --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1131,6 +1131,8 @@ void __init setup_arch(char **cmdline_p) =20 early_quirks(); =20 + topology_apply_cmdline_limits_early(); + /* * Parse SMP configuration. Try ACPI first and then the platform * specific parser. @@ -1138,13 +1140,10 @@ void __init setup_arch(char **cmdline_p) acpi_boot_init(); x86_init.mpparse.parse_smp_cfg(); =20 - /* - * Systems w/o ACPI and mptables might not have it mapped the local - * APIC yet, but prefill_possible_map() might need to access it. - */ + /* Last opportunity to detect and map the local APIC */ init_apic_mappings(); =20 - prefill_possible_map(); + topology_init_possible_cpus(); =20 init_cpu_to_node(); init_gi_nodes(); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1147,11 +1147,7 @@ static __init void disable_smp(void) pr_info("SMP disabled\n"); =20 disable_ioapic_support(); - - init_cpu_present(cpumask_of(0)); - init_cpu_possible(cpumask_of(0)); - - reset_phys_cpu_present_map(smp_found_config ? boot_cpu_physical_apicid : = 0); + topology_reset_possible_cpus_up(); =20 cpumask_set_cpu(0, topology_sibling_cpumask(0)); cpumask_set_cpu(0, topology_core_cpumask(0)); From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D8CC7E76D for ; Tue, 13 Feb 2024 21:05:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858358; cv=none; b=mkt7Js0pDgu7STYrqYyBZd2MqCg+h4i0e6TwsR5BPmX+6KAAwbJIeHhpNtheToF7K2UmumBZdFEQi4qUJW3HwZX3QQQjEpQ8pdGehQl4molB6u3rD/76KyuEbopMCPDnvW7x9oc0uknNWg6upWBMEgGqxvUfQRvd3MslKeI5fdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858358; c=relaxed/simple; bh=JTW4jUF4bw2Z2J20O1fkn2NaWfwrPB/09rDVcEOBOes=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=p31pPr0i2uZTFy5pfrIGieTD8fEKTbCOqp47h1gh0dKVdJJqpw5oM7+V27So2RO9Pt1UF2O5dN00CrFCCNSqNeGwZq+0Meq/yZr4aSGptysIc+2NRj8gQNob+qYESTKF/vu5Pm1309+821X3BidwX0T7vTYAbUXypzwgSxYHa7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Rs5MXGF8; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zvwylgMe; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Rs5MXGF8"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zvwylgMe" Message-ID: <20240213210252.348542071@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aFAX03aVjPEmwT7UTyknP3rbEgKma3/xTYdPSINFEHc=; b=Rs5MXGF8uXTwvniXF6SbnjdNWiY8sy/waZLfu5BufIwoR3McA7WP4mxWiKV009K4feCsO7 qQ55lmQrcc3CZqamUhF5yAf40LIuK/zr7CyEHeiharomLma1KiniyrXIpcbn8SKB+G6p2t j5ieNNh4a03gu2YQTDx0z8tltygkpQ7zmiPiNNZP0ZWMhOad4GkLAWUNIAQEQXRaQeTLzm 6QElRGLDgRAnkClP2bPYECoMjHFMyd7ZVWXi3lLzJ04MjvRki1wRZ3PULBVwnDrbAtK5hq qm6GBlHQr2o8pLWgmFz/1tZMjkfybVBUhUaJQ2yfHwHY+RKAO04sp5tsXs4hXQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aFAX03aVjPEmwT7UTyknP3rbEgKma3/xTYdPSINFEHc=; b=zvwylgMeuogM/svyGz5fdsAMgF0ofydnNkHgZN+RTWNaNjDZHfgfKNf2I6t/Fwvh01r9Oo h5oF+Vjyg1odXMDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 15/30] x86/cpu: Detect real BSP on crash kernels References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:54 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner When a kdump kernel is started from a crashing CPU then there is no guarantee that this CPU is the real boot CPU (BSP). If the kdump kernel tries to online the BSP then the INIT sequence will reset the machine. There is a command line option to prevent this, but in case of nested kdump kernels this is wrong. But that command line option is not required at all because the real BSP is enumerated as the first CPU by firmware. Support for the only known system which was different (Voyager) got removed long ago. Detect whether the boot CPU APIC ID is the first APIC ID enumerated by the firmware. If the first APIC ID enumerated is not matching the boot CPU APIC ID then skip registering it. Signed-off-by: Thomas Gleixner --- V3: Adopt to prior ordering and boot APIC exclusion changes V2: Check for the first enumerated APIC ID (Rui) --- Documentation/admin-guide/kdump/kdump.rst | 7 - Documentation/admin-guide/kernel-parameters.txt | 9 -- arch/x86/kernel/cpu/topology.c | 97 ++++++++++++++-----= ----- 3 files changed, 61 insertions(+), 52 deletions(-) --- --- a/Documentation/admin-guide/kdump/kdump.rst +++ b/Documentation/admin-guide/kdump/kdump.rst @@ -191,9 +191,7 @@ Dump-capture kernel config options (Arch CPU is enough for kdump kernel to dump vmcore on most of systems. =20 However, you can also specify nr_cpus=3DX to enable multiple processors - in kdump kernel. In this case, "disable_cpu_apicid=3D" is needed to - tell kdump kernel which cpu is 1st kernel's BSP. Please refer to - admin-guide/kernel-parameters.txt for more details. + in kdump kernel. =20 With CONFIG_SMP=3Dn, the above things are not related. =20 @@ -454,8 +452,7 @@ loading dump-capture kernel. to use multi-thread programs with it, such as parallel dump feature of makedumpfile. Otherwise, the multi-thread program may have a great performance degradation. To enable multi-cpu support, you should bring u= p an - SMP dump-capture kernel and specify maxcpus/nr_cpus, disable_cpu_apicid= =3D[X] - options while loading it. + SMP dump-capture kernel and specify maxcpus/nr_cpus options while loadin= g it. =20 * For s390x there are two kdump modes: If a ELF header is specified with the elfcorehdr=3D kernel parameter, it is used by the kdump kernel as it --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1100,15 +1100,6 @@ Disable TLBIE instruction. Currently does not work with KVM, with HASH MMU, or with coherent accelerators. =20 - disable_cpu_apicid=3D [X86,APIC,SMP] - Format: - The number of initial APIC ID for the - corresponding CPU to be disabled at boot, - mostly used for the kdump 2nd kernel to - disable BSP to wake up multiple CPUs without - causing system reset or hang due to sending - INIT from AP to BSP. - disable_ddw [PPC/PSERIES] Disable Dynamic DMA Window support. Use this to workaround buggy firmware. --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -32,18 +32,13 @@ static struct { unsigned int nr_disabled_cpus; unsigned int nr_rejected_cpus; u32 boot_cpu_apic_id; + u32 real_bsp_apic_id; } topo_info __read_mostly =3D { .nr_assigned_cpus =3D 1, .boot_cpu_apic_id =3D BAD_APICID, + .real_bsp_apic_id =3D BAD_APICID, }; =20 -/* - * Processor to be disabled specified by kernel parameter - * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to - * avoid undefined behaviour caused by sending INIT from AP to BSP. - */ -static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; - bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -123,6 +118,60 @@ static void topo_set_cpuids(unsigned int cpu_mark_primary_thread(cpu, apic_id); } =20 +static __init bool check_for_real_bsp(u32 apic_id) +{ + /* + * There is no real good way to detect whether this a kdump() + * kernel, but except on the Voyager SMP monstrosity which is not + * longer supported, the real BSP APIC ID is the first one which is + * enumerated by firmware. That allows to detect whether the boot + * CPU is the real BSP. If it is not, then do not register the APIC + * because sending INIT to the real BSP would reset the whole + * system. + * + * The first APIC ID which is enumerated by firmware is detectable + * because the boot CPU APIC ID is registered before that without + * invoking this code. + */ + if (topo_info.real_bsp_apic_id !=3D BAD_APICID) + return false; + + if (apic_id =3D=3D topo_info.boot_cpu_apic_id) { + topo_info.real_bsp_apic_id =3D apic_id; + return false; + } + + pr_warn("Boot CPU APIC ID not the first enumerated APIC ID: %x > %x\n", + topo_info.boot_cpu_apic_id, apic_id); + pr_warn("Crash kernel detected. Disabling real BSP to prevent machine INI= T\n"); + + topo_info.real_bsp_apic_id =3D apic_id; + return true; +} + +static __init void topo_register_apic(u32 apic_id, u32 acpi_id, bool prese= nt) +{ + int cpu; + + if (present) { + set_bit(apic_id, phys_cpu_present_map); + + /* + * Double registration is valid in case of the boot CPU + * APIC because that is registered before the enumeration + * of the APICs via firmware parsers or VM guest + * mechanisms. + */ + if (apic_id =3D=3D topo_info.boot_cpu_apic_id) + cpu =3D 0; + else + cpu =3D topo_get_cpunr(apic_id); + topo_set_cpuids(cpu, apic_id, acpi_id); + } else { + topo_info.nr_disabled_cpus++; + } +} + /** * topology_register_apic - Register an APIC in early topology maps * @apic_id: The APIC ID to set up @@ -131,16 +180,13 @@ static void topo_set_cpuids(unsigned int */ void __init topology_register_apic(u32 apic_id, u32 acpi_id, bool present) { - int cpu; - if (apic_id >=3D MAX_LOCAL_APIC) { pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); topo_info.nr_rejected_cpus++; return; } =20 - if (disabled_cpu_apicid =3D=3D apic_id) { - pr_info("Disabling CPU as requested via 'disable_cpu_apicid=3D0x%x'.\n",= apic_id); + if (check_for_real_bsp(apic_id)) { topo_info.nr_rejected_cpus++; return; } @@ -152,23 +198,7 @@ void __init topology_register_apic(u32 a return; } =20 - if (present) { - set_bit(apic_id, phys_cpu_present_map); - - /* - * Double registration is valid in case of the boot CPU - * APIC because that is registered before the enumeration - * of the APICs via firmware parsers or VM guest - * mechanisms. - */ - if (apic_id =3D=3D topo_info.boot_cpu_apic_id) - cpu =3D 0; - else - cpu =3D topo_get_cpunr(apic_id); - topo_set_cpuids(cpu, apic_id, acpi_id); - } else { - topo_info.nr_disabled_cpus++; - } + topo_register_apic(apic_id, acpi_id, present); } =20 /** @@ -182,7 +212,7 @@ void __init topology_register_boot_apic( WARN_ON_ONCE(topo_info.boot_cpu_apic_id !=3D BAD_APICID); =20 topo_info.boot_cpu_apic_id =3D apic_id; - topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); + topo_register_apic(apic_id, CPU_ACPIID_INVALID, true); } =20 #ifdef CONFIG_ACPI_HOTPLUG_CPU @@ -335,12 +365,3 @@ static int __init setup_possible_cpus(ch } early_param("possible_cpus", setup_possible_cpus); #endif - -static int __init apic_set_disabled_cpu_apicid(char *arg) -{ - if (!arg || !get_option(&arg, &disabled_cpu_apicid)) - return -EINVAL; - - return 0; -} -early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 192DA8172D for ; Tue, 13 Feb 2024 21:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858359; cv=none; b=HIvFNbMWtvhw9MRk0JK6MwLUc/b7YiL81wjqyPgwkZYZnAelUDVwSTzIgRZEt1FuGPTc2GQ+AoPmIr6bnkOTYxWoh1pDhSECP/oLhMogLvBFd5Wp5X+8TxgE4N7w+ezZE5huh9FFsO9kiFHyzGMVH+2YlzwFUAn8deCx/Mv3JbQ= ARC-Message-Signature: i=1; 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bh=6N/WUbTSEcHybys5fcjgpX9vLfa80Wg5DfRxfxs6bpg=; b=q2OklErlIHp7vOEBa5ADKui58zGpHKITpmjdJml0Rvxc9BhY+u3geJUBx2taztELInOFF1 VrhzbhofB6dE0rDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 16/30] x86/topology: Add a mechanism to track topology via APIC IDs References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:56 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Topology on X86 is determined by the registered APIC IDs and the segmentation information retrieved from CPUID. Depending on the granularity of the provided CPUID information the most fine grained scheme looks like this according to Intel terminology: [PKG][DIEGRP][DIE][TILE][MODULE][CORE][THREAD] Not enumerated domain levels consume 0 bits in the APIC ID. This allows to provide a consistent view at the topology and determine other information precisely like the number of cores in a package on hybrid systems, where the existing assumption that number or cores =3D=3D number of threads / thr= eads per core does not hold. Provide per domain level bitmaps which record the APIC ID split into the domain levels to make later evaluation of domain level specific information simple. This allows to calculate e.g. the logical IDs without any further extra logic. Contrary to the existing registration mechanism this records disabled CPUs, which are subject to later hotplug as well. That's useful for boot time sizing of package or die dependent allocations without using heuristics. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 48 ++++++++++++++++++++++++++++++++++++= +++-- 1 file changed, 46 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -1,5 +1,27 @@ // SPDX-License-Identifier: GPL-2.0-only - +/* + * CPU/APIC topology + * + * The APIC IDs describe the system topology in multiple domain levels. + * The CPUID topology parser provides the information which part of the + * APIC ID is associated to the individual levels: + * + * [PACKAGE][DIEGRP][DIE][TILE][MODULE][CORE][THREAD] + * + * The root space contains the package (socket) IDs. + * + * Not enumerated levels consume 0 bits space, but conceptually they are + * always represented. If e.g. only CORE and THREAD levels are enumerated + * then the DIE, MODULE and TILE have the same physical ID as the PACKAGE. + * + * If SMT is not supported, then the THREAD domain is still used. It then + * has the same physical ID as the CORE domain and is the only child of + * the core domain. + * + * This allows a unified view on the system independent of the enumerated + * domain levels without requiring any conditionals in the code. + */ +#define pr_fmt(fmt) "CPU topo: " fmt #include =20 #include @@ -9,6 +31,8 @@ #include #include =20 +#include "cpu.h" + /* * Map cpu index to physical APIC ID */ @@ -23,6 +47,9 @@ DECLARE_BITMAP(phys_cpu_present_map, MAX /* Used for CPU number allocation and parallel CPU bringup */ u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; =20 +/* Bitmaps to mark registered APICs at each topology domain */ +static struct { DECLARE_BITMAP(map, MAX_LOCAL_APIC); } apic_maps[TOPO_MAX_= DOMAIN] __ro_after_init; + /* * Keep track of assigned, disabled and rejected CPUs. Present assigned * with 1 as CPU #0 is reserved for the boot CPU. @@ -39,6 +66,8 @@ static struct { .real_bsp_apic_id =3D BAD_APICID, }; =20 +#define domain_weight(_dom) bitmap_weight(apic_maps[_dom].map, MAX_LOCAL_A= PIC) + bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -81,6 +110,17 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 +/* + * Convert the APIC ID to a domain level ID by masking out the low bits + * below the domain level @dom. + */ +static inline u32 topo_apicid(u32 apicid, enum x86_topology_domains dom) +{ + if (dom =3D=3D TOPO_SMT_DOMAIN) + return apicid; + return apicid & (UINT_MAX << x86_topo_system.dom_shifts[dom - 1]); +} + static int topo_lookup_cpuid(u32 apic_id) { int i; @@ -151,7 +191,7 @@ static __init bool check_for_real_bsp(u3 =20 static __init void topo_register_apic(u32 apic_id, u32 acpi_id, bool prese= nt) { - int cpu; + int cpu, dom; =20 if (present) { set_bit(apic_id, phys_cpu_present_map); @@ -170,6 +210,10 @@ static __init void topo_register_apic(u3 } else { topo_info.nr_disabled_cpus++; } + + /* Register present and possible CPUs in the domain maps */ + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) + set_bit(topo_apicid(apic_id, dom), apic_maps[dom].map); } =20 /** From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9DF38174F for ; Tue, 13 Feb 2024 21:05:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858361; cv=none; b=PpF+f5aftNVxRuko8ihWhOQhT9Fe5hOKcp0OOMNVwHlfn1ey/IyTDUsjvs6rHLzN3ro3BZeF1HJ7tVp0n1nuHnqv1wFRJSwb3LrXrf31xPyNIARfqzvxVl/Xx+ic3FQJjC/acEJc1eDlJB9eGDsxZnl+rGWPodcD9awomG41FPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858361; c=relaxed/simple; bh=HtpJ3xliOS+lPd3a3JPFOOp0Bo2w5a0wYDFDoURbUEc=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=e/bYG5loZ5CsZnJvGcuH6jKS75OxmdCCOolWQy9ZxihXUQFwlIH2pVX/iPrSt7LIhDYLrZVVxUGfBYHw+8v2I+QYjKs2TPyNuWfRWUpU1LZTog2lS1n6V78PWD9lJTJvnsPucob6LQWwbr6uETjQIL6nj8zTE+jDkTlfPSWnK0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3LmvAtsd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=W/G5phlw; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3LmvAtsd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="W/G5phlw" Message-ID: <20240213210252.462231229@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5JJur1G2I1XboqcLYG+3cvwsrYIK9ClOurubWw6N59g=; b=3LmvAtsdVeujQdo7UnZ7n3gPd2u6LuvJ12D7j7Q/OAex3Tz20+9lnZ9WOjRmvoOKvzSdBy teJdnz7sBDo/GOpIRiwzPeSEa8R+28cvWZAsTxIileQnt3XXMCnrfjQzaEdBmZNmdzKFV6 4eLEPrVkk5MTOiLmfNJOn+H8zXjsGAjK2rFOTjVT0stpD2xMK8UxecOR0ZaB3fRg/dzI1Z yub0+4ismEhZoBPIaWkbe8vUYhGST5vw8XwdUzpSyZy6n1vwvtwqJHoc3Fknc+Ex+y5av9 TLIe8gh3Eqp+N9OoQqNJAroioOZdEBuMiKYudmjh9fFaNKNB2Rn02xK2BKynCQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5JJur1G2I1XboqcLYG+3cvwsrYIK9ClOurubWw6N59g=; b=W/G5phlwoDRR/PczSSP9ln5sld6ZNCEsiZWpdwtNQOP6KaTMl61YhqjIdobHV0NjUB+dWI M/Zg1y/1CmSOt1BQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 17/30] x86/cpu/topology: Reject unknown APIC IDs on ACPI hotplug References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:57 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The topology bitmaps track all possible APIC IDs which have been registered during enumeration. As sizing and further topology information is going to be derived from these bitmaps, reject attempts to hotplug an APIC ID which was not registered during enumeration. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 4 ++++ 1 file changed, 4 insertions(+) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -272,6 +272,10 @@ int topology_hotplug_apic(u32 apic_id, u if (apic_id >=3D MAX_LOCAL_APIC) return -EINVAL; =20 + /* Reject if the APIC ID was not registered during enumeration. */ + if (!test_bit(apic_id, apic_maps[TOPO_SMT_DOMAIN].map)) + return -ENODEV; + cpu =3D topo_lookup_cpuid(apic_id); if (cpu < 0) { if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 147E7823DF for ; Tue, 13 Feb 2024 21:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858362; cv=none; b=Aj479hG8Ug3dIFMwTtKT2ufzLwOCsFIL2MdETsZ9nc333QL/PlaPXt+wALLQLyFR2/0oorY2w56q/YnakJwbiLHRHky5uaWjkQHeExtr4MOd/QUut5OwswGgmBxSbhs6UN1ndb629w0imNABvexydlW2BNo//h6ruLUZ0kwJtD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858362; c=relaxed/simple; bh=EkaARuCY1Em9Ccmsvxie3qQFf3fY3idOKxWU1yQp28c=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ABbUs91JRDPrRcUEw/NsG52ECcrPJ3ZGgEBvtYw2DjNlBHpww2ENyM/8AkLrW3cCI2RV+9TR3s45YqX7nJJW4ur5dBfWxq5Y/4GjXG/blghCoBMJU/T3CDD5b/9eIuDqWxfodwhj7W7mAc6bpb3qVuzM36eXfjuuHj3NYxS/KHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GCS7tKuZ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fj4ze1V0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GCS7tKuZ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fj4ze1V0" Message-ID: <20240213210252.517339971@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=951G8Dsh3krD7dIXNUNj7MpLz5iSrDKvH09osYcSnLQ=; b=GCS7tKuZBZl9EBMgDK6iLgoKKO7vWC+vcY/uj517z24t+1fYw9gp2lR5rFGpuQvCB/M2P8 o6pgT6/44bSu7iaySWfJqYEtCyP5kw4mD/ISWk+nZn+21cG/Msqh73HHJ+JxMmxssMWQNO 3WA4u/bOlxh6iEMU6t/pvXF6vUst9YZg85k/Ub7Cke2tReixCyaPtPAuDuLmLd9RvM6RfR 96m+t1xSohVtc9ysJjuQ/BQZrS26Bm8EQ/LoC83JmQBDgoDnbVHn+bHXqNMRdRsW4en4Hr dXm1APBalOnygu+djXlnmQrdCX14TOrUEEnpyO7MDW5uhksW3CQ+4KO6Hh7SgQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=951G8Dsh3krD7dIXNUNj7MpLz5iSrDKvH09osYcSnLQ=; b=fj4ze1V040bfL2mjSZ5ovOvDHLMa1Hm4aUOmo0OQUhQnJ198VgeC/SjhSCM0fN4HMhS3Qp noRgTi8THE88ezDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 18/30] x86/cpu/topology: Assign hotpluggable CPUIDs during init References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:05:59 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner There is no point in assigning the CPU numbers during ACPI physical hotplug. The number of possible hotplug CPUs is known when the possible map is initialized, so the CPU numbers can be associated to the registered non-present APIC IDs right there. This allows to put more code into the __init section and makes the related data __ro_after_init. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -45,7 +45,7 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_a DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC) __read_mostly; =20 /* Used for CPU number allocation and parallel CPU bringup */ -u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; +u32 cpuid_to_apicid[] __ro_after_init =3D { [0 ... NR_CPUS - 1] =3D BAD_AP= ICID, }; =20 /* Bitmaps to mark registered APICs at each topology domain */ static struct { DECLARE_BITMAP(map, MAX_LOCAL_APIC); } apic_maps[TOPO_MAX_= DOMAIN] __ro_after_init; @@ -60,7 +60,7 @@ static struct { unsigned int nr_rejected_cpus; u32 boot_cpu_apic_id; u32 real_bsp_apic_id; -} topo_info __read_mostly =3D { +} topo_info __ro_after_init =3D { .nr_assigned_cpus =3D 1, .boot_cpu_apic_id =3D BAD_APICID, .real_bsp_apic_id =3D BAD_APICID, @@ -133,7 +133,7 @@ static int topo_lookup_cpuid(u32 apic_id return -ENODEV; } =20 -static int topo_get_cpunr(u32 apic_id) +static __init int topo_get_cpunr(u32 apic_id) { int cpu =3D topo_lookup_cpuid(apic_id); =20 @@ -149,8 +149,6 @@ static void topo_set_cpuids(unsigned int early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; #endif - cpuid_to_apicid[cpu] =3D apic_id; - set_cpu_possible(cpu, true); set_cpu_present(cpu, true); =20 @@ -206,6 +204,8 @@ static __init void topo_register_apic(u3 cpu =3D 0; else cpu =3D topo_get_cpunr(apic_id); + + cpuid_to_apicid[cpu] =3D apic_id; topo_set_cpuids(cpu, apic_id, acpi_id); } else { topo_info.nr_disabled_cpus++; @@ -277,12 +277,9 @@ int topology_hotplug_apic(u32 apic_id, u return -ENODEV; =20 cpu =3D topo_lookup_cpuid(apic_id); - if (cpu < 0) { - if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) - return -ENOSPC; + if (cpu < 0) + return -ENOSPC; =20 - cpu =3D topo_assign_cpunr(apic_id); - } set_bit(apic_id, phys_cpu_present_map); topo_set_cpuids(cpu, apic_id, acpi_id); return cpu; @@ -353,6 +350,7 @@ void __init topology_init_possible_cpus( unsigned int disabled =3D topo_info.nr_disabled_cpus; unsigned int total =3D assigned + disabled; unsigned int cpu, allowed =3D 1; + u32 apicid; =20 if (!restrict_to_up()) { if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { @@ -381,8 +379,17 @@ void __init topology_init_possible_cpus( init_cpu_present(cpumask_of(0)); init_cpu_possible(cpumask_of(0)); =20 + /* Assign CPU numbers to non-present CPUs */ + for (apicid =3D 0; disabled; disabled--, apicid++) { + apicid =3D find_next_andnot_bit(apic_maps[TOPO_SMT_DOMAIN].map, phys_cpu= _present_map, + MAX_LOCAL_APIC, apicid); + if (apicid >=3D MAX_LOCAL_APIC) + break; + cpuid_to_apicid[topo_info.nr_assigned_cpus++] =3D apicid; + } + for (cpu =3D 0; cpu < allowed; cpu++) { - u32 apicid =3D cpuid_to_apicid[cpu]; + apicid =3D cpuid_to_apicid[cpu]; =20 set_cpu_possible(cpu, true); From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DAE839E7 for ; Tue, 13 Feb 2024 21:06:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858364; cv=none; b=CwtjeUYKI4qNC48koSkRadENcqefIhsZdiVyCRWrc1MksqvYHZHNJ/OwnlhOSkHWkqtLEDLNQUui8tlWt69vqeaj856e2bkMSy21bd160PVk35m/Fdx1+pS89aNJyommLtMU16iqTsQuDbos5/cXZzK6gbRMSjSTjs9GRwc/2fs= ARC-Message-Signature: i=1; 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bh=l5IIheic7HTdLbtL8FePLNCYvWctux8lTDROKkU5h0g=; b=a1Vsgm7b2KoILqZlz/V01LMAGTu+EopHn2bXvBSK5ls0/E3HO1hQG+Dc294cj3B67tmfnk WaGUvLvojc1mH2DQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 19/30] x86/xen/smp_pv: Count number of vCPUs early References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:00 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner XEN/PV has a completely broken vCPU enumeration scheme, which just works by chance and provides zero topology information. Each vCPU ends up being a single core package. Dom0 provides MADT which can be used for topology information, but that table is the unmodified host table, which means that there can be more CPUs registered than the number of vCPUs XEN provides for the dom0 guest. DomU does not have ACPI and both rely on counting the possible vCPUs via an hypercall. To prepare for using CPUID topology information either via MADT or via fake APIC IDs count the number of possible CPUs during early boot and adjust nr_cpu_ids() accordingly. Signed-off-by: Thomas Gleixner --- arch/x86/xen/enlighten_pv.c | 3 +++ arch/x86/xen/smp.h | 2 ++ arch/x86/xen/smp_pv.c | 14 ++++++++++++++ 3 files changed, 19 insertions(+) --- --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -200,6 +200,9 @@ static void __init xen_pv_init_platform( xen_set_mtrr_data(); else mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); + + /* Adjust nr_cpu_ids before "enumeration" happens */ + xen_smp_count_cpus(); } =20 static void __init xen_pv_guest_late_init(void) --- a/arch/x86/xen/smp.h +++ b/arch/x86/xen/smp.h @@ -19,6 +19,7 @@ extern void xen_smp_intr_free(unsigned i int xen_smp_intr_init_pv(unsigned int cpu); void xen_smp_intr_free_pv(unsigned int cpu); =20 +void xen_smp_count_cpus(void); void xen_smp_cpus_done(unsigned int max_cpus); =20 void xen_smp_send_reschedule(int cpu); @@ -44,6 +45,7 @@ static inline int xen_smp_intr_init_pv(u return 0; } static inline void xen_smp_intr_free_pv(unsigned int cpu) {} +static inline void xen_smp_count_cpus(void) { } #endif /* CONFIG_SMP */ =20 #endif --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -411,6 +411,20 @@ static irqreturn_t xen_irq_work_interrup return IRQ_HANDLED; } =20 +void __init xen_smp_count_cpus(void) +{ + unsigned int cpus; + + for (cpus =3D 0; cpus < nr_cpu_ids; cpus++) { + if (HYPERVISOR_vcpu_op(VCPUOP_is_up, cpus, NULL) < 0) + break; + } + + pr_info("Xen PV: Detected %u vCPUS\n", cpus); + if (cpus < nr_cpu_ids) + set_nr_cpu_ids(cpus); +} + static const struct smp_ops xen_smp_ops __initconst =3D { .smp_prepare_boot_cpu =3D xen_pv_smp_prepare_boot_cpu, .smp_prepare_cpus =3D xen_pv_smp_prepare_cpus, From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2875383A1E for ; Tue, 13 Feb 2024 21:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858365; cv=none; b=s5B6kJ2tBDxnVx5oZZibZVt0EPpvL0vZBhTeYbtXCb13SQ9Q7LC5WjZAlTWLhy2hs2MSKWePYxQ5OFzcIZm1Is0iQyfuHtHu08iZYtmeyxIb7nFi23YmmHHOVFAs9koqEMEE4wuKMyYfuKFLtg1jxQ11SHphf7wE08J05165xBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858365; c=relaxed/simple; bh=F2aXhX15QFP6QhNyaG/FX2TOG0GF8KCwsOMK8hzmTZI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=VxNaI5/ShbyV/UpnKPHFrFn3oacYb8rnSmias5nKLXVi5oLd47KmFPP4HgRg8KpW++WubBU+C4sWJnL4FGGeT/4SnSPRmCjuPdMKptEJl46q3j2Sa2Ur6T4lxx07qFefElvTSXVYN09DIyeAWIhNhvoNVUrqh+e2umnTZIcbwx0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=w1pnvsGf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iEtxKqWa; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="w1pnvsGf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iEtxKqWa" Message-ID: <20240213210252.626195405@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=d+71tkpEB4OcuO512PE3kL/Lm9tKC8Y2URct1lCVA2Y=; b=w1pnvsGf7y6P/B8MeW2P5V54ejWX3pUIdqF1aOi61mN1kYsQpwEQdGXXpBMzBKx7n30BiD y5aW4MDPI8x7A29iHMmrTlknEFkRre9wIXVuWgdPWccIQtBN7tKOuG5GtkzhnbgbwAYvm0 QzfNm9kaXe0Q7OuL/Y9BAzhLvj8YlD1EINsMTSm4bew/zjFJ9pM0TsbNhMQ9jXsb8VuIpf XJAS26zU64rXfJJhuE5xXol+7h5tgWkHVqHsJZernc+sCDWg/LrcBt3UO91e9rgCuJuY5o 1Hk2gG67PRDCfp51lwGIfqIXJpv6wslbd/5yX6qirPeKOTDB5msdL8GaO7WFZA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=d+71tkpEB4OcuO512PE3kL/Lm9tKC8Y2URct1lCVA2Y=; b=iEtxKqWa3vMIPnvdqpl1UtY0TZFXj35OHR/FknPAGEdxoUYbVDuH2lBVRb/N94Ov9xu3rL EqIQ2Sc/3cs/zbDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 20/30] x86/cpu/topology: Let XEN/PV use topology from CPUID/MADT References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:02 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner It turns out that XEN/PV Dom0 has halfways usable CPUID/MADT enumeration except that it cannot deal with CPUs which are enumerated as disabled in MADT. DomU has no MADT and provides at least rudimentary topology information in CPUID leaves 1 and 4. For both it's important that there are not more possible Linux CPUs than vCPUs provided by the hypervisor. As this is ensured by counting the vCPUs before enumeration happens: - lift the restrictions in the CPUID evaluation and the MADT parser - Utilize MADT registration for Dom0 - Keep the fake APIC ID registration for DomU - Fix the XEN APIC fake so the readout of the local APIC ID works for Dom0 via the hypercall and for DomU by returning the registered fake APIC IDs. With that the XEN/PV fake approximates usefulness. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/acpi/boot.c | 25 ++++++++----------------- arch/x86/kernel/cpu/topology_common.c | 2 +- arch/x86/xen/apic.c | 14 +++++++------- arch/x86/xen/smp_pv.c | 13 ++++++++----- 4 files changed, 24 insertions(+), 30 deletions(-) --- --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -23,8 +23,6 @@ #include #include =20 -#include - #include #include #include @@ -166,12 +164,6 @@ static int __init acpi_parse_madt(struct return 0; } =20 -static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) -{ - if (!xen_pv_domain()) - topology_register_apic(apic_id, acpi_id, present); -} - static bool __init acpi_is_processor_usable(u32 lapic_flags) { if (lapic_flags & ACPI_MADT_ENABLED) @@ -233,7 +225,7 @@ acpi_parse_x2apic(union acpi_subtable_he return 0; } =20 - acpi_register_lapic(apic_id, processor->uid, enabled); + topology_register_apic(apic_id, processor->uid, enabled); #else pr_warn("x2apic entry ignored\n"); #endif @@ -268,9 +260,9 @@ acpi_parse_lapic(union acpi_subtable_hea * to not preallocating memory for all NR_CPUS * when we use CPU hotplug. */ - acpi_register_lapic(processor->id, /* APIC ID */ - processor->processor_id, /* ACPI ID */ - processor->lapic_flags & ACPI_MADT_ENABLED); + topology_register_apic(processor->id, /* APIC ID */ + processor->processor_id, /* ACPI ID */ + processor->lapic_flags & ACPI_MADT_ENABLED); =20 has_lapic_cpus =3D true; return 0; @@ -288,9 +280,9 @@ acpi_parse_sapic(union acpi_subtable_hea =20 acpi_table_print_madt_entry(&header->common); =20 - acpi_register_lapic((processor->id << 8) | processor->eid,/* APIC ID */ - processor->processor_id, /* ACPI ID */ - processor->lapic_flags & ACPI_MADT_ENABLED); + topology_register_apic((processor->id << 8) | processor->eid,/* APIC ID */ + processor->processor_id, /* ACPI ID */ + processor->lapic_flags & ACPI_MADT_ENABLED); =20 return 0; } @@ -1090,8 +1082,7 @@ static int __init early_acpi_parse_madt_ return count; } =20 - if (!xen_pv_domain()) - register_lapic_address(acpi_lapic_addr); + register_lapic_address(acpi_lapic_addr); =20 return count; } --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -77,7 +77,7 @@ static bool fake_topology(struct topo_sc topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); topology_set_dom(tscan, TOPO_CORE_DOMAIN, 0, 1); =20 - return tscan->c->cpuid_level < 1 || xen_pv_domain(); + return tscan->c->cpuid_level < 1; } =20 static void parse_topology(struct topo_scan *tscan, bool early) --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -43,20 +43,20 @@ static u32 xen_apic_read(u32 reg) struct xen_platform_op op =3D { .cmd =3D XENPF_get_cpuinfo, .interface_version =3D XENPF_INTERFACE_VERSION, - .u.pcpu_info.xen_cpuid =3D 0, }; - int ret; - - /* Shouldn't need this as APIC is turned off for PV, and we only - * get called on the bootup processor. But just in case. */ - if (!xen_initial_domain() || smp_processor_id()) - return 0; + int ret, cpu; =20 if (reg =3D=3D APIC_LVR) return 0x14; if (reg !=3D APIC_ID) return 0; =20 + cpu =3D smp_processor_id(); + if (!xen_initial_domain()) + return cpu ? cpuid_to_apicid[cpu] << 24 : 0; + + op.u.pcpu_info.xen_cpuid =3D cpu; + ret =3D HYPERVISOR_platform_op(&op); if (ret) op.u.pcpu_info.apic_id =3D BAD_APICID; --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -156,11 +156,9 @@ static void __init xen_pv_smp_config(voi =20 topology_register_boot_apic(apicid++); =20 - for (i =3D 1; i < nr_cpu_ids; i++) { - if (HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL) < 0) - break; + for (i =3D 1; i < nr_cpu_ids; i++) topology_register_apic(apicid++, CPU_ACPIID_INVALID, true); - } + /* Pretend to be a proper enumerated system */ smp_found_config =3D 1; } @@ -451,5 +449,10 @@ void __init xen_smp_init(void) /* Avoid searching for BIOS MP tables */ x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; - x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; + + /* XEN/PV Dom0 has halfways sane topology information via CPUID/MADT */ + if (xen_initial_domain()) + x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; + else + x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC5684FC2 for ; Tue, 13 Feb 2024 21:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858368; cv=none; b=FdfiQN8dw3WN9Y2IilcwN1RAI/ICwnfCvs29suQyZqjuvmjhYJJlt3fKLXR8RIBLeJG7kuAzF4WwtCh4TGKEgSMSvFPWhgF55Y8W0oi1y4Mt2uyvmdkZG/1WeE1Sc2m9ZocobJj+vKNrQEjA5PpQJenZisZYeFO2QT/A2tP1blc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858368; c=relaxed/simple; bh=/gji1ltnd85K3RSSeO+xm2HSGttvW35bsHvRZmT3Yzs=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=d4ixNdsP0fmYgkCTo/hzT3cU0rT+3BvavDrM3TzdoEoZDyagxcwsoB4pD3dEdQ2Btp+eCSIAJHf4mNIDtySAZUTBfHQEnfBvZnk+N421RucesgdDy93QS0G4tjV4QzWs7tH6PErXaoElWyiIn1Rnuo064tg5uj0ss4dR39YeT6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=AMrmpUiV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eGiuLV6Z; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="AMrmpUiV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eGiuLV6Z" Message-ID: <20240213210252.681709880@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C/JTSxodC/ubcWBLJsrbomU+eWq3u3+UpltNmhF7/sw=; b=AMrmpUiVYBRC6xPWK+9B9+ry+7nZ2eXH4opBdTZ/o/8Vtqi5o1cgMNr8QqF7LpuRXqhCWQ I67AU3k4OPVwylN/UKs5L+s0IOwva7uelIFZ4G/b1V6aCfMxlGd5F40xwAUKb2gcqjjXMn g4bWvAlSHLbYC1njQbrxrJN6rLiLULf+uWbzmBmHx9SlcvWH1pPsmI6K8+a30PBIfL9vui C7KOHMCnty0nnBf/HlOq+XgHA4PHZAWreej0PLcqbQI2UaV5Pn49K1lCu7wydKxyY/xB2g dJ2vavpRFXJAwBpEjAPaMQV8qpfsI3ACJUifPZqvVNPnqonE9NQFX2lBra1gPQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C/JTSxodC/ubcWBLJsrbomU+eWq3u3+UpltNmhF7/sw=; b=eGiuLV6ZSs/Vi90K3RP76sspvIqGx0AkPUB82ycC+rH2B1BlZJOdf+J35fbqLgphL5/9kw mk8tTbQhoXE0SdBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 21/30] x86/cpu/topology: Use topology bitmaps for sizing References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:03 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Now that all possible APIC IDs are tracked in the topology bitmaps, its trivial to retrieve the real information from there. This gets rid of the guesstimates for the maximal packages and dies per package as the actual numbers can be determined before a single AP has been brought up. The number of SMT threads can now be determined correctly from the bitmaps in all situations. Up to now a system which has SMT disabled in the BIOS will still claim that it is SMT capable, because the lowest APIC ID bit is reserved for that and CPUID leaf 0xb/0x1f still enumerates the SMT domain accordingly. By calculating the bitmap weights of the SMT and the CORE domain and setting them into relation the SMT disabled in BIOS situation reports correctly that the system is not SMT capable. It also handles the situation correctly when a hybrid systems boot CPU does not have SMT as it takes the SMT capability of the APs fully into account. Signed-off-by: Thomas Gleixner --- V3: Fix the SMT capabable calculation - Rui --- arch/x86/include/asm/smp.h | 3 +-- arch/x86/include/asm/topology.h | 23 ++++++++++++----------- arch/x86/kernel/cpu/common.c | 9 ++++++--- arch/x86/kernel/cpu/debugfs.c | 2 +- arch/x86/kernel/cpu/topology.c | 20 +++++++++++++++++++- arch/x86/kernel/cpu/topology_common.c | 24 ------------------------ arch/x86/kernel/smpboot.c | 16 ---------------- arch/x86/xen/smp.c | 2 -- 8 files changed, 39 insertions(+), 60 deletions(-) --- --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -8,7 +8,7 @@ #include #include =20 -extern int smp_num_siblings; +extern unsigned int smp_num_siblings; =20 DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); @@ -109,7 +109,6 @@ void cpu_disable_common(void); void native_smp_prepare_boot_cpu(void); void smp_prepare_cpus_common(void); void native_smp_prepare_cpus(unsigned int max_cpus); -void calculate_max_logical_packages(void); void native_smp_cpus_done(unsigned int max_cpus); int common_cpu_up(unsigned int cpunum, struct task_struct *tidle); int native_kick_ap(unsigned int cpu, struct task_struct *tidle); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -143,7 +143,18 @@ extern const struct cpumask *cpu_cluster =20 #define topology_amd_node_id(cpu) (cpu_data(cpu).topo.amd_node_id) =20 -extern unsigned int __max_die_per_package; +extern unsigned int __max_dies_per_package; +extern unsigned int __max_logical_packages; + +static inline unsigned int topology_max_packages(void) +{ + return __max_logical_packages; +} + +static inline unsigned int topology_max_die_per_package(void) +{ + return __max_dies_per_package; +} =20 #ifdef CONFIG_SMP #define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) @@ -152,14 +163,6 @@ extern unsigned int __max_die_per_packag #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) #define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) =20 -extern unsigned int __max_logical_packages; -#define topology_max_packages() (__max_logical_packages) - -static inline int topology_max_die_per_package(void) -{ - return __max_die_per_package; -} - extern int __max_smt_threads; =20 static inline int topology_max_smt_threads(void) @@ -193,13 +196,11 @@ static inline bool topology_is_primary_t } =20 #else /* CONFIG_SMP */ -#define topology_max_packages() (1) static inline int topology_update_package_map(unsigned int apicid, unsigned int cpu) { retur= n 0; } static inline int topology_update_die_map(unsigned int dieid, unsigned int cpu) { return 0; } static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } -static inline int topology_max_die_per_package(void) { return 1; } static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } static inline unsigned int topology_amd_nodes_per_pkg(void) { return 0; }; --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -73,11 +73,14 @@ u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ -int smp_num_siblings =3D 1; +unsigned int smp_num_siblings __ro_after_init =3D 1; EXPORT_SYMBOL(smp_num_siblings); =20 -unsigned int __max_die_per_package __read_mostly =3D 1; -EXPORT_SYMBOL(__max_die_per_package); +unsigned int __max_dies_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_dies_per_package); + +unsigned int __max_logical_packages __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_logical_packages); =20 static struct ppin_info { int feature; --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -29,7 +29,7 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); seq_printf(m, "max_cores: %u\n", c->x86_max_cores); - seq_printf(m, "max_die_per_pkg: %u\n", __max_die_per_package); + seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); return 0; } --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -348,8 +348,8 @@ void __init topology_init_possible_cpus( { unsigned int assigned =3D topo_info.nr_assigned_cpus; unsigned int disabled =3D topo_info.nr_disabled_cpus; + unsigned int cnta, cntb, cpu, allowed =3D 1; unsigned int total =3D assigned + disabled; - unsigned int cpu, allowed =3D 1; u32 apicid; =20 if (!restrict_to_up()) { @@ -372,6 +372,24 @@ void __init topology_init_possible_cpus( total_cpus =3D allowed; set_nr_cpu_ids(allowed); =20 + cnta =3D domain_weight(TOPO_PKG_DOMAIN); + cntb =3D domain_weight(TOPO_DIE_DOMAIN); + __max_logical_packages =3D cnta; + __max_dies_per_package =3D 1U << (get_count_order(cntb) - get_count_order= (cnta)); + + pr_info("Max. logical packages: %3u\n", cnta); + pr_info("Max. logical dies: %3u\n", cntb); + pr_info("Max. dies per package: %3u\n", __max_dies_per_package); + + cnta =3D domain_weight(TOPO_CORE_DOMAIN); + cntb =3D domain_weight(TOPO_SMT_DOMAIN); + /* + * Can't use order delta here as order(cnta) can be equal + * order(cntb) even if cnta !=3D cntb. + */ + smp_num_siblings =3D DIV_ROUND_UP(cntb, cnta); + pr_info("Max. threads per core: %3u\n", smp_num_siblings); + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -196,16 +196,6 @@ void cpu_parse_topology(struct cpuinfo_x tscan.dom_shifts[dom], x86_topo_system.dom_shifts[dom]); } =20 - /* Bug compatible with the existing parsers */ - if (tscan.dom_ncpus[TOPO_SMT_DOMAIN] > smp_num_siblings) { - if (system_state =3D=3D SYSTEM_BOOTING) { - pr_warn_once("CPU%d: SMT detected and enabled late\n", cpu); - smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; - } else { - pr_warn_once("CPU%d: SMT detected after init. Too late!\n", cpu); - } - } - topo_set_ids(&tscan); topo_set_max_cores(&tscan); } @@ -232,20 +222,6 @@ void __init cpu_init_topology(struct cpu topo_set_max_cores(&tscan); =20 /* - * Bug compatible with the existing code. If the boot CPU does not - * have SMT this ends up with one sibling. This needs way deeper - * changes further down the road to get it right during early boot. - */ - smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; - - /* - * Neither it's clear whether there are as many dies as the APIC - * space indicating die level is. But assume that the actual number - * of CPUs gives a proper indication for now to stay bug compatible. - */ - __max_die_per_package =3D tscan.dom_ncpus[TOPO_DIE_DOMAIN] / - tscan.dom_ncpus[TOPO_DIE_DOMAIN - 1]; - /* * AMD systems have Nodes per package which cannot be mapped to * APIC ID. */ --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -139,8 +139,6 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct .phys_die_id =3D U32_MAX, }; =20 -unsigned int __max_logical_packages __read_mostly; -EXPORT_SYMBOL(__max_logical_packages); static unsigned int logical_packages __read_mostly; static unsigned int logical_die __read_mostly; =20 @@ -1267,24 +1265,10 @@ void __init native_smp_prepare_boot_cpu( native_pv_lock_init(); } =20 -void __init calculate_max_logical_packages(void) -{ - int ncpus; - - /* - * Today neither Intel nor AMD support heterogeneous systems so - * extrapolate the boot cpu's data to all packages. - */ - ncpus =3D cpu_data(0).booted_cores * topology_max_smt_threads(); - __max_logical_packages =3D DIV_ROUND_UP(total_cpus, ncpus); - pr_info("Max logical packages: %u\n", __max_logical_packages); -} - void __init native_smp_cpus_done(unsigned int max_cpus) { pr_debug("Boot done\n"); =20 - calculate_max_logical_packages(); build_sched_topology(); nmi_selftest(); impress_friends(); --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -123,8 +123,6 @@ void __init xen_smp_cpus_done(unsigned i { if (xen_hvm_domain()) native_smp_cpus_done(max_cpus); - else - calculate_max_logical_packages(); } =20 void xen_smp_send_reschedule(int cpu) From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B488A84FD8 for ; Tue, 13 Feb 2024 21:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858368; cv=none; b=E87GPmvlOwNGG4O6cbBO2MaUEWD+80Ehy4KmsA31IV1cqVJCofw4ouQwg6sy2E+gt+daT4moyjMYZH1kkGyzODU6prcjRym5HX9YSLGM5jHSUolAV/Ngluw/37Ap+YFdZ8CaJzPZZGKm9nNYSwt1tv1/jz+D1rph08cSo9ulDN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858368; c=relaxed/simple; bh=f7TjAfRNJePRvBVh60Mlq3WaXOIueC9RaU3KBd5vNSQ=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ua+/FUqpGh3ENO6E1U1NyMJtDYJKDMLBIf2AVzxYlNTed53zeXoLg/+HahnCUo++WsXzGPAJG5AoOeW40SKajlZJVS3l9z+nojCCykkeh+MnTlqIPxmXEc5iuM33+Qr0ye9Fo3CQ23KGv5CMdwc5nxK52q6Y+TkklBCvGbazVB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GY2mq/NF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ISgqYSJn; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GY2mq/NF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ISgqYSJn" Message-ID: <20240213210252.736104257@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858365; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TKbUBcNH0EQ/gLK3fnpU18ylL1ck8LsuH2l84iqWPqs=; b=GY2mq/NFSPH+GSw6gAmOmCoE9kHYCGw4vM72bnpYhTyDS3u1MHINPu/krM8Jgqc2PmZ9R9 xBxOT10RrZYSfYiZ39GK4gdvoGjd8zud5fn+Bhccf0dKSQqBwLLAHw8BU8m1VOjDmIILFS Maf4nQ7m47HrA0nNfa/zpCgBbDoRqZQNKf0mwtWSSb2NOuTVyxOwYPqjn/U0dktUFLqSgS kycW7Q2XO2FvZQpoPrbPdgMl5qjUEj7yBm8ofV2K2RJ5l1oBdi9IqqfAisbCDwxMU5d9+A mjIEDB9AT0eLmaLyWcYzMY5bXbr9rtnZyLjFZjCc7WlKSVrNqJqokvmMPWLxeA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858365; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TKbUBcNH0EQ/gLK3fnpU18ylL1ck8LsuH2l84iqWPqs=; b=ISgqYSJnb4ORWJzaBcbYql6oOdFC9OeW55CfrtR04MA+nvxYVpoxTfG1/Dqa+VQTCDYjUF 3CGlPAMSK89T5mAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 22/30] x86/cpu/topology: Mop up primary thread mask handling References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:05 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The early initcall to initialize the primary thread mask is not longer required because topology_init_possible_cpus() can mark primary threads correctly when initializing the possible and present map as the number of SMT threads is already determined correctly. The XENPV workaround is not longer required because XENPV now registers fake APIC IDs which will just work like any other enumeration. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -82,30 +82,6 @@ static void cpu_mark_primary_thread(unsi if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } - -/* - * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid - * during early boot. Initialize the primary thread mask before SMP - * bringup. - */ -static int __init smp_init_primary_thread_mask(void) -{ - unsigned int cpu; - - /* - * XEN/PV provides either none or useless topology information. - * Pretend that all vCPUs are primary threads. - */ - if (xen_pv_domain()) { - cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); - return 0; - } - - for (cpu =3D 0; cpu < topo_info.nr_assigned_cpus; cpu++) - cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); - return 0; -} -early_initcall(smp_init_primary_thread_mask); #else static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif @@ -151,9 +127,6 @@ static void topo_set_cpuids(unsigned int #endif set_cpu_possible(cpu, true); set_cpu_present(cpu, true); - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apic_id); } =20 static __init bool check_for_real_bsp(u32 apic_id) @@ -276,6 +249,7 @@ int topology_hotplug_apic(u32 apic_id, u =20 set_bit(apic_id, phys_cpu_present_map); topo_set_cpuids(cpu, apic_id, acpi_id); + cpu_mark_primary_thread(cpu, apic_id); return cpu; } =20 @@ -411,6 +385,7 @@ void __init topology_init_possible_cpus( if (apicid =3D=3D BAD_APICID) continue; =20 + cpu_mark_primary_thread(cpu, apicid); set_cpu_present(cpu, test_bit(apicid, phys_cpu_present_map)); } } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E82D8527D for ; Tue, 13 Feb 2024 21:06:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858369; cv=none; b=eF5Nm7Kj3oIvvyr4ifqLlsUuSLkkldcSduHWLtddrCb/LUb0T8KSFEWlkXF7Wj4ki/pIcyhndikW7C1JtnlPtaYmxFrQJYnE+RSc9t6BOmjuZD33flFtefn5DJKRhpMezhyvyUROeOg+CLcCEZWdIWkwXKGHohR87fv8wvJGrTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858369; c=relaxed/simple; bh=GELcpW9HVBoRzmyXJvaQUEiRKMX+NhRhw6z94yRJV98=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ZJoXhSBxUa33Rx6G1hKbJc5fRdFMSzuO5Vh83ZKddrtbRqflvMH0DTA/3dEpwHZKDUikG0rrccSUu9AqPpP1+z1kYFHOnyckSJJC26ksol7BFSgfu2rX/ONEVHl5Yb5R0TwNTqCbU1jUU4/77POZKtfOkGetYqQ+EdTGdhCxeac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oPx1XJxS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hmRhfhej; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oPx1XJxS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hmRhfhej" Message-ID: <20240213210252.791176581@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=h5Fk2rHdvsa9daqL+lfmpiGhGHrHMczyPypdwtxy44M=; b=oPx1XJxS1VsEi9t/HVHvfVMWijw/db3doezwnh5CP26KnNRz4mcL+nH+zhg7LlksM40fDM Nf8nOn8W5hdxTf0BGzqCof/j6aa5m3z9lv7kpPQS01RAbHUBMhuY5ai1Iy9OXmUk/2PsrQ o7s7cHIOv85SM2wY6TDOuaG+4+OT4JjcZFpj5+PKHgsiC1ih1dsie+6mk3gRgYUjmSlHEs TcFnSITavX9Ip/wwxAaY2NhkPqR1JxfTrSL+RSiff81gIQ5gP4rW0IuvMR79za2j8bGfLS fWAMn3N1fxJZ5m+2fgTpfh/NFZlq6NJ2BmCXVThNn2MK3uKqVey45h89I24TjQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=h5Fk2rHdvsa9daqL+lfmpiGhGHrHMczyPypdwtxy44M=; b=hmRhfhejWNIOcYm5dSBmxst5vZzsUvoD3B4sy5hx/yqg361s9+Yuwi8/9NHytueP6Lt2z0 fM/5cYIra2odj2AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 23/30] x86/cpu/topology: Simplify cpu_mark_primary_thread() References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:06 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No point in creating a mask via fls(). smp_num_siblings is guaranteed to be a power of 2. So just using (smp_num_siblings - 1) has the same effect. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -76,10 +76,7 @@ bool arch_match_cpu_phys_id(int cpu, u64 #ifdef CONFIG_SMP static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { - /* Isolate the SMT bit(s) in the APICID and check for 0 */ - u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; - - if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) + if (!(apicid & (smp_num_siblings - 1))) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } #else From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E71558562F for ; Tue, 13 Feb 2024 21:06:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858371; cv=none; b=GVhuYRMm3Fxec2SzpDeQbY7Msfi1QUaormJp37i3u/ks8s3mlWSkKTKMFsjlddTH7QTwhR1TeH1jeud2QbwapDXYdzq2LDUKd+0KoHxL7K0Hb0A14CpI2FwoiO2NDp4DNymXq/j+054NPLRQYRXRLvDDM++ldlSweWusVS9olcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858371; c=relaxed/simple; bh=dzZg/qbHJvAs2UTwP+S3YTraj0xonaKUEUGBDYOq4Ys=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=hO7KoINDvHMilB8U+zE4chCXRkRgGLBwQ7A5pEbmOMcOetzP7GH2agG0nudYQ8ZwYHiGoO3mLZdkyRO+5EREIgZaL6vNIM8zGq/tAlbRrURSLSYvh6Hr4HnhG3MBR0AZavyzJXRntmfwoXzbRQWZsR0fUlm9Ok64KLIJJ7QMUr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0JUjk1Nb; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=pKyhgdLo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0JUjk1Nb"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="pKyhgdLo" Message-ID: <20240213210252.846136196@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VSt0e/pJgXOuwhWfq+S+zmb74FzHu/CZzfV9Bz+FkzQ=; b=0JUjk1NbcZdKyEcWK408QIMwYUEaGUYAKKNJ74i87P8E8w6szqsv7OePZ3tcOXQ94++mbV eDbPHX75r9nyjMFwpD2GZiQqJxDfZfudq+iEtNggN5pHOci/VKhTOJgKtZ7rm9NmUQHsb2 XqU8bbKeZ3dA0iJXH9xlflyBcN2zMY7kDrpKQZ+Dzi1vSi7i9698g/FF9PEOSycCsuPRO3 BwQLTgCfmszEhtfHRa/EJEX/RstNFKEotR1xE901wAxx8YetfATEr+XbCuKQd5B5PEAe/1 XgtCnnWgJUCYECm7Xzz7RjY81FX54JZcaD1PjTPfwBSbj5yXXdi6UKZ2TExmoQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VSt0e/pJgXOuwhWfq+S+zmb74FzHu/CZzfV9Bz+FkzQ=; b=pKyhgdLod3f79cGRjJsb3nBPliUbF3C9bSowopxEVo5WMqdabcozXoC10wIa7UCUQno3M3 F4zfClkK9ZstF8AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 24/30] x86/cpu/topology: Provide logical pkg/die mapping References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:07 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner With the topology bitmaps in place the logical package and die IDs can trivially be retrieved by determining the bitmap weight of the relevant topology domain level up to and including the physical ID in question. Provide a function to that effect. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/topology.h | 9 +++++++++ arch/x86/kernel/cpu/topology.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) --- --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -156,6 +156,15 @@ static inline unsigned int topology_max_ return __max_dies_per_package; } =20 +#ifdef CONFIG_X86_LOCAL_APIC +int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level= ); +#else +static inline int topology_get_logical_id(u32 apicid, enum x86_topology_do= mains at_level) +{ + return 0; +} +#endif + #ifdef CONFIG_SMP #define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu)) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -230,6 +230,34 @@ void __init topology_register_boot_apic( topo_register_apic(apic_id, CPU_ACPIID_INVALID, true); } =20 +/** + * topology_get_logical_id - Retrieve the logical ID at a given topology d= omain level + * @apicid: The APIC ID for which to lookup the logical ID + * @at_level: The topology domain level to use + * + * @apicid must be a full APIC ID, not the normalized variant. It's valid = to have + * all bits below the domain level specified by @at_level to be clear. So = both + * real APIC IDs and backshifted normalized APIC IDs work correctly. + * + * Returns: + * - >=3D 0: The requested logical ID + * - -ERANGE: @apicid is out of range + * - -ENODEV: @apicid is not registered + */ +int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level) +{ + /* Remove the bits below @at_level to get the proper level ID of @apicid = */ + unsigned int lvlid =3D topo_apicid(apicid, at_level); + + if (lvlid >=3D MAX_LOCAL_APIC) + return -ERANGE; + if (!test_bit(lvlid, apic_maps[at_level].map)) + return -ENODEV; + /* Get the number of set bits before @lvlid. */ + return bitmap_weight(apic_maps[at_level].map, lvlid); +} +EXPORT_SYMBOL_GPL(topology_get_logical_id); + #ifdef CONFIG_ACPI_HOTPLUG_CPU /** * topology_hotplug_apic - Handle a physical hotplugged APIC after boot From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1417B85928 for ; Tue, 13 Feb 2024 21:06:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858372; cv=none; b=LDmw+kBVuiDAmIWHUInebZIQiw3yLzIAmHzmQhul9RaOtJ6uH8OCvBHLmfYLMprzhV0NzceIaC2iy8DeckoYcXXT7xR2zDpPqKv2viarCmuAbkvvB9Pg6/zQaVxUtuDWrQROeDF3tIkgdPOTNOXx3yBwbZ2LvPb5pf4LTgmB/q0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858372; c=relaxed/simple; bh=S+zrw2iNRe5XUZyTaQTtsAmH60QnO8xwEi9zsCOtap0=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=jYGyrPnblKBhPrUolryE/LMwPsRxTnIn6OYlrue5vJrj6my42xICFawK3ILQgcUHgMownxuaLbJQoqjoJ3tO+DzXh9++VxojSkEfKpcYME7k0NthPPfCceca3e7EL+R0+3c45Ga6xl8qXTOko16Gc5LDQXXj8IdgWTLvg6nzoAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hSAB2cUp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dNaSQ87A; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hSAB2cUp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dNaSQ87A" Message-ID: <20240213210252.901865302@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2gNN8N211J8r3cEeSTx0fDaLRLHYwp4/SNdr79QRTMw=; b=hSAB2cUpl9wuEEZBy14Sxa/PKUIbOJRrp0GNZGqglB28ge2Vo8uMuQhTnap7fHIi0+cStO tl/fQrmb2WP9Musz0rZXMxCbuDyzowJ542t2QGeTytUjowHwFJmOUbn5Cd7KABaOalu9U7 YAOnDtNUkuplDcPT/a4wjTa3VWmBI/q9vu1opSRrdWid1VwWIcdpN2nqriTMzQBb0kJcyV jeyOpNMeb2LoyOg+PU0+ngyzAQK9XNz4xePpsHl08j31gJ8po42crO3bHjkG4Lm/JfsUYk JCgE8xu5UCePDC6oIMwM4avarSDvxxDe3JEAn22Q0ALAyZcUgi3sgWr0Wg6Yjg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2gNN8N211J8r3cEeSTx0fDaLRLHYwp4/SNdr79QRTMw=; b=dNaSQ87APbxkLU/3zJGhxo2ti+7KPT5gznzzsmW95J0CSsF77+2Ni7QVGVzsI2reipgci4 QlMs1doljFH8uHAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 25/30] x86/cpu/topology: Use topology logical mapping mechanism References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:09 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Replace the logical package and die management functionality and retrieve the logical IDs from the topology bitmaps. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/topology.h | 15 ++-- arch/x86/kernel/cpu/common.c | 13 --- arch/x86/kernel/cpu/topology_common.c | 4 + arch/x86/kernel/smpboot.c | 111 -----------------------------= ----- 4 files changed, 12 insertions(+), 131 deletions(-) --- --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -172,6 +172,13 @@ static inline int topology_get_logical_i #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) #define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) =20 + +static inline int topology_phys_to_logical_pkg(unsigned int pkg) +{ + return topology_get_logical_id(pkg << x86_topo_system.dom_shifts[TOPO_PKG= _DOMAIN], + TOPO_PKG_DOMAIN); +} + extern int __max_smt_threads; =20 static inline int topology_max_smt_threads(void) @@ -181,10 +188,6 @@ static inline int topology_max_smt_threa =20 #include =20 -int topology_update_package_map(unsigned int apicid, unsigned int cpu); -int topology_update_die_map(unsigned int dieid, unsigned int cpu); -int topology_phys_to_logical_pkg(unsigned int pkg); - extern unsigned int __amd_nodes_per_pkg; =20 static inline unsigned int topology_amd_nodes_per_pkg(void) @@ -205,10 +208,6 @@ static inline bool topology_is_primary_t } =20 #else /* CONFIG_SMP */ -static inline int -topology_update_package_map(unsigned int apicid, unsigned int cpu) { retur= n 0; } -static inline int -topology_update_die_map(unsigned int dieid, unsigned int cpu) { return 0; } static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1718,18 +1718,6 @@ static void generic_identify(struct cpui #endif } =20 -static void update_package_map(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned int cpu =3D smp_processor_id(); - - BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); - BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); -#else - c->topo.logical_pkg_id =3D 0; -#endif -} - /* * This does the hard work of actually picking apart the CPU stuff... */ @@ -1913,7 +1901,6 @@ void identify_secondary_cpu(struct cpuin #ifdef CONFIG_X86_32 enable_sep_cpu(); #endif - update_package_map(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); if (boot_cpu_has_bug(X86_BUG_GDS)) --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -10,6 +10,7 @@ #include "cpu.h" =20 struct x86_topology_system x86_topo_system __ro_after_init; +EXPORT_SYMBOL_GPL(x86_topo_system); =20 unsigned int __amd_nodes_per_pkg __ro_after_init; EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg); @@ -147,6 +148,9 @@ static void topo_set_ids(struct topo_sca c->topo.pkg_id =3D topo_shift_apicid(apicid, TOPO_PKG_DOMAIN); c->topo.die_id =3D topo_shift_apicid(apicid, TOPO_DIE_DOMAIN); =20 + c->topo.logical_pkg_id =3D topology_get_logical_id(apicid, TOPO_PKG_DOMAI= N); + c->topo.logical_die_id =3D topology_get_logical_id(apicid, TOPO_DIE_DOMAI= N); + /* Package relative core ID */ c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -125,23 +125,6 @@ struct mwait_cpu_dead { */ static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); =20 -/* Logical package management. */ -struct logical_maps { - u32 phys_pkg_id; - u32 phys_die_id; - u32 logical_pkg_id; - u32 logical_die_id; -}; - -/* Temporary workaround until the full topology mechanics is in place */ -static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) =3D { - .phys_pkg_id =3D U32_MAX, - .phys_die_id =3D U32_MAX, -}; - -static unsigned int logical_packages __read_mostly; -static unsigned int logical_die __read_mostly; - /* Maximum number of SMT threads on any online core */ int __read_mostly __max_smt_threads =3D 1; =20 @@ -334,103 +317,11 @@ static void notrace start_secondary(void cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); } =20 -/** - * topology_phys_to_logical_pkg - Map a physical package id to a logical - * @phys_pkg: The physical package id to map - * - * Returns logical package id or -1 if not found - */ -int topology_phys_to_logical_pkg(unsigned int phys_pkg) -{ - int cpu; - - for_each_possible_cpu(cpu) { - if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D phys_pkg) - return per_cpu(logical_maps.logical_pkg_id, cpu); - } - return -1; -} -EXPORT_SYMBOL(topology_phys_to_logical_pkg); - -/** - * topology_phys_to_logical_die - Map a physical die id to logical - * @die_id: The physical die id to map - * @cur_cpu: The CPU for which the mapping is done - * - * Returns logical die id or -1 if not found - */ -static int topology_phys_to_logical_die(unsigned int die_id, unsigned int = cur_cpu) -{ - int cpu, proc_id =3D cpu_data(cur_cpu).topo.pkg_id; - - for_each_possible_cpu(cpu) { - if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D proc_id && - per_cpu(logical_maps.phys_die_id, cpu) =3D=3D die_id) - return per_cpu(logical_maps.logical_die_id, cpu); - } - return -1; -} - -/** - * topology_update_package_map - Update the physical to logical package map - * @pkg: The physical package id as retrieved via CPUID - * @cpu: The cpu for which this is updated - */ -int topology_update_package_map(unsigned int pkg, unsigned int cpu) -{ - int new; - - /* Already available somewhere? */ - new =3D topology_phys_to_logical_pkg(pkg); - if (new >=3D 0) - goto found; - - new =3D logical_packages++; - if (new !=3D pkg) { - pr_info("CPU %u Converting physical %u to logical package %u\n", - cpu, pkg, new); - } -found: - per_cpu(logical_maps.phys_pkg_id, cpu) =3D pkg; - per_cpu(logical_maps.logical_pkg_id, cpu) =3D new; - cpu_data(cpu).topo.logical_pkg_id =3D new; - return 0; -} -/** - * topology_update_die_map - Update the physical to logical die map - * @die: The die id as retrieved via CPUID - * @cpu: The cpu for which this is updated - */ -int topology_update_die_map(unsigned int die, unsigned int cpu) -{ - int new; - - /* Already available somewhere? */ - new =3D topology_phys_to_logical_die(die, cpu); - if (new >=3D 0) - goto found; - - new =3D logical_die++; - if (new !=3D die) { - pr_info("CPU %u Converting physical %u to logical die %u\n", - cpu, die, new); - } -found: - per_cpu(logical_maps.phys_die_id, cpu) =3D die; - per_cpu(logical_maps.logical_die_id, cpu) =3D new; - cpu_data(cpu).topo.logical_die_id =3D new; - return 0; -} - static void __init smp_store_boot_cpu_info(void) { - int id =3D 0; /* CPU 0 */ - struct cpuinfo_x86 *c =3D &cpu_data(id); + struct cpuinfo_x86 *c =3D &cpu_data(0); =20 *c =3D boot_cpu_data; - c->cpu_index =3D id; - topology_update_package_map(c->topo.pkg_id, id); - topology_update_die_map(c->topo.die_id, id); c->initialized =3D true; } From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FCC985950 for ; Tue, 13 Feb 2024 21:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 26/30] x86/cpu/topology: Retrieve cores per package from topology bitmaps References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:10 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Similar to other sizing information the number of cores per package can be established from the topology bitmap. Provide a function for retrieving that information and replace the buggy hack in the CPUID evaluation with it. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/topology.c | 43 +++++++++++++++++++++++++++++= +++++ arch/x86/kernel/cpu/topology.h | 11 ++++++++ arch/x86/kernel/cpu/topology_common.c | 18 ++------------ 3 files changed, 57 insertions(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -217,6 +217,49 @@ int topology_get_logical_id(u32 apicid, } EXPORT_SYMBOL_GPL(topology_get_logical_id); =20 +/** + * topology_unit_count - Retrieve the count of specified units at a given = topology domain level + * @apicid: The APIC ID which specifies the search range + * @which_units: The domain level specifying the units to count + * @at_level: The domain level at which @which_units have to be counted + * + * This returns the number of possible units according to the enumerated + * information. + * + * E.g. topology_count_units(apicid, TOPO_CORE_DOMAIN, TOPO_PKG_DOMAIN) + * counts the number of possible cores in the package to which @apicid + * belongs. + * + * @at_level must obviously be greater than @which_level to produce useful + * results. If @at_level is equal to @which_units the result is + * unsurprisingly 1. If @at_level is less than @which_units the results + * is by definition undefined and the function returns 0. + */ +unsigned int topology_unit_count(u32 apicid, enum x86_topology_domains whi= ch_units, + enum x86_topology_domains at_level) +{ + /* Remove the bits below @at_level to get the proper level ID of @apicid = */ + unsigned int lvlid =3D topo_apicid(apicid, at_level); + unsigned int id, end, cnt =3D 0; + + if (lvlid >=3D MAX_LOCAL_APIC) + return 0; + if (!test_bit(lvlid, apic_maps[at_level].map)) + return 0; + if (which_units > at_level) + return 0; + if (which_units =3D=3D at_level) + return 1; + + /* Calculate the exclusive end */ + end =3D lvlid + (1U << x86_topo_system.dom_shifts[at_level]); + /* Unfortunately there is no bitmap_weight_range() */ + for (id =3D find_next_bit(apic_maps[which_units].map, end, lvlid); + id < end; id =3D find_next_bit(apic_maps[which_units].map, end, ++id= )) + cnt++; + return cnt; +} + #ifdef CONFIG_ACPI_HOTPLUG_CPU /** * topology_hotplug_apic - Handle a physical hotplugged APIC after boot --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -53,4 +53,15 @@ static inline void topology_update_dom(s tscan->dom_ncpus[dom] =3D ncpus; } =20 +#ifdef CONFIG_X86_LOCAL_APIC +unsigned int topology_unit_count(u32 apicid, enum x86_topology_domains whi= ch_units, + enum x86_topology_domains at_level); +#else +static inline unsigned int topology_unit_count(u32 apicid, enum x86_topolo= gy_domains which_units, + enum x86_topology_domains at_level) +{ + return 1; +} +#endif + #endif /* ARCH_X86_TOPOLOGY_H */ --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -155,25 +155,15 @@ static void topo_set_ids(struct topo_sca c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; =20 + /* Maximum number of cores on this package */ + c->x86_max_cores =3D topology_unit_count(apicid, TOPO_CORE_DOMAIN, TOPO_P= KG_DOMAIN); + c->topo.amd_node_id =3D tscan->amd_node_id; =20 if (c->x86_vendor =3D=3D X86_VENDOR_AMD) cpu_topology_fixup_amd(tscan); } =20 -static void topo_set_max_cores(struct topo_scan *tscan) -{ - /* - * Bug compatible for now. This is broken on hybrid systems: - * 8 cores SMT + 8 cores w/o SMT - * tscan.dom_ncpus[TOPO_DIEGRP_DOMAIN] =3D 24; 24 / 2 =3D 12 !! - * - * Cannot be fixed without further topology enumeration changes. - */ - tscan->c->x86_max_cores =3D tscan->dom_ncpus[TOPO_DIEGRP_DOMAIN] >> - x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; -} - void cpu_parse_topology(struct cpuinfo_x86 *c) { unsigned int dom, cpu =3D smp_processor_id(); @@ -201,7 +191,6 @@ void cpu_parse_topology(struct cpuinfo_x } =20 topo_set_ids(&tscan); - topo_set_max_cores(&tscan); } =20 void __init cpu_init_topology(struct cpuinfo_x86 *c) @@ -223,7 +212,6 @@ void __init cpu_init_topology(struct cpu } =20 topo_set_ids(&tscan); - topo_set_max_cores(&tscan); =20 /* * AMD systems have Nodes per package which cannot be mapped to From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD6B386628 for ; Tue, 13 Feb 2024 21:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858375; cv=none; b=olgaWqFDUF/AobVt+fW80Rf5woZj7dTi7RM6atHEcP59KfhrBVxlI+UuBdbgzUzecL00/DbbBVR5O8LRrGLz+5CDFOEZgXJ2uunXvECKBEK590FeXrRP6kNHsIDLt29DzX89mWmvyjYsyETjsoScBxfDRxkvSC/OfDRJx5nCrcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858375; c=relaxed/simple; bh=s/A2+ZY7Rf7M0EQ3UGtS6O9OKfyKowSFbCRCkkdvXZk=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=M3L4VVVDG8nCyss+DJ+J6aJPN+Fks3vJ2S7NQ4097a5RSeHni7N7ZKo73ZfcEt9Hd92zhB/6TcKf34yfE92GCbuxBF+tgrAavGrvW8sTV9jY7NfuT2YPNWhb9zBRLu7CWz0PdAplzqrNBzF+L+4SCp4w/q0424aGfXcYtYbJH1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SVTVjhBs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Y/5noyqM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SVTVjhBs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Y/5noyqM" Message-ID: <20240213210253.011307973@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4pCQK2UFAUtL2O0jgy3dfLAezLU+/RO2d3+vkQMhqqc=; b=SVTVjhBsuXeacGadV0DKCQkrh08WGOaOh93yoWb0oArH+CENTCfSu6yhp/iBecEGLurC7W 4mtNApSCX5M/YOzYYE500kGa9cFHN4UJYvzaQnHYc6VjKY66xbteueK2m1wsmyEAQaONgs 2ZTLrTjfcR9s44uX30uJm3R+LLrhTDmjMxzynH1crLrrik0/Gltd4apopDeh8f7oHbnsAr X+0zAbgK28crpc5u/11lNB/72fgFOdL4DozNZz3f3A0KMlA8VsyLiqKcwygGM8tRE4NsMH bcz/Uf8TYnYoIn0xoh5W32v+O0vPsE+cAIopkQ1DCfcjEM0YzarlOT6l25OIRw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4pCQK2UFAUtL2O0jgy3dfLAezLU+/RO2d3+vkQMhqqc=; b=Y/5noyqMTHkGWUbuwIfHe6koxOwmdecHVhf+fCCyTSKgABdfzNr+q1rMPyNDEr9PkY0iIt anp1utXf5gnQPzBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 27/30] x86/cpu/topology: Rename smp_num_siblings References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:12 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner It's really a non-intuitive name. Rename it to __max_threads_per_core which is obvious. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/perf_event_p4.h | 4 ++-- arch/x86/include/asm/smp.h | 2 -- arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/common.c | 6 +++--- arch/x86/kernel/cpu/debugfs.c | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/cpu/topology.c | 6 +++--- arch/x86/kernel/process.c | 2 +- arch/x86/kernel/smpboot.c | 2 +- 9 files changed, 13 insertions(+), 14 deletions(-) --- --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -181,7 +181,7 @@ static inline u64 p4_clear_ht_bit(u64 co static inline int p4_ht_active(void) { #ifdef CONFIG_SMP - return smp_num_siblings > 1; + return __max_threads_per_core > 1; #endif return 0; } @@ -189,7 +189,7 @@ static inline int p4_ht_active(void) static inline int p4_ht_thread(int cpu) { #ifdef CONFIG_SMP - if (smp_num_siblings =3D=3D 2) + if (__max_threads_per_core =3D=3D 2) return cpu !=3D cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map)); #endif return 0; --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -8,8 +8,6 @@ #include #include =20 -extern unsigned int smp_num_siblings; - DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -145,6 +145,7 @@ extern const struct cpumask *cpu_cluster =20 extern unsigned int __max_dies_per_package; extern unsigned int __max_logical_packages; +extern unsigned int __max_threads_per_core; =20 static inline unsigned int topology_max_packages(void) { --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -73,8 +73,8 @@ u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ -unsigned int smp_num_siblings __ro_after_init =3D 1; -EXPORT_SYMBOL(smp_num_siblings); +unsigned int __max_threads_per_core __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_threads_per_core); =20 unsigned int __max_dies_per_package __ro_after_init =3D 1; EXPORT_SYMBOL(__max_dies_per_package); @@ -2251,7 +2251,7 @@ void __init arch_cpu_finalize_init(void) * identify_boot_cpu() initialized SMT support information, let the * core code know. */ - cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings); + cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); =20 if (!IS_ENABLED(CONFIG_SMP)) { pr_info("CPU: "); --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -30,7 +30,7 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); seq_printf(m, "max_cores: %u\n", c->x86_max_cores); seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); - seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); + seq_printf(m, "max_threads_per_core:%u\n", __max_threads_per_core); return 0; } =20 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -433,7 +433,7 @@ static u32 get_nbc_for_node(int node_id) struct cpuinfo_x86 *c =3D &boot_cpu_data; u32 cores_per_node; =20 - cores_per_node =3D (c->x86_max_cores * smp_num_siblings) / topology_amd_n= odes_per_pkg(); + cores_per_node =3D (c->x86_max_cores * __max_threads_per_core) / topology= _amd_nodes_per_pkg(); return cores_per_node * node_id; } =20 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -76,7 +76,7 @@ bool arch_match_cpu_phys_id(int cpu, u64 #ifdef CONFIG_SMP static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { - if (!(apicid & (smp_num_siblings - 1))) + if (!(apicid & (__max_threads_per_core - 1))) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } #else @@ -429,8 +429,8 @@ void __init topology_init_possible_cpus( * Can't use order delta here as order(cnta) can be equal * order(cntb) even if cnta !=3D cntb. */ - smp_num_siblings =3D DIV_ROUND_UP(cntb, cnta); - pr_info("Max. threads per core: %3u\n", smp_num_siblings); + __max_threads_per_core =3D DIV_ROUND_UP(cntb, cnta); + pr_info("Max. threads per core: %3u\n", __max_threads_per_core); =20 pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -936,7 +936,7 @@ static __cpuidle void mwait_idle(void) void select_idle_routine(const struct cpuinfo_x86 *c) { #ifdef CONFIG_SMP - if (boot_option_idle_override =3D=3D IDLE_POLL && smp_num_siblings > 1) + if (boot_option_idle_override =3D=3D IDLE_POLL && __max_threads_per_core = > 1) pr_warn_once("WARNING: polling idle and HT enabled, performance may degr= ade\n"); #endif if (x86_idle_set() || boot_option_idle_override =3D=3D IDLE_POLL) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -563,7 +563,7 @@ static void __init build_sched_topology( =20 void set_cpu_sibling_map(int cpu) { - bool has_smt =3D smp_num_siblings > 1; + bool has_smt =3D __max_threads_per_core > 1; bool has_mp =3D has_smt || boot_cpu_data.x86_max_cores > 1; struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct cpuinfo_x86 *o; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 28/30] x86/cpu/topology: Rename topology_max_die_per_package() References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:13 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The plural of die is dies. Signed-off-by: Thomas Gleixner --- arch/x86/events/intel/cstate.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/intel/uncore_snbep.c | 2 +- arch/x86/events/rapl.c | 2 +- arch/x86/include/asm/topology.h | 2 +- drivers/hwmon/coretemp.c | 2 +- drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c | 2 +- drivers/powercap/intel_rapl_common.c | 2 +- drivers/thermal/intel/intel_hfi.c | 2 +- drivers/thermal/intel/intel_powerclamp.c | 2 +- drivers/thermal/intel/x86_pkg_temp_thermal.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) --- --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -834,7 +834,7 @@ static int __init cstate_init(void) } =20 if (has_cstate_pkg) { - if (topology_max_die_per_package() > 1) { + if (topology_max_dies_per_package() > 1) { err =3D perf_pmu_register(&cstate_pkg_pmu, "cstate_die", -1); } else { --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1893,7 +1893,7 @@ static int __init intel_uncore_init(void return -ENODEV; =20 __uncore_max_dies =3D - topology_max_packages() * topology_max_die_per_package(); + topology_max_packages() * topology_max_dies_per_package(); =20 id =3D x86_match_cpu(intel_uncore_match); if (!id) { --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -1406,7 +1406,7 @@ static int topology_gidnid_map(int nodei */ for (i =3D 0; i < 8; i++) { if (nodeid =3D=3D GIDNIDMAP(gidnid, i)) { - if (topology_max_die_per_package() > 1) + if (topology_max_dies_per_package() > 1) die_id =3D i; else die_id =3D topology_phys_to_logical_pkg(i); --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -674,7 +674,7 @@ static const struct attribute_group *rap =20 static int __init init_rapl_pmus(void) { - int maxdie =3D topology_max_packages() * topology_max_die_per_package(); + int maxdie =3D topology_max_packages() * topology_max_dies_per_package(); size_t size; =20 size =3D sizeof(*rapl_pmus) + maxdie * sizeof(struct rapl_pmu *); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -152,7 +152,7 @@ static inline unsigned int topology_max_ return __max_logical_packages; } =20 -static inline unsigned int topology_max_die_per_package(void) +static inline unsigned int topology_max_dies_per_package(void) { return __max_dies_per_package; } --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -780,7 +780,7 @@ static int __init coretemp_init(void) if (!x86_match_cpu(coretemp_ids)) return -ENODEV; =20 - max_zones =3D topology_max_packages() * topology_max_die_per_package(); + max_zones =3D topology_max_packages() * topology_max_dies_per_package(); zone_devices =3D kcalloc(max_zones, sizeof(struct platform_device *), GFP_KERNEL); if (!zone_devices) --- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c +++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c @@ -242,7 +242,7 @@ static int __init intel_uncore_init(void return -ENODEV; =20 uncore_max_entries =3D topology_max_packages() * - topology_max_die_per_package(); + topology_max_dies_per_package(); uncore_instances =3D kcalloc(uncore_max_entries, sizeof(*uncore_instances), GFP_KERNEL); if (!uncore_instances) --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -1564,7 +1564,7 @@ struct rapl_package *rapl_add_package(in if (id_is_cpu) { rp->id =3D topology_logical_die_id(id); rp->lead_cpu =3D id; - if (topology_max_die_per_package() > 1) + if (topology_max_dies_per_package() > 1) snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d-die-%d", topology_physical_package_id(id), topology_die_id(id)); else --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -581,7 +581,7 @@ void __init intel_hfi_init(void) =20 /* There is one HFI instance per die/package. */ max_hfi_instances =3D topology_max_packages() * - topology_max_die_per_package(); + topology_max_dies_per_package(); =20 /* * This allocation may fail. CPU hotplug callbacks must check --- a/drivers/thermal/intel/intel_powerclamp.c +++ b/drivers/thermal/intel/intel_powerclamp.c @@ -616,7 +616,7 @@ static int powerclamp_idle_injection_reg poll_pkg_cstate_enable =3D false; if (cpumask_equal(cpu_present_mask, idle_injection_cpu_mask)) { ii_dev =3D idle_inject_register_full(idle_injection_cpu_mask, idle_injec= t_update); - if (topology_max_packages() =3D=3D 1 && topology_max_die_per_package() = =3D=3D 1) + if (topology_max_packages() =3D=3D 1 && topology_max_dies_per_package() = =3D=3D 1) poll_pkg_cstate_enable =3D true; } else { ii_dev =3D idle_inject_register(idle_injection_cpu_mask); --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -494,7 +494,7 @@ static int __init pkg_temp_thermal_init( if (!x86_match_cpu(pkg_temp_thermal_ids)) return -ENODEV; =20 - max_id =3D topology_max_packages() * topology_max_die_per_package(); + max_id =3D topology_max_packages() * topology_max_dies_per_package(); zones =3D kcalloc(max_id, sizeof(struct zone_device *), GFP_KERNEL); if (!zones) From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F68186656 for ; Tue, 13 Feb 2024 21:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858378; cv=none; b=Zhkg53Nlotm8jb3tBWM1OOKKurlAoOrNqTpY3+/FkVneC+TEYEobGW2oENXMAjQM3kNQsulMJLzMCKlHuMrdTYD14BRSqSJeZD1//A3Zm3Tebqk4MGdSo+tsGJxVz2bWOGPfxme1TQ+JCG7CmIpA54Zp64Axzx4HyEI3T3qmgZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858378; c=relaxed/simple; bh=BYCek0/+KoSqfQdbi1lbVUiGFjTm1kaHkGsteLGoGIE=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=X+6pSAoa9PBlwKuIwtWwgOmpCxP8m+SkzI5/OyR2UZNLM1Y2JtaYkqqZBGs9djaNGxGDVIhuMDxIO7dpZi48x55qGe5LtI5ZXPSA4Tutzy5RYgIg7hxPV6jH5uBCYlRsB7aFrjE/cD1h5zuZbxvjV1CwM5FeHoWa/LjZPJZtXoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hYaOnL/2; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3J2b59gv; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hYaOnL/2"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3J2b59gv" Message-ID: <20240213210253.120958987@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858375; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C480USuDHEN1DJ+mKCDr2IgHfoW7jqhf18boy4k9tqM=; b=hYaOnL/2Ivox9nGn6t1XhqdZYSeR367afVMDfPkVKYBkupJXWsIv3t0KB/M60YAmcRbtRQ GJsQ9TsdWBQ0Vh9i0vc3pHz5awnxMJRYE52WHDqwaFl7o1rVeSWAWiki82qlR/o1uMaABo qdyAHDgFOPDOehXMgCsc5nHiptunDWV3ZolodYWeKNAE0a1jLz8Zi6bHAUb4U3TVqkLJ1H iOlNyc0JfnU4lA9/HGWBXd0hIsMqHnCg1X1LNKCk24Hrb4dGiO5TOXSgw1mgI3Ar8uSDBJ Mi7UF6MD2hLVhMeIOcDL9iyKr9q480hyTWcVLVGxd+5BaoOL9wATQtP5tQ2NVA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858375; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C480USuDHEN1DJ+mKCDr2IgHfoW7jqhf18boy4k9tqM=; b=3J2b59gvV8IAF6w5DQ21L0W8SAgnPLSrBqG0IGpzra53FVKM3SBvvgt86wGk+3SkkW/qRy NKCjFWVmism2MOAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 29/30] x86/cpu/topology: Provide __num_[cores|threads]_per_package References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:14 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Expose properly accounted information and accessors so the fiddling with other topology variables can be replaced. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/topology.h | 12 ++++++++++++ arch/x86/kernel/cpu/common.c | 6 ++++++ arch/x86/kernel/cpu/topology.c | 8 +++++++- 3 files changed, 25 insertions(+), 1 deletion(-) --- --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -146,6 +146,8 @@ extern const struct cpumask *cpu_cluster extern unsigned int __max_dies_per_package; extern unsigned int __max_logical_packages; extern unsigned int __max_threads_per_core; +extern unsigned int __num_threads_per_package; +extern unsigned int __num_cores_per_package; =20 static inline unsigned int topology_max_packages(void) { @@ -157,6 +159,16 @@ static inline unsigned int topology_max_ return __max_dies_per_package; } =20 +static inline unsigned int topology_num_cores_per_package(void) +{ + return __num_cores_per_package; +} + +static inline unsigned int topology_num_threads_per_package(void) +{ + return __num_threads_per_package; +} + #ifdef CONFIG_X86_LOCAL_APIC int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level= ); #else --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -82,6 +82,12 @@ EXPORT_SYMBOL(__max_dies_per_package); unsigned int __max_logical_packages __ro_after_init =3D 1; EXPORT_SYMBOL(__max_logical_packages); =20 +unsigned int __num_cores_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__num_cores_per_package); + +unsigned int __num_threads_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__num_threads_per_package); + static struct ppin_info { int feature; int msr_ppin_ctl; --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -392,7 +392,7 @@ void __init topology_init_possible_cpus( unsigned int disabled =3D topo_info.nr_disabled_cpus; unsigned int cnta, cntb, cpu, allowed =3D 1; unsigned int total =3D assigned + disabled; - u32 apicid; + u32 apicid, firstid; =20 if (!restrict_to_up()) { if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { @@ -432,6 +432,12 @@ void __init topology_init_possible_cpus( __max_threads_per_core =3D DIV_ROUND_UP(cntb, cnta); pr_info("Max. threads per core: %3u\n", __max_threads_per_core); =20 + firstid =3D find_first_bit(apic_maps[TOPO_SMT_DOMAIN].map, MAX_LOCAL_APIC= ); + __num_cores_per_package =3D topology_unit_count(firstid, TOPO_CORE_DOMAIN= , TOPO_PKG_DOMAIN); + pr_info("Num. cores per package: %3u\n", __num_cores_per_package); + __num_threads_per_package =3D topology_unit_count(firstid, TOPO_SMT_DOMAI= N, TOPO_PKG_DOMAIN); + pr_info("Num. threads per package: %3u\n", __num_threads_per_package); + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); From nobody Wed Dec 17 07:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6189E126F27 for ; Tue, 13 Feb 2024 21:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch 30/30] x86/cpu/topology: Get rid of cpuinfo:: X86_max_cores References: <20240213205415.307029033@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 13 Feb 2024 22:06:16 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Now that __num_cores_per_package and __num_threads_per_package are available, cpuinfo::x86_max_cores and the related math all over the place can be replaced with the ready to consume data. Signed-off-by: Thomas Gleixner --- Documentation/arch/x86/topology.rst | 24 ++++++++----------= ----- arch/x86/events/intel/uncore_nhmex.c | 4 +-- arch/x86/events/intel/uncore_snb.c | 8 +++---- arch/x86/events/intel/uncore_snbep.c | 16 +++++++-------- arch/x86/include/asm/processor.h | 2 - arch/x86/kernel/cpu/cacheinfo.c | 2 - arch/x86/kernel/cpu/common.c | 1=20 arch/x86/kernel/cpu/debugfs.c | 3 +- arch/x86/kernel/cpu/mce/inject.c | 3 -- arch/x86/kernel/cpu/microcode/intel.c | 2 - arch/x86/kernel/cpu/topology_common.c | 3 -- arch/x86/kernel/smpboot.c | 2 - drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 2 - drivers/hwmon/fam15h_power.c | 2 - 14 files changed, 31 insertions(+), 43 deletions(-) --- --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -47,17 +47,21 @@ AMD nomenclature for package is 'Node'. =20 Package-related topology information in the kernel: =20 - - cpuinfo_x86.x86_max_cores: + - topology_num_threads_per_package() =20 - The number of cores in a package. This information is retrieved via CP= UID. + The number of threads in a package. =20 - - cpuinfo_x86.x86_max_dies: + - topology_num_cores_per_package() =20 - The number of dies in a package. This information is retrieved via CPU= ID. + The number of cores in a package. + + - topology_max_dies_per_package() + + The maximum number of dies in a package. =20 - cpuinfo_x86.topo.die_id: =20 - The physical ID of the die. This information is retrieved via CPUID. + The physical ID of the die. =20 - cpuinfo_x86.topo.pkg_id: =20 @@ -96,16 +100,6 @@ are SMT- or CMT-type threads. AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses "core". =20 -Core-related topology information in the kernel: - - - smp_num_siblings: - - The number of threads in a core. The number of threads in a package ca= n be - calculated by:: - - threads_per_package =3D cpuinfo_x86.x86_max_cores * smp_num_siblings - - Threads =3D=3D=3D=3D=3D=3D=3D A thread is a single scheduling unit. It's the equivalent to a logical Lin= ux --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -1221,8 +1221,8 @@ void nhmex_uncore_cpu_init(void) uncore_nhmex =3D true; else nhmex_uncore_mbox.event_descs =3D wsmex_uncore_mbox_events; - if (nhmex_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - nhmex_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (nhmex_uncore_cbox.num_boxes > topology_num_cores_per_package()) + nhmex_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D nhmex_msr_uncores; } /* end of Nehalem-EX uncore support */ --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -364,8 +364,8 @@ static struct intel_uncore_type *snb_msr void snb_uncore_cpu_init(void) { uncore_msr_uncores =3D snb_msr_uncores; - if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - snb_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (snb_uncore_cbox.num_boxes > topology_num_cores_per_package()) + snb_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); } =20 static void skl_uncore_msr_init_box(struct intel_uncore_box *box) @@ -428,8 +428,8 @@ static struct intel_uncore_type *skl_msr void skl_uncore_cpu_init(void) { uncore_msr_uncores =3D skl_msr_uncores; - if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - skl_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (skl_uncore_cbox.num_boxes > topology_num_cores_per_package()) + skl_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); snb_uncore_arb.ops =3D &skl_uncore_msr_ops; } =20 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -1172,8 +1172,8 @@ static struct intel_uncore_type *snbep_m =20 void snbep_uncore_cpu_init(void) { - if (snbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - snbep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (snbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + snbep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D snbep_msr_uncores; } =20 @@ -1845,8 +1845,8 @@ static struct intel_uncore_type *ivbep_m =20 void ivbep_uncore_cpu_init(void) { - if (ivbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - ivbep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (ivbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + ivbep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D ivbep_msr_uncores; } =20 @@ -2917,8 +2917,8 @@ static bool hswep_has_limit_sbox(unsigne =20 void hswep_uncore_cpu_init(void) { - if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - hswep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (hswep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + hswep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); =20 /* Detect 6-8 core systems with only two SBOXes */ if (hswep_has_limit_sbox(HSWEP_PCU_DID)) @@ -3280,8 +3280,8 @@ static struct event_constraint bdx_uncor =20 void bdx_uncore_cpu_init(void) { - if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - bdx_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (bdx_uncore_cbox.num_boxes > topology_num_cores_per_package()) + bdx_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D bdx_msr_uncores; =20 /* Detect systems with no SBOXes */ --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -149,8 +149,6 @@ struct cpuinfo_x86 { unsigned long loops_per_jiffy; /* protected processor identification number */ u64 ppin; - /* cpuid returned max cores value: */ - u16 x86_max_cores; u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -301,7 +301,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_ eax->split.type =3D types[leaf]; eax->split.level =3D levels[leaf]; eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D __this_cpu_read(cpu_info.x86_max_cores) -= 1; + eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 =20 if (assoc =3D=3D 0xffff) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1738,7 +1738,6 @@ static void identify_cpu(struct cpuinfo_ c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ c->x86_vendor_id[0] =3D '\0'; /* Unset */ c->x86_model_id[0] =3D '\0'; /* Unset */ - c->x86_max_cores =3D 1; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -28,7 +28,8 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "l2c_id: %u\n", c->topo.l2c_id); seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); - seq_printf(m, "max_cores: %u\n", c->x86_max_cores); + seq_printf(m, "num_threads: %u\n", __num_threads_per_package); + seq_printf(m, "num_cores: %u\n", __num_cores_per_package); seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); seq_printf(m, "max_threads_per_core:%u\n", __max_threads_per_core); return 0; --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -430,10 +430,9 @@ static void trigger_thr_int(void *info) =20 static u32 get_nbc_for_node(int node_id) { - struct cpuinfo_x86 *c =3D &boot_cpu_data; u32 cores_per_node; =20 - cores_per_node =3D (c->x86_max_cores * __max_threads_per_core) / topology= _amd_nodes_per_pkg(); + cores_per_node =3D topology_num_threads_per_package() / topology_amd_node= s_per_pkg(); return cores_per_node * node_id; } =20 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -641,7 +641,7 @@ static __init void calc_llc_size_per_cor { u64 llc_size =3D c->x86_cache_size * 1024ULL; =20 - do_div(llc_size, c->x86_max_cores); + do_div(llc_size, topology_num_cores_per_package()); llc_size_per_core =3D (unsigned int)llc_size; } =20 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -155,9 +155,6 @@ static void topo_set_ids(struct topo_sca c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; =20 - /* Maximum number of cores on this package */ - c->x86_max_cores =3D topology_unit_count(apicid, TOPO_CORE_DOMAIN, TOPO_P= KG_DOMAIN); - c->topo.amd_node_id =3D tscan->amd_node_id; =20 if (c->x86_vendor =3D=3D X86_VENDOR_AMD) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -564,7 +564,7 @@ static void __init build_sched_topology( void set_cpu_sibling_map(int cpu) { bool has_smt =3D __max_threads_per_core > 1; - bool has_mp =3D has_smt || boot_cpu_data.x86_max_cores > 1; + bool has_mp =3D has_smt || topology_num_cores_per_package() > 1; struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct cpuinfo_x86 *o; int i, threads; --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -451,7 +451,7 @@ static int vangogh_init_smc_tables(struc =20 #ifdef CONFIG_X86 /* AMD x86 APU only */ - smu->cpu_core_num =3D boot_cpu_data.x86_max_cores; + smu->cpu_core_num =3D topology_num_cores_per_package(); #else smu->cpu_core_num =3D 4; #endif --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -209,7 +209,7 @@ static ssize_t power1_average_show(struc * With the new x86 topology modelling, x86_max_cores is the * compute unit number. */ - cu_num =3D boot_cpu_data.x86_max_cores; + cu_num =3D topology_num_cores_per_package(); =20 ret =3D read_registers(data); if (ret)