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Mon, 12 Feb 2024 19:37:46 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear , Samuel Holland , stable@vger.kernel.org Subject: [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Date: Mon, 12 Feb 2024 19:37:32 -0800 Message-ID: <20240213033744.4069020-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> References: <20240213033744.4069020-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); 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Mon, 12 Feb 2024 19:37:47 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear , Samuel Holland Subject: [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions Date: Mon, 12 Feb 2024 19:37:33 -0800 Message-ID: <20240213033744.4069020-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> References: <20240213033744.4069020-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The baseline for the RISC-V privileged ISA is version 1.10. Using features from newer versions of the privileged ISA requires the supported version to be reported by platform firmware, either in the ISA string (where the binding already accepts version numbers) or in the riscv,isa-extensions property. So far two newer versions are ratified. Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- Changes in v2: - New patch for v2 .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..7faf22df01af 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -121,6 +121,16 @@ properties: version of the privileged ISA specification. =20 # multi-letter extensions, sorted alphanumerically + - const: sm1p11 + description: + The standard Machine ISA v1.11, as ratified in the 20190608 + version of the privileged ISA specification. + + - const: sm1p12 + description: + The standard Machine ISA v1.12, as ratified in the 20211203 + version of the privileged ISA specification. + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -134,6 +144,16 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enab= le. =20 + - const: ss1p11 + description: + The standard Supervisor ISA v1.11, as ratified in the 20190608 + version of the privileged ISA specification. + + - const: ss1p12 + description: + The standard Supervisor ISA v1.12, as ratified in the 20211203 + version of the privileged ISA specification. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced --=20 2.43.0 From nobody Sun Feb 8 14:31:25 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEE5BAD2C for ; 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charset="utf-8" Previously, all extension version numbers were ignored. However, the version number is important for these two extensions. The simplest way to implement this is to use a separate bitmap bit for each supported version, with each successive version implying all of the previous ones. This allows alternatives and riscv_has_extension_[un]likely() to work naturally. To avoid duplicate extensions in /proc/cpuinfo, the new successor_id field allows hiding all but the newest implemented version of an extension. Cc: # v6.7+ Signed-off-by: Samuel Holland --- Changes in v2: - New patch for v2 arch/riscv/include/asm/cpufeature.h | 1 + arch/riscv/include/asm/hwcap.h | 8 ++++++ arch/riscv/kernel/cpu.c | 5 ++++ arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- 4 files changed, 51 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 0bd11862b760..ac71384e7bc4 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { const char *property; const unsigned int *subset_ext_ids; const unsigned int subset_ext_size; + const unsigned int successor_id; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..5b51aa1db15b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,13 +80,21 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SM1p11 74 +#define RISCV_ISA_EXT_SM1p12 75 +#define RISCV_ISA_EXT_SS1p11 76 +#define RISCV_ISA_EXT_SS1p12 77 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX =20 #ifdef CONFIG_RISCV_M_MODE +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA #else +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #endif =20 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index d11d6320fb0d..2e6b90ed0d51 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsign= ed long *isa_bitmap) if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) continue; =20 + /* Only show the newest implemented version of an extension */ + if (riscv_isa_ext[i].successor_id !=3D RISCV_ISA_EXT_INVALID && + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].success= or_id)) + continue; + /* Only multi-letter extensions are split by underscores */ if (strnlen(riscv_isa_ext[i].name, 2) !=3D 1) seq_puts(f, "_"); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c5b13f7dd482..8e10b50120e9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) return true; } =20 -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {= \ +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _= successor) { \ .name =3D #_name, \ .property =3D #_name, \ .id =3D _id, \ .subset_ext_ids =3D _subset_exts, \ - .subset_ext_size =3D _subset_exts_size \ + .subset_ext_size =3D _subset_exts_size, \ + .successor_id =3D _successor, \ } =20 -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, N= ULL, 0) +#define __RISCV_ISA_EXT_DATA(_name, _id) \ + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) =20 /* Used to declare pure "lasso" extension (Zk for instance) */ #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SI= ZE(_bundled_exts)) + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) =20 /* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_I= SA_EXT_INVALID) + +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successo= r) \ + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) =20 static const unsigned int riscv_zk_bundled_exts[] =3D { RISCV_ISA_EXT_ZBKB, @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] =3D { RISCV_ISA_EXT_ZVKB }; =20 +static const unsigned int riscv_sm_ext_versions[] =3D { + RISCV_ISA_EXT_SM1p11, + RISCV_ISA_EXT_SM1p12, +}; + +static const unsigned int riscv_ss_ext_versions[] =3D { + RISCV_ISA_EXT_SS1p11, + RISCV_ISA_EXT_SS1p12, +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versio= ns, 0, + RISCV_ISA_EXT_SM1p12), + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versio= ns, 1, + RISCV_ISA_EXT_INVALID), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versio= ns, 0, + RISCV_ISA_EXT_SS1p12), + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versio= ns, 1, + RISCV_ISA_EXT_INVALID), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc ; 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Mon, 12 Feb 2024 19:37:49 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear , Samuel Holland , stable@vger.kernel.org Subject: [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Date: Mon, 12 Feb 2024 19:37:35 -0800 Message-ID: <20240213033744.4069020-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> References: <20240213033744.4069020-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. Cc: # v6.7+ Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland --- Changes in v2: - Check for privileged ISA v1.12 instead of the specific CSR - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/suspend.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/susp= end.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..be03615486ed 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,8 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch =3D csr_read(CSR_SCRATCH); + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) + context->envcfg =3D csr_read(CSR_ENVCFG); context->tvec =3D csr_read(CSR_TVEC); context->ie =3D csr_read(CSR_IE); =20 @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) + csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); =20 --=20 2.43.0