From nobody Fri Oct 18 04:29:31 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D2722AF0C; Tue, 13 Feb 2024 00:24:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707783882; cv=none; b=XAgYX6BlRgBktmCVV9qKrdQ1ZFxV5cAsLgSUiObGIlxuriJ9mCYYrE6mJp8/hNhhLy+GZqczeMaJmGe0cOnPm3eF5w1JlwQPCDFpC/q7/Vwor1VltWGwHrhAW1eAT7JyOeP1IBe7QMx6k/YLB9s2ZJ7G30EYUT/+t2Mme5yHKPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707783882; c=relaxed/simple; bh=jENiGHyDBDfkXFMRZi02MBN1t2DVNvmbrSh3CPhenDI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VaZ0vtYWs67zcA5xrSi6CB8OT2YVSrwDrdFLlGsjBhWpr8YJOjAGpIB58XUb0/OTjv6rEMxLzzLWbSI52zytGh0N+UEGd+92AjEzX5sKXBeN4kTkSpNLnnOwcWkpQn5sYin85jx93kwn/qU+bXSzji+qfLB3qE8VgIPKkIbUPFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=THMlNu9A; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="THMlNu9A" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41D0OHJ6088672; Mon, 12 Feb 2024 18:24:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707783857; bh=gjIQkQk0XyLlWC62YyfoYsqGsstVP1Jl1mRAtlNrcmg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=THMlNu9ArgCeGH8d2TU4So6YSRfN5t2AE5U+LyEHQdSlVcGf3GwHmfQhpIisTL8TP QSomv8wi6M7yDi62QGyHi6TvsDLSdFb/R+/kNxFn5exSGZYFoE07JDL3gKq4IK/jvw p1uJDXSW+eRF7Tilm0oyW3nTcEvp6b7M/wHQauG0= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41D0OHoE031534 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 12 Feb 2024 18:24:17 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 12 Feb 2024 18:24:16 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 12 Feb 2024 18:24:16 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41D0OGXh119810; Mon, 12 Feb 2024 18:24:16 -0600 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , , , , Wadim Egorov , Francesco Dolcini Subject: [PATCH v2 3/9] arm64: dts: ti: k3-am62a7-sk: Enable eMMC support Date: Mon, 12 Feb 2024 18:24:10 -0600 Message-ID: <20240213002416.1560357-4-jm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213002416.1560357-1-jm@ti.com> References: <20240213002416.1560357-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Nitin Yadav Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0 pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts. Signed-off-by: Nitin Yadav Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f5ae91bf1bdb..c99b2e90f76d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -20,6 +20,7 @@ aliases { serial0 =3D &wkup_uart0; serial2 =3D &main_uart0; serial3 =3D &main_uart1; + mmc0 =3D &sdhci0; mmc1 =3D &sdhci1; }; =20 @@ -263,6 +264,22 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC= 0_CSn3.I2C2_SDA */ >; }; =20 + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins =3D < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -550,6 +567,15 @@ &main_i2c2 { clock-frequency =3D <400000>; }; =20 +&sdhci0 { + /* eMMC */ + status =3D "okay"; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status =3D "okay"; --=20 2.43.0