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charset="utf-8" Add pll_clk to pin group 98 for compatibility with SM8475. Signed-off-by: Danila Tikhonov --- drivers/pinctrl/qcom/pinctrl-sm8450.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/p= inctrl-sm8450.c index 617286711695..45ac8e72c1c7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -957,7 +957,7 @@ static const char * const pll_bist_groups[] =3D { }; =20 static const char * const pll_clk_groups[] =3D { - "gpio107", + "gpio98", "gpio107", }; =20 static const char * const pri_mi2s_groups[] =3D { @@ -1511,7 +1511,7 @@ static const struct msm_pingroup sm8450_groups[] =3D { [95] =3D PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, = _), [96] =3D PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _), [97] =3D PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _), - [98] =3D PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _), + [98] =3D PINGROUP(98, pcie1_clkreqn, phase_flag, pll_clk, _, _, _, _, _, = _), [99] =3D PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _), [100] =3D PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), [101] =3D PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), --=20 2.43.0