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([178.197.223.6]) by smtp.gmail.com with ESMTPSA id i5-20020a05600c290500b0040ef95e1c78sm9337299wmd.3.2024.02.12.10.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 10:29:13 -0800 (PST) From: Krzysztof Kozlowski To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Oleksij Rempel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2] dt-bindings: net: qca,ar9331: convert to DT schema Date: Mon, 12 Feb 2024 19:29:11 +0100 Message-Id: <20240212182911.233819-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Qualcomm Atheros AR9331 built-in switch bindings to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Reviewed-by: Oleksij Rempel --- DSA switch bindings still bring me headache... Changes in v2: 1. Narrow pattern for phy children to ethernet-phy@ or phy@ (MIPS DTS has the latter) - Conor. --- .../devicetree/bindings/net/dsa/ar9331.txt | 147 ---------------- .../bindings/net/dsa/qca,ar9331.yaml | 161 ++++++++++++++++++ 2 files changed, 161 insertions(+), 147 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/dsa/ar9331.txt create mode 100644 Documentation/devicetree/bindings/net/dsa/qca,ar9331.ya= ml diff --git a/Documentation/devicetree/bindings/net/dsa/ar9331.txt b/Documen= tation/devicetree/bindings/net/dsa/ar9331.txt deleted file mode 100644 index f824fdae0da2..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/ar9331.txt +++ /dev/null @@ -1,147 +0,0 @@ -Atheros AR9331 built-in switch -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D - -It is a switch built-in to Atheros AR9331 WiSoC and addressable over inter= nal -MDIO bus. All PHYs are built-in as well. - -Required properties: - - - compatible: should be: "qca,ar9331-switch" - - reg: Address on the MII bus for the switch. - - resets : Must contain an entry for each entry in reset-names. - - reset-names : Must include the following entries: "switch" - - interrupt-parent: Phandle to the parent interrupt controller - - interrupts: IRQ line for the switch - - interrupt-controller: Indicates the switch is itself an interrupt - controller. This is used for the PHY interrupts. - - #interrupt-cells: must be 1 - - mdio: Container of PHY and devices on the switches MDIO bus. - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additi= onal -required and optional properties. -Examples: - -eth0: ethernet@19000000 { - compatible =3D "qca,ar9330-eth"; - reg =3D <0x19000000 0x200>; - interrupts =3D <4>; - - resets =3D <&rst 9>, <&rst 22>; - reset-names =3D "mac", "mdio"; - clocks =3D <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names =3D "eth", "mdio"; - - phy-mode =3D "mii"; - phy-handle =3D <&phy_port4>; -}; - -eth1: ethernet@1a000000 { - compatible =3D "qca,ar9330-eth"; - reg =3D <0x1a000000 0x200>; - interrupts =3D <5>; - resets =3D <&rst 13>, <&rst 23>; - reset-names =3D "mac", "mdio"; - clocks =3D <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names =3D "eth", "mdio"; - - phy-mode =3D "gmii"; - - fixed-link { - speed =3D <1000>; - full-duplex; - }; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - switch10: switch@10 { - #address-cells =3D <1>; - #size-cells =3D <0>; - - compatible =3D "qca,ar9331-switch"; - reg =3D <0x10>; - resets =3D <&rst 8>; - reset-names =3D "switch"; - - interrupt-parent =3D <&miscintc>; - interrupts =3D <12>; - - interrupt-controller; - #interrupt-cells =3D <1>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - switch_port0: port@0 { - reg =3D <0x0>; - ethernet =3D <ð1>; - - phy-mode =3D "gmii"; - - fixed-link { - speed =3D <1000>; - full-duplex; - }; - }; - - switch_port1: port@1 { - reg =3D <0x1>; - phy-handle =3D <&phy_port0>; - phy-mode =3D "internal"; - }; - - switch_port2: port@2 { - reg =3D <0x2>; - phy-handle =3D <&phy_port1>; - phy-mode =3D "internal"; - }; - - switch_port3: port@3 { - reg =3D <0x3>; - phy-handle =3D <&phy_port2>; - phy-mode =3D "internal"; - }; - - switch_port4: port@4 { - reg =3D <0x4>; - phy-handle =3D <&phy_port3>; - phy-mode =3D "internal"; - }; - }; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - interrupt-parent =3D <&switch10>; - - phy_port0: phy@0 { - reg =3D <0x0>; - interrupts =3D <0>; - }; - - phy_port1: phy@1 { - reg =3D <0x1>; - interrupts =3D <0>; - }; - - phy_port2: phy@2 { - reg =3D <0x2>; - interrupts =3D <0>; - }; - - phy_port3: phy@3 { - reg =3D <0x3>; - interrupts =3D <0>; - }; - - phy_port4: phy@4 { - reg =3D <0x4>; - interrupts =3D <0>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/dsa/qca,ar9331.yaml b/Do= cumentation/devicetree/bindings/net/dsa/qca,ar9331.yaml new file mode 100644 index 000000000000..fd9ddc59d38c --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/qca,ar9331.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/qca,ar9331.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR9331 built-in switch + +maintainers: + - Oleksij Rempel + +description: + Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and + addressable over internal MDIO bus. All PHYs are built-in as well. + +properties: + compatible: + const: qca,ar9331-switch + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + properties: + interrupt-parent: true + + patternProperties: + '(ethernet-)?phy@[0-4]+$': + type: object + unevaluatedProperties: false + + properties: + reg: true + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: switch + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - mdio + - ports + - resets + - reset-names + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch10: switch@10 { + compatible =3D "qca,ar9331-switch"; + reg =3D <0x10>; + + interrupt-parent =3D <&miscintc>; + interrupts =3D <12>; + interrupt-controller; + #interrupt-cells =3D <1>; + + resets =3D <&rst 8>; + reset-names =3D "switch"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0x0>; + ethernet =3D <ð1>; + + phy-mode =3D "gmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + port@1 { + reg =3D <0x1>; + phy-handle =3D <&phy_port0>; + phy-mode =3D "internal"; + }; + + port@2 { + reg =3D <0x2>; + phy-handle =3D <&phy_port1>; + phy-mode =3D "internal"; + }; + + port@3 { + reg =3D <0x3>; + phy-handle =3D <&phy_port2>; + phy-mode =3D "internal"; + }; + + port@4 { + reg =3D <0x4>; + phy-handle =3D <&phy_port3>; + phy-mode =3D "internal"; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + interrupt-parent =3D <&switch10>; + + phy_port0: ethernet-phy@0 { + reg =3D <0x0>; + interrupts =3D <0>; + }; + + phy_port1: ethernet-phy@1 { + reg =3D <0x1>; + interrupts =3D <0>; + }; + + phy_port2: ethernet-phy@2 { + reg =3D <0x2>; + interrupts =3D <0>; + }; + + phy_port3: ethernet-phy@3 { + reg =3D <0x3>; + interrupts =3D <0>; + }; + + phy_port4: ethernet-phy@4 { + reg =3D <0x4>; + interrupts =3D <0>; + }; + }; + }; + }; --=20 2.34.1