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Signed-off-by: Christophe Kerello --- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-= fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm= 32-fmc2-ebi.yaml index 14f1833d37c9..12e6afeceffd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-eb= i.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-eb= i.yaml @@ -23,7 +23,9 @@ maintainers: =20 properties: compatible: - const: st,stm32mp1-fmc2-ebi + enum: + - st,stm32mp1-fmc2-ebi + - st,stm32mp25-fmc2-ebi =20 reg: maxItems: 1 --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CF8E3F9CE; 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charset="utf-8" From: Patrick Delaunay On STM32MP25 SOC, STM32 FMC2 memory controller is in a power domain. Allow a single 'power-domains' entry for STM32 FMC2. Signed-off-by: Patrick Delaunay Signed-off-by: Christophe Kerello --- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-= fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm= 32-fmc2-ebi.yaml index 12e6afeceffd..84ac6f50a6fc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-eb= i.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-eb= i.yaml @@ -36,6 +36,9 @@ properties: resets: maxItems: 1 =20 + power-domains: + maxItems: 1 + "#address-cells": const: 2 =20 --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 835D93F9D5; Mon, 12 Feb 2024 17:50:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707760245; cv=none; b=gS7P+ZBcYY3v3AVtwi5e7vx3Nv4SRAawjvgy0IcPHpwUQt44nMH2xStNIgB/sHL6eS7iWCDnN2GDofN8892zJY/DWa623yDK3KD0db/Zy6R+bO4kWIqMway9KsDz1IEatD1zjkzvxfTzYKpiUtSqA8HzNF1W/op0VUwCE3SDpIQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707760245; c=relaxed/simple; bh=vWxwg4hf+VjPDAyXlyVO+P4o51AzsUHRMVNMPfC34UU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bLcXYKXylwG+AV4yGnnKPG69IZTdYoTYHcfuOytpz0pCKMVksdBWk+MUcW9QdcWGhK8yMM/wG/hdAiMKZqdUI7j+SgSkS6PKPb0rVkoAaX20aFCnHA0fnGVjAZwgnk1UrIwIK/2buPUXSHx49MIxq/ZVPsn3uHaWA55OYedKP6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=mqEayElp; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="mqEayElp" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41CE0Psl006769; Mon, 12 Feb 2024 18:50:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=OFS/WeJd4jRcMqQNxQdciKfLU7r6D+lgxuZRfC3hr4E=; b=mq EayElp2oxnKrSiPjYOaXW9jhDzTOk6b2bPRqaqgT0kEG4BYALw7WyX9N9QjhG1mS X4jniFnY6NZd1sZr+Q2p3YKf7ZTZKXm+HnZYocY0EAyzG2RJew42BMymX2Lk0gv8 z3qMjEdLib0QUZMq7QpnWhMkCaIK9U4qKPg+6hH1QPu7rXXUYSJY7vN0W9ZrA5Fx 2cOcm+Z+VICyqiXaCscdxQoC25Re0zu6TT+B2vjuKufxOc8vlm3SfyVlPyGc4JWi Y1DcichcHIL+xTA/vdbVSEfJkut0cna9kn5WRBWHSnraq3qLFqUvODlFpIiwggme zzv+Bb1ciKmv8Pdh/otg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3w62js7ptu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Feb 2024 18:50:14 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C54CD4002D; Mon, 12 Feb 2024 18:50:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1CB1627F260; Mon, 12 Feb 2024 18:49:22 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:49:21 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 03/12] memory: stm32-fmc2-ebi: add a platform data structure Date: Mon, 12 Feb 2024 18:48:13 +0100 Message-ID: <20240212174822.77734-4-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Before the introduction of MP25 support, let's use a platform data structure for parameters that will differ. The MP1 SOCs have only one signal to manage all the controllers (NWAIT). The MP25 SOC has one RNB signal for the NAND controller and one NWAIT signal for the memory controller. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index 47d0ea5f1616..5f82686689ee 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -132,10 +132,15 @@ enum stm32_fmc2_ebi_cpsize { FMC2_CPSIZE_1024 =3D 1024 }; =20 +struct stm32_fmc2_ebi_data { + bool rnb_for_nand; +}; + struct stm32_fmc2_ebi { struct device *dev; struct clk *clk; struct regmap *regmap; + const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; =20 u32 bcr[FMC2_MAX_EBI_CE]; @@ -988,6 +993,9 @@ static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct s= tm32_fmc2_ebi *ebi) unsigned int cs; u32 bcr; =20 + if (ebi->data->rnb_for_nand) + return false; + for (cs =3D 0; cs < FMC2_MAX_EBI_CE; cs++) { if (!(ebi->bank_assigned & BIT(cs))) continue; @@ -1108,6 +1116,10 @@ static int stm32_fmc2_ebi_probe(struct platform_devi= ce *pdev) =20 ebi->dev =3D dev; =20 + ebi->data =3D of_device_get_match_data(dev); + if (!ebi->data) + return -EINVAL; + ebi->regmap =3D device_node_to_regmap(dev->of_node); if (IS_ERR(ebi->regmap)) return PTR_ERR(ebi->regmap); @@ -1187,8 +1199,15 @@ static int __maybe_unused stm32_fmc2_ebi_resume(stru= ct device *dev) static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, stm32_fmc2_ebi_resume); =20 +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data =3D { + .rnb_for_nand =3D false, +}; + static const struct of_device_id stm32_fmc2_ebi_match[] =3D { - {.compatible =3D "st,stm32mp1-fmc2-ebi"}, + { + .compatible =3D "st,stm32mp1-fmc2-ebi", + .data =3D &stm32_fmc2_ebi_mp1_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8ED33F9D8; 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charset="utf-8" Add MP25 SOC support. RNB and NWAIT signals are differentiated. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index 5f82686689ee..d79dcb6c239a 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -1203,11 +1203,19 @@ static const struct stm32_fmc2_ebi_data stm32_fmc2_= ebi_mp1_data =3D { .rnb_for_nand =3D false, }; =20 +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp25_data =3D { + .rnb_for_nand =3D true, +}; + static const struct of_device_id stm32_fmc2_ebi_match[] =3D { { .compatible =3D "st,stm32mp1-fmc2-ebi", .data =3D &stm32_fmc2_ebi_mp1_data, }, + { + .compatible =3D "st,stm32mp25-fmc2-ebi", + .data =3D &stm32_fmc2_ebi_mp25_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A95373F9CE; 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charset="utf-8" Add the support of the revision 2 of FMC2 IP. - PCSCNTR register has been removed, - CFGR register has been added, - the bit used to enable the IP has moved from BCR1 to CFGR, - the timeout for CEx deassertion has moved from PCSCNTR to BCRx, - the continuous clock enable has moved from BCR1 to CFGR, - the clk divide ratio has moved from BCR1 to CFGR. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 206 +++++++++++++++++++++++++------- 1 file changed, 163 insertions(+), 43 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index d79dcb6c239a..066722274a45 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -20,8 +20,10 @@ #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) #define FMC2_PCSCNTR 0x20 +#define FMC2_CFGR 0x20 #define FMC2_BWTR1 0x104 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) +#define FMC2_VERR 0x3f4 =20 /* Register: FMC2_BCR1 */ #define FMC2_BCR1_CCLKEN BIT(20) @@ -42,6 +44,7 @@ #define FMC2_BCR_ASYNCWAIT BIT(15) #define FMC2_BCR_CPSIZE GENMASK(18, 16) #define FMC2_BCR_CBURSTRW BIT(19) +#define FMC2_BCR_CSCOUNT GENMASK(21, 20) #define FMC2_BCR_NBLSET GENMASK(23, 22) =20 /* Register: FMC2_BTRx/FMC2_BWTRx */ @@ -58,6 +61,15 @@ #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) =20 +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_CLKDIV GENMASK(19, 16) +#define FMC2_CFGR_CCLKEN BIT(20) +#define FMC2_CFGR_FMC2EN BIT(31) + +/* Register: FMC2_VERR */ +#define FMC2_VERR_MAJREV GENMASK(7, 4) +#define FMC2_VERR_MAJREV_2 2 + #define FMC2_MAX_EBI_CE 4 #define FMC2_MAX_BANKS 5 =20 @@ -74,6 +86,11 @@ #define FMC2_BCR_MTYP_PSRAM 0x1 #define FMC2_BCR_MTYP_NOR 0x2 =20 +#define FMC2_BCR_CSCOUNT_0 0x0 +#define FMC2_BCR_CSCOUNT_1 0x1 +#define FMC2_BCR_CSCOUNT_64 0x2 +#define FMC2_BCR_CSCOUNT_256 0x3 + #define FMC2_BXTR_EXTMOD_A 0x0 #define FMC2_BXTR_EXTMOD_B 0x1 #define FMC2_BXTR_EXTMOD_C 0x2 @@ -85,7 +102,7 @@ #define FMC2_BXTR_DATAST_MAX 0xff #define FMC2_BXTR_BUSTURN_MAX 0xf #define FMC2_BXTR_DATAHLD_MAX 0x3 -#define FMC2_BTR_CLKDIV_MAX 0xf +#define FMC2_REG_CLKDIV_MAX 0xf #define FMC2_BTR_DATLAT_MAX 0xf #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff =20 @@ -101,7 +118,8 @@ enum stm32_fmc2_ebi_register_type { FMC2_REG_BCR =3D 1, FMC2_REG_BTR, FMC2_REG_BWTR, - FMC2_REG_PCSCNTR + FMC2_REG_PCSCNTR, + FMC2_REG_CFGR, }; =20 enum stm32_fmc2_ebi_transaction_type { @@ -132,6 +150,13 @@ enum stm32_fmc2_ebi_cpsize { FMC2_CPSIZE_1024 =3D 1024 }; =20 +enum stm32_fmc2_ebi_cscount { + FMC2_CSCOUNT_0 =3D 0, + FMC2_CSCOUNT_1 =3D 1, + FMC2_CSCOUNT_64 =3D 64, + FMC2_CSCOUNT_256 =3D 256 +}; + struct stm32_fmc2_ebi_data { bool rnb_for_nand; }; @@ -142,11 +167,13 @@ struct stm32_fmc2_ebi { struct regmap *regmap; const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; + u8 majrev; =20 u32 bcr[FMC2_MAX_EBI_CE]; u32 btr[FMC2_MAX_EBI_CE]; u32 bwtr[FMC2_MAX_EBI_CE]; u32 pcscntr; + u32 cfgr; }; =20 /* @@ -274,15 +301,29 @@ static int stm32_fmc2_ebi_check_clk_period(struct stm= 32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs) { - u32 bcr, bcr1; + u32 bcr, cfgr; =20 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); - if (cs) - regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); - else - bcr1 =3D bcr; =20 - if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 bcr1; + + if (cs) + regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); + else + bcr1 =3D bcr; + + if (bcr & FMC2_BCR_BURSTEN && + (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) + return 0; + + return -EINVAL; + } + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + + if (bcr & FMC2_BCR_BURSTEN && + (!cs || !(cfgr & FMC2_CFGR_CCLKEN))) return 0; =20 return -EINVAL; @@ -311,15 +352,29 @@ static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm= 32_fmc2_ebi *ebi, int cs, u32 setup) { u32 nb_clk_cycles =3D stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); - u32 bcr, btr, clk_period; + u32 btr, clk_period; =20 - regmap_read(ebi->regmap, FMC2_BCR1, &bcr); - if (bcr & FMC2_BCR1_CCLKEN || !cs) - regmap_read(ebi->regmap, FMC2_BTR1, &btr); - else - regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 bcr; =20 - clk_period =3D FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + regmap_read(ebi->regmap, FMC2_BCR1, &bcr); + if (bcr & FMC2_BCR1_CCLKEN || !cs) + regmap_read(ebi->regmap, FMC2_BTR1, &btr); + else + regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + + clk_period =3D FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + } else { + u32 cfgr; + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + if (cfgr & FMC2_CFGR_CCLKEN) { + clk_period =3D FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; + } else { + regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + clk_period =3D FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + } + } =20 return DIV_ROUND_UP(nb_clk_cycles, clk_period); } @@ -339,6 +394,9 @@ static int stm32_fmc2_ebi_get_reg(int reg_type, int cs,= u32 *reg) case FMC2_REG_PCSCNTR: *reg =3D FMC2_PCSCNTR; break; + case FMC2_REG_CFGR: + *reg =3D FMC2_CFGR; + break; default: return -EINVAL; } @@ -672,10 +730,26 @@ static int stm32_fmc2_ebi_set_clk_period(struct stm32= _fmc2_ebi *ebi, int cs, u32 setup) { u32 val; + u32 reg =3D FMC2_BTR(cs); + u32 mask =3D FMC2_BTR_CLKDIV; =20 - val =3D setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; - val =3D FIELD_PREP(FMC2_BTR_CLKDIV, val); - regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); + if (ebi->majrev >=3D FMC2_VERR_MAJREV_2) { + u32 cfgr; + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + + if (cfgr & FMC2_CFGR_CCLKEN) { + reg =3D FMC2_CFGR; + mask =3D FMC2_CFGR_CLKDIV; + } + } + + val =3D setup ? clamp_val(setup - 1, 1, FMC2_REG_CLKDIV_MAX) : 1; + if (reg =3D=3D FMC2_CFGR) + val =3D FIELD_PREP(FMC2_CFGR_CLKDIV, val); + else + val =3D FIELD_PREP(FMC2_BTR_CLKDIV, val); + regmap_update_bits(ebi->regmap, reg, mask, val); =20 return 0; } @@ -697,27 +771,58 @@ static int stm32_fmc2_ebi_set_max_low_pulse(struct st= m32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs, u32 setup) { - u32 old_val, new_val, pcscntr; + u32 val; + u32 reg =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_PCSCNTR : + FMC2_BCR(cs); + u32 mask =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_PCSCNTR_CSCOUNT : + FMC2_BCR_CSCOUNT; =20 - if (setup < 1) - return 0; + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 old_val, pcscntr; =20 - regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); + if (setup < 1) + return 0; =20 - /* Enable counter for the bank */ - regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, - FMC2_PCSCNTR_CNTBEN(cs), - FMC2_PCSCNTR_CNTBEN(cs)); + regmap_read(ebi->regmap, reg, &pcscntr); =20 - new_val =3D min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); - old_val =3D FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); - if (old_val && new_val > old_val) - /* Keep current counter value */ - return 0; + /* Enable counter for the bank */ + regmap_update_bits(ebi->regmap, reg, + FMC2_PCSCNTR_CNTBEN(cs), + FMC2_PCSCNTR_CNTBEN(cs)); + + val =3D min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); + old_val =3D FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); + if (old_val && val > old_val) + /* Keep current counter value */ + return 0; + + val =3D FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, val); + } else { + if (setup =3D=3D FMC2_CSCOUNT_0) + val =3D FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_0); + else if (setup =3D=3D FMC2_CSCOUNT_1) + val =3D FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_1); + else if (setup <=3D FMC2_CSCOUNT_64) + val =3D FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_64); + else + val =3D FIELD_PREP(FMC2_BCR_CSCOUNT, + FMC2_BCR_CSCOUNT_256); + } + + regmap_update_bits(ebi->regmap, reg, mask, val); =20 - new_val =3D FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); - regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, - FMC2_PCSCNTR_CSCOUNT, new_val); + return 0; +} + +static int stm32_fmc2_ebi_set_cclk(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs, u32 setup) +{ + u32 reg =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1 : FMC2_CFGR; + u32 mask =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_CCLKEN : + FMC2_CFGR_CCLKEN; + + regmap_update_bits(ebi->regmap, reg, mask, setup ? mask : 0); =20 return 0; } @@ -732,10 +837,8 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_p= rops[] =3D { { .name =3D "st,fmc2-ebi-cs-cclk-enable", .bprop =3D true, - .reg_type =3D FMC2_REG_BCR, - .reg_mask =3D FMC2_BCR1_CCLKEN, .check =3D stm32_fmc2_ebi_check_cclk, - .set =3D stm32_fmc2_ebi_set_bit_field, + .set =3D stm32_fmc2_ebi_set_cclk, }, { .name =3D "st,fmc2-ebi-cs-mux-enable", @@ -831,7 +934,7 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_pr= ops[] =3D { }, { .name =3D "st,fmc2-ebi-cs-clk-period-ns", - .reset_val =3D FMC2_BTR_CLKDIV_MAX + 1, + .reset_val =3D FMC2_REG_CLKDIV_MAX + 1, .check =3D stm32_fmc2_ebi_check_clk_period, .calculate =3D stm32_fmc2_ebi_ns_to_clock_cycles, .set =3D stm32_fmc2_ebi_set_clk_period, @@ -959,7 +1062,10 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fm= c2_ebi *ebi) regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); } =20 - regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) + regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); + else + regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); } =20 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) @@ -972,7 +1078,10 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc= 2_ebi *ebi) regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); } =20 - regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) + regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); + else + regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); } =20 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi) @@ -1011,13 +1120,20 @@ static bool stm32_fmc2_ebi_nwait_used_by_ctrls(stru= ct stm32_fmc2_ebi *ebi) =20 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) { - regmap_update_bits(ebi->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + u32 reg =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? 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charset="utf-8" The FMC2 revision 2 supports security and isolation compliant with the Resource Isolation Framework (RIF). From RIF point of view, the FMC2 is composed of several independent resources, listed below, which can be assigned to different security and compartment domains: - 0: Common FMC_CFGR register. - 1: EBI controller for Chip Select 1. - 2: EBI controller for Chip Select 2. - 3: EBI controller for Chip Select 3. - 4: EBI controller for Chip Select 4. - 5: NAND controller. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 178 +++++++++++++++++++++++++++++++- 1 file changed, 174 insertions(+), 4 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index 066722274a45..04248c15832f 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -21,8 +21,14 @@ #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) #define FMC2_PCSCNTR 0x20 #define FMC2_CFGR 0x20 +#define FMC2_SR 0x84 #define FMC2_BWTR1 0x104 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) +#define FMC2_SECCFGR 0x300 +#define FMC2_CIDCFGR0 0x30c +#define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0) +#define FMC2_SEMCR0 0x310 +#define FMC2_SEMCR(x) ((x) * 0x8 + FMC2_SEMCR0) #define FMC2_VERR 0x3f4 =20 /* Register: FMC2_BCR1 */ @@ -66,12 +72,27 @@ #define FMC2_CFGR_CCLKEN BIT(20) #define FMC2_CFGR_FMC2EN BIT(31) =20 +/* Register: FMC2_SR */ +#define FMC2_SR_ISOST GENMASK(1, 0) + +/* Register: FMC2_CIDCFGR */ +#define FMC2_CIDCFGR_CFEN BIT(0) +#define FMC2_CIDCFGR_SEMEN BIT(1) +#define FMC2_CIDCFGR_SCID GENMASK(6, 4) +#define FMC2_CIDCFGR_SEMWLC1 BIT(17) + +/* Register: FMC2_SEMCR */ +#define FMC2_SEMCR_SEM_MUTEX BIT(0) +#define FMC2_SEMCR_SEMCID GENMASK(7, 5) + /* Register: FMC2_VERR */ #define FMC2_VERR_MAJREV GENMASK(7, 4) #define FMC2_VERR_MAJREV_2 2 =20 #define FMC2_MAX_EBI_CE 4 #define FMC2_MAX_BANKS 5 +#define FMC2_MAX_RESOURCES 6 +#define FMC2_CID1 1 =20 #define FMC2_BCR_CPSIZE_0 0x0 #define FMC2_BCR_CPSIZE_128 0x1 @@ -167,7 +188,9 @@ struct stm32_fmc2_ebi { struct regmap *regmap; const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; + u8 sem_taken; u8 majrev; + bool access_granted; =20 u32 bcr[FMC2_MAX_EBI_CE]; u32 btr[FMC2_MAX_EBI_CE]; @@ -733,6 +756,11 @@ static int stm32_fmc2_ebi_set_clk_period(struct stm32_= fmc2_ebi *ebi, u32 reg =3D FMC2_BTR(cs); u32 mask =3D FMC2_BTR_CLKDIV; =20 + if (!ebi->access_granted) { + dev_err(ebi->dev, "CFGR access forbidden\n"); + return -EACCES; + } + if (ebi->majrev >=3D FMC2_VERR_MAJREV_2) { u32 cfgr; =20 @@ -822,6 +850,11 @@ static int stm32_fmc2_ebi_set_cclk(struct stm32_fmc2_e= bi *ebi, u32 mask =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_CCLKEN : FMC2_CFGR_CCLKEN; =20 + if (!ebi->access_granted) { + dev_err(ebi->dev, "CFGR access forbidden\n"); + return -EACCES; + } + regmap_update_bits(ebi->regmap, reg, mask, setup ? mask : 0); =20 return 0; @@ -990,6 +1023,107 @@ static const struct stm32_fmc2_prop stm32_fmc2_child= _props[] =3D { }, }; =20 +static int stm32_fmc2_ebi_check_rif(struct stm32_fmc2_ebi *ebi, u32 resour= ce) +{ + u32 seccfgr, cidcfgr, semcr; + int cid; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return 0; + + if (resource >=3D FMC2_MAX_RESOURCES) + return -EINVAL; + + regmap_read(ebi->regmap, FMC2_SECCFGR, &seccfgr); + if (seccfgr & BIT(resource)) { + if (resource) + dev_err(ebi->dev, "resource %d is configured as secure\n", + resource); + + return -EACCES; + } + + regmap_read(ebi->regmap, FMC2_CIDCFGR(resource), &cidcfgr); + if (!(cidcfgr & FMC2_CIDCFGR_CFEN)) + /* CID filtering is turned off: access granted */ + return 0; + + if (!(cidcfgr & FMC2_CIDCFGR_SEMEN)) { + /* Static CID mode */ + cid =3D FIELD_GET(FMC2_CIDCFGR_SCID, cidcfgr); + if (cid !=3D FMC2_CID1) { + if (resource) + dev_err(ebi->dev, "static CID%d set for resource %d\n", + cid, resource); + + return -EACCES; + } + + return 0; + } + + /* Pass-list with semaphore mode */ + if (!(cidcfgr & FMC2_CIDCFGR_SEMWLC1)) { + if (resource) + dev_err(ebi->dev, "CID1 is block-listed for resource %d\n", + resource); + + return -EACCES; + } + + regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); + if (!(semcr & FMC2_SEMCR_SEM_MUTEX)) { + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); + regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); + } + + cid =3D FIELD_GET(FMC2_SEMCR_SEMCID, semcr); + if (cid !=3D FMC2_CID1) { + if (resource) + dev_err(ebi->dev, "resource %d is already used by CID%d\n", + resource, cid); + + return -EACCES; + } + + ebi->sem_taken |=3D BIT(resource); + + return 0; +} + +static void stm32_fmc2_ebi_put_sems(struct stm32_fmc2_ebi *ebi) +{ + unsigned int resource; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return; + + for (resource =3D 0; resource < FMC2_MAX_RESOURCES; resource++) { + if (!(ebi->sem_taken & BIT(resource))) + continue; + + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, 0); + } +} + +static void stm32_fmc2_ebi_get_sems(struct stm32_fmc2_ebi *ebi) +{ + unsigned int resource; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return; + + for (resource =3D 0; resource < FMC2_MAX_RESOURCES; resource++) { + if (!(ebi->sem_taken & BIT(resource))) + continue; + + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); + } +} + static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, struct device_node *dev_node, const struct stm32_fmc2_prop *prop, @@ -1057,6 +1191,9 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fm= c2_ebi *ebi) unsigned int cs; =20 for (cs =3D 0; cs < FMC2_MAX_EBI_CE; cs++) { + if (!(ebi->bank_assigned & BIT(cs))) + continue; + regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); @@ -1064,7 +1201,7 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fm= c2_ebi *ebi) =20 if (ebi->majrev < FMC2_VERR_MAJREV_2) regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); - else + else if (ebi->access_granted) regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); } =20 @@ -1073,6 +1210,9 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc= 2_ebi *ebi) unsigned int cs; =20 for (cs =3D 0; cs < FMC2_MAX_EBI_CE; cs++) { + if (!(ebi->bank_assigned & BIT(cs))) + continue; + regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]); regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]); regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); @@ -1080,7 +1220,7 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc= 2_ebi *ebi) =20 if (ebi->majrev < FMC2_VERR_MAJREV_2) regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); - else + else if (ebi->access_granted) regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); } =20 @@ -1124,7 +1264,8 @@ static void stm32_fmc2_ebi_enable(struct stm32_fmc2_e= bi *ebi) u32 mask =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : FMC2_CFGR_FMC2EN; =20 - regmap_update_bits(ebi->regmap, reg, mask, mask); + if (ebi->access_granted) + regmap_update_bits(ebi->regmap, reg, mask, mask); } =20 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) @@ -1133,7 +1274,8 @@ static void stm32_fmc2_ebi_disable(struct stm32_fmc2_= ebi *ebi) u32 mask =3D ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : FMC2_CFGR_FMC2EN; =20 - regmap_update_bits(ebi->regmap, reg, mask, 0); + if (ebi->access_granted) + regmap_update_bits(ebi->regmap, reg, mask, 0); } =20 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, @@ -1190,6 +1332,13 @@ static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2= _ebi *ebi) return -EINVAL; } =20 + ret =3D stm32_fmc2_ebi_check_rif(ebi, bank + 1); + if (ret) { + dev_err(dev, "bank access failed: %d\n", bank); + of_node_put(child); + return ret; + } + if (bank < FMC2_MAX_EBI_CE) { ret =3D stm32_fmc2_ebi_setup_cs(ebi, child, bank); if (ret) { @@ -1261,6 +1410,23 @@ static int stm32_fmc2_ebi_probe(struct platform_devi= ce *pdev) regmap_read(ebi->regmap, FMC2_VERR, &verr); ebi->majrev =3D FIELD_GET(FMC2_VERR_MAJREV, verr); =20 + /* Check if CFGR register can be modified */ + ret =3D stm32_fmc2_ebi_check_rif(ebi, 0); + if (!ret) + ebi->access_granted =3D true; + + /* In case of CFGR is secure, just check that the FMC2 is enabled */ + if (!ebi->access_granted) { + u32 sr; + + regmap_read(ebi->regmap, FMC2_SR, &sr); + if (sr & FMC2_SR_ISOST) { + dev_err(dev, "FMC2 is not ready to be used.\n"); + ret =3D -EACCES; + goto err_release; + } + } + ret =3D stm32_fmc2_ebi_parse_dt(ebi); if (ret) goto err_release; @@ -1273,6 +1439,7 @@ static int stm32_fmc2_ebi_probe(struct platform_devic= e *pdev) err_release: stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); =20 return ret; @@ -1285,6 +1452,7 @@ static void stm32_fmc2_ebi_remove(struct platform_dev= ice *pdev) of_platform_depopulate(&pdev->dev); stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); } =20 @@ -1293,6 +1461,7 @@ static int __maybe_unused stm32_fmc2_ebi_suspend(stru= ct device *dev) struct stm32_fmc2_ebi *ebi =3D dev_get_drvdata(dev); =20 stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); pinctrl_pm_select_sleep_state(dev); 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charset="utf-8" Add runtime PM support in FMC2 ebi driver to be able to manage GENPD support when it will be enabled. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 40 ++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-eb= i.c index 04248c15832f..8c30e56be3b0 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include =20 @@ -1381,6 +1382,7 @@ static int stm32_fmc2_ebi_probe(struct platform_devic= e *pdev) return -ENOMEM; =20 ebi->dev =3D dev; + platform_set_drvdata(pdev, ebi); =20 ebi->data =3D of_device_get_match_data(dev); if (!ebi->data) @@ -1398,10 +1400,14 @@ static int stm32_fmc2_ebi_probe(struct platform_dev= ice *pdev) if (PTR_ERR(rstc) =3D=3D -EPROBE_DEFER) return -EPROBE_DEFER; =20 - ret =3D clk_prepare_enable(ebi->clk); + ret =3D devm_pm_runtime_enable(dev); if (ret) return ret; =20 + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); @@ -1432,7 +1438,6 @@ static int stm32_fmc2_ebi_probe(struct platform_devic= e *pdev) goto err_release; =20 stm32_fmc2_ebi_save_setup(ebi); - platform_set_drvdata(pdev, ebi); =20 return 0; =20 @@ -1440,7 +1445,7 @@ static int stm32_fmc2_ebi_probe(struct platform_devic= e *pdev) stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); - clk_disable_unprepare(ebi->clk); + pm_runtime_put_sync_suspend(dev); =20 return ret; } @@ -1453,7 +1458,23 @@ static void stm32_fmc2_ebi_remove(struct platform_de= vice *pdev) stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); + pm_runtime_put_sync_suspend(&pdev->dev); +} + +static int __maybe_unused stm32_fmc2_ebi_runtime_suspend(struct device *de= v) +{ + struct stm32_fmc2_ebi *ebi =3D dev_get_drvdata(dev); + clk_disable_unprepare(ebi->clk); + + return 0; +} + +static int __maybe_unused stm32_fmc2_ebi_runtime_resume(struct device *dev) +{ + struct stm32_fmc2_ebi *ebi =3D dev_get_drvdata(dev); + + return clk_prepare_enable(ebi->clk); } =20 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) @@ -1462,7 +1483,7 @@ static int __maybe_unused stm32_fmc2_ebi_suspend(stru= ct device *dev) =20 stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); - clk_disable_unprepare(ebi->clk); + pm_runtime_put_sync_suspend(dev); pinctrl_pm_select_sleep_state(dev); =20 return 0; @@ -1475,8 +1496,8 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struc= t device *dev) =20 pinctrl_pm_select_default_state(dev); =20 - ret =3D clk_prepare_enable(ebi->clk); - if (ret) + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) return ret; =20 stm32_fmc2_ebi_get_sems(ebi); @@ -1486,8 +1507,11 @@ static int __maybe_unused stm32_fmc2_ebi_resume(stru= ct device *dev) return 0; } =20 -static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, - stm32_fmc2_ebi_resume); +static const struct dev_pm_ops stm32_fmc2_ebi_pm_ops =3D { + SET_RUNTIME_PM_OPS(stm32_fmc2_ebi_runtime_suspend, + stm32_fmc2_ebi_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(stm32_fmc2_ebi_suspend, stm32_fmc2_ebi_resume) +}; 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charset="utf-8" Add 2 new compatible strings to support MP25 SOC. MP25 SOC supports up to 4 chip select. Signed-off-by: Christophe Kerello --- .../bindings/mtd/st,stm32-fmc2-nand.yaml | 58 ++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml = b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml index e72cb5bacaf0..33a753c8877b 100644 --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml @@ -14,10 +14,12 @@ properties: enum: - st,stm32mp15-fmc2 - st,stm32mp1-fmc2-nfc + - st,stm32mp25-fmc2 + - st,stm32mp25-fmc2-nfc =20 reg: minItems: 6 - maxItems: 7 + maxItems: 13 =20 interrupts: maxItems: 1 @@ -92,6 +94,60 @@ allOf: - description: Chip select 1 command - description: Chip select 1 address space =20 + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2 + then: + properties: + reg: + items: + - description: Registers + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + required: + - clocks + + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2-nfc + then: + properties: + reg: + items: + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + required: - compatible - reg --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9AAA40C09; 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charset="utf-8" use dma_get_slave_caps API to get the max burst size of a DMA channel. For MP1 SOCs, MDMA is used and the max burst size is 128. For MP25 SOC, DMA3 is used and the max burst size is 64. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 29 +++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index 88811139aaf5..a7db7b675514 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -264,6 +264,8 @@ struct stm32_fmc2_nfc { struct sg_table dma_ecc_sg; u8 *ecc_buf; int dma_ecc_len; + u32 tx_dma_max_burst; + u32 rx_dma_max_burst; =20 struct completion complete; struct completion dma_data_complete; @@ -347,20 +349,26 @@ static int stm32_fmc2_nfc_select_chip(struct nand_chi= p *chip, int chipnr) stm32_fmc2_nfc_setup(chip); stm32_fmc2_nfc_timings_init(chip); =20 - if (nfc->dma_tx_ch && nfc->dma_rx_ch) { + if (nfc->dma_tx_ch) { memset(&dma_cfg, 0, sizeof(dma_cfg)); - dma_cfg.src_addr =3D nfc->data_phys_addr[nfc->cs_sel]; dma_cfg.dst_addr =3D nfc->data_phys_addr[nfc->cs_sel]; - dma_cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; dma_cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_cfg.src_maxburst =3D 32; - dma_cfg.dst_maxburst =3D 32; + dma_cfg.dst_maxburst =3D nfc->tx_dma_max_burst / + dma_cfg.dst_addr_width; =20 ret =3D dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg); if (ret) { dev_err(nfc->dev, "tx DMA engine slave config failed\n"); return ret; } + } + + if (nfc->dma_rx_ch) { + memset(&dma_cfg, 0, sizeof(dma_cfg)); + dma_cfg.src_addr =3D nfc->data_phys_addr[nfc->cs_sel]; + dma_cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_cfg.src_maxburst =3D nfc->rx_dma_max_burst / + dma_cfg.src_addr_width; =20 ret =3D dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg); if (ret) { @@ -1545,6 +1553,7 @@ static int stm32_fmc2_nfc_setup_interface(struct nand= _chip *chip, int chipnr, =20 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) { + struct dma_slave_caps caps; int ret =3D 0; =20 nfc->dma_tx_ch =3D dma_request_chan(nfc->dev, "tx"); @@ -1557,6 +1566,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc= 2_nfc *nfc) goto err_dma; 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charset="utf-8" Before the introduction of MP25 SOC, let's use a platform data structure for parameters that will differ (number of chip select). The FMC2 NAND can support up to 4 chips select. On MP1 SOCs, only 2 chip select are available. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 32 +++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index a7db7b675514..c5bdb43f7221 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,7 @@ #define FMC2_MAX_SG 16 =20 /* Max chip enable */ -#define FMC2_MAX_CE 2 +#define FMC2_MAX_CE 4 =20 /* Max ECC buffer length */ #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) @@ -243,6 +244,10 @@ static inline struct stm32_fmc2_nand *to_fmc2_nand(str= uct nand_chip *chip) return container_of(chip, struct stm32_fmc2_nand, chip); } =20 +struct stm32_fmc2_nfc_data { + int max_ncs; +}; + struct stm32_fmc2_nfc { struct nand_controller base; struct stm32_fmc2_nand nand; @@ -256,6 +261,7 @@ struct stm32_fmc2_nfc { phys_addr_t data_phys_addr[FMC2_MAX_CE]; struct clk *clk; u8 irq_state; + const struct stm32_fmc2_nfc_data *data; =20 struct dma_chan *dma_tx_ch; struct dma_chan *dma_rx_ch; @@ -1809,7 +1815,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fm= c2_nfc *nfc, return ret; } =20 - if (cs >=3D FMC2_MAX_CE) { + if (cs >=3D nfc->data->max_ncs) { dev_err(nfc->dev, "invalid reg value: %d\n", cs); return -EINVAL; } @@ -1915,6 +1921,10 @@ static int stm32_fmc2_nfc_probe(struct platform_devi= ce *pdev) nand_controller_init(&nfc->base); nfc->base.ops =3D &stm32_fmc2_nfc_controller_ops; =20 + nfc->data =3D of_device_get_match_data(dev); + if (!nfc->data) + return -EINVAL; + ret =3D stm32_fmc2_nfc_set_cdev(nfc); if (ret) return ret; @@ -1936,7 +1946,7 @@ static int stm32_fmc2_nfc_probe(struct platform_devic= e *pdev) if (nfc->dev =3D=3D nfc->cdev) start_region =3D 1; =20 - for (chip_cs =3D 0, mem_region =3D start_region; chip_cs < FMC2_MAX_CE; + for (chip_cs =3D 0, mem_region =3D start_region; chip_cs < nfc->data->max= _ncs; chip_cs++, mem_region +=3D 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -2092,7 +2102,7 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struc= t device *dev) =20 stm32_fmc2_nfc_wp_disable(nand); =20 - for (chip_cs =3D 0; chip_cs < FMC2_MAX_CE; chip_cs++) { + for (chip_cs =3D 0; chip_cs < nfc->data->max_ncs; chip_cs++) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; =20 @@ -2105,9 +2115,19 @@ static int __maybe_unused stm32_fmc2_nfc_resume(stru= ct device *dev) static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, stm32_fmc2_nfc_resume); =20 +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data =3D { + .max_ncs =3D 2, +}; + static const struct of_device_id stm32_fmc2_nfc_match[] =3D { - {.compatible =3D "st,stm32mp15-fmc2"}, - {.compatible =3D "st,stm32mp1-fmc2-nfc"}, + { + .compatible =3D "st,stm32mp15-fmc2", + .data =3D &stm32_fmc2_nfc_mp1_data, + }, + { + .compatible =3D "st,stm32mp1-fmc2-nfc", + .data =3D &stm32_fmc2_nfc_mp1_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); --=20 2.25.1 From nobody Sun Feb 8 12:35:21 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F208D47A5C; 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charset="utf-8" Add MP25 SOC support (4 chip select are available). Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index c5bdb43f7221..d71ec12cd5b1 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1878,11 +1878,14 @@ static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc= 2_nfc *nfc) struct device *dev =3D nfc->dev; bool ebi_found =3D false; =20 - if (dev->parent && of_device_is_compatible(dev->parent->of_node, - "st,stm32mp1-fmc2-ebi")) + if (dev->parent && (of_device_is_compatible(dev->parent->of_node, + "st,stm32mp1-fmc2-ebi") || + of_device_is_compatible(dev->parent->of_node, + "st,stm32mp25-fmc2-ebi"))) ebi_found =3D true; =20 - if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) { + if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc") || + of_device_is_compatible(dev->of_node, "st,stm32mp25-fmc2-nfc")) { if (ebi_found) { nfc->cdev =3D dev->parent; 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Mon, 12 Feb 2024 18:52:23 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D9C8740044; Mon, 12 Feb 2024 18:52:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3B9C9257A8E; Mon, 12 Feb 2024 18:51:37 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:51:36 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 12/12] mtd: rawnand: stm32_fmc2: update the driver to support revision 2 Date: Mon, 12 Feb 2024 18:48:22 +0100 Message-ID: <20240212174822.77734-13-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add the support of the revision 2 of FMC2 IP. For the NAND controller, the bit used to enable the IP has moved. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index d71ec12cd5b1..877255b0d0fc 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -54,6 +54,7 @@ =20 /* FMC2 Controller Registers */ #define FMC2_BCR1 0x0 +#define FMC2_CFGR 0x20 #define FMC2_PCR 0x80 #define FMC2_SR 0x84 #define FMC2_PMEM 0x88 @@ -83,10 +84,14 @@ #define FMC2_BCHDSR2 0x284 #define FMC2_BCHDSR3 0x288 #define FMC2_BCHDSR4 0x28c +#define FMC2_VERR 0x3f4 =20 /* Register: FMC2_BCR1 */ #define FMC2_BCR1_FMC2EN BIT(31) =20 +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_FMC2EN BIT(31) + /* Register: FMC2_PCR */ #define FMC2_PCR_PWAITEN BIT(1) #define FMC2_PCR_PBKEN BIT(2) @@ -208,6 +213,10 @@ #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) =20 +/* Register: FMC2_VERR */ +#define FMC2_VERR_MAJREV GENMASK(7, 4) +#define FMC2_VERR_MAJREV_2 2 + enum stm32_fmc2_ecc { FMC2_ECC_HAM =3D 1, FMC2_ECC_BCH4 =3D 4, @@ -1397,9 +1406,20 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nf= c *nfc) pcr |=3D FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); =20 /* Enable FMC2 controller */ - if (nfc->dev =3D=3D nfc->cdev) - regmap_update_bits(nfc->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + if (nfc->dev =3D=3D nfc->cdev) { + u32 verr; + u8 majrev; + + regmap_read(nfc->regmap, FMC2_VERR, &verr); + majrev =3D FIELD_GET(FMC2_VERR_MAJREV, verr); + + if (majrev < FMC2_VERR_MAJREV_2) + regmap_update_bits(nfc->regmap, FMC2_BCR1, + FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + else + regmap_update_bits(nfc->regmap, FMC2_CFGR, + FMC2_CFGR_FMC2EN, FMC2_CFGR_FMC2EN); + } =20 regmap_write(nfc->regmap, FMC2_PCR, pcr); regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT); --=20 2.25.1