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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240212-fencei-v11-1-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=639; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=23qauOezLdGd/qvi+eoGfAUmo21GdLnF/O1XuhUSBhA=; b=3fk1hPn8uk0LHRB8yl3Y0RYndhVQhDbBlNi5Ce1BSrXXKhsMTW4JUlwl8LFpuZbLYzru9RLEH y8tsCF/wTQcAF+CZe6nMI0QqK6iZZlmz8RM55ve7LYSJeVzXo12jwfv X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= This include is not used. Remove it to avoid a circular dependency in the next patch in the series. Signed-off-by: Charlie Jenkins Reviewed-by: Samuel Holland --- arch/riscv/include/asm/irqflags.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irq= flags.h index 08d4d6a5b7e9..6fd8cbfcfcc7 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -7,7 +7,6 @@ #ifndef _ASM_RISCV_IRQFLAGS_H #define _ASM_RISCV_IRQFLAGS_H =20 -#include #include =20 /* read interrupt enabled status */ --=20 2.43.0 From nobody Sat Sep 7 23:47:16 2024 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C976850246 for ; Mon, 12 Feb 2024 23:36:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707780999; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240212-fencei-v11-2-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=11568; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=TKCt+8IZ9ruFBnTgfJxRkDydxZvQ/nlPrN0EVMID0+A=; b=mXok/mb98DSDzfQSJsMFWzjeOw67T47xCMxZXKsQOL+eBtqj6VQDjbSmupvqXHeKGrQt9DCXz RTyTXGZNotGBvzga7ax/Xk2AcIKACM5dP0xS8ZpYk4cSQsMp40CZquV X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable optimization of cross modifying code. This prctl enables userspace code to use icache flushing instructions such as fence.i with the guarantee that the icache will continue to be clean after thread migration. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 12 +++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++ arch/riscv/mm/cacheflush.c | 105 +++++++++++++++++++++++++++++++++= ++++ arch/riscv/mm/context.c | 18 +++++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 7 files changed, 167 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index a8509cc31ab2..46c5c3b91165 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -69,6 +69,7 @@ #endif =20 #ifndef __ASSEMBLY__ +#include =20 struct task_struct; struct pt_regs; @@ -123,6 +124,14 @@ struct thread_struct { struct __riscv_v_ext_state vstate; unsigned long align_ctl; struct __riscv_v_ext_state kernel_vstate; +#ifdef CONFIG_SMP + /* A local icache flush is needed before user execution can resume on one= of these cpus. */ + cpumask_t icache_stale_mask; + /* Regardless of the icache_stale_mask, flush the icache on migration */ + bool force_icache_flush; + /* A forced icache flush is not needed if migrating to the previous cpu. = */ + unsigned int prev_cpu; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -184,6 +193,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, uns= igned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) =20 +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(= arg1, arg2) +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per= _thread); + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7efdb0584d47..7594df37cc9f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -72,14 +73,36 @@ static __always_inline bool has_fpu(void) { return fals= e; } extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 +static inline bool switch_to_should_flush_icache(struct task_struct *task) +{ +#ifdef CONFIG_SMP + bool stale_mm =3D task->mm && task->mm->context.force_icache_flush; + bool stale_thread =3D task->thread.force_icache_flush; + bool thread_migrated =3D smp_processor_id() !=3D task->thread.prev_cpu; + + return thread_migrated && (stale_mm || stale_thread); +#else + return false; +#endif +} + +#ifdef CONFIG_SMP +#define __set_prev_cpu(thread) ((thread).prev_cpu =3D smp_processor_id()) +#else +#define __set_prev_cpu(thread) +#endif + #define switch_to(prev, next, last) \ do { \ struct task_struct *__prev =3D (prev); \ struct task_struct *__next =3D (next); \ + __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (switch_to_should_flush_icache(__next)) \ + local_flush_icache_all(); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 55a34f2020a8..6513a0ab8655 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include =20 @@ -152,3 +153,107 @@ void __init riscv_init_cbo_blocksizes(void) if (cboz_block_size) riscv_cboz_block_size =3D cboz_block_size; } + +/** + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructi= ons in + * userspace. + * @ctx: Set the type of icache flushing instructions permitted/prohibited= in + * userspace. Supported values described below. + * + * Supported values for ctx: + * + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in user space. + * + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in user space. All thre= ads in + * a process will be affected when ``scope =3D=3D PR_RISCV_SCOPE_PER_PRO= CESS``. + * Therefore, caution must be taken; use this flag only when you can gua= rantee + * that no thread in the process will emit fence.i from this point onwar= d. + * + * @scope: Set scope of where icache flushing instructions are allowed to = be + * emitted. Supported values described below. + * + * Supported values for scope: + * + * * %PR_RISCV_SCOPE_PER_PROCESS: Ensure the icache of any thread in this = process + * is coherent with instruction storage upon + * migration. + * + * * %PR_RISCV_SCOPE_PER_THREAD: Ensure the icache of the current thread is + * coherent with instruction storage upon + * migration. + * + * When ``scope =3D=3D PR_RISCV_SCOPE_PER_PROCESS``, all threads in the pr= ocess are + * permitted to emit icache flushing instructions. Whenever any thread in = the + * process is migrated, the corresponding hart's icache will be guaranteed= to be + * consistent with instruction storage. This does not enforce any guarante= es + * outside of migration. If a thread modifies an instruction that another = thread + * may attempt to execute, the other thread must still emit an icache flus= hing + * instruction before attempting to execute the potentially modified + * instruction. This must be performed by the user-space program. + * + * In per-thread context (eg. ``scope =3D=3D PR_RISCV_SCOPE_PER_THREAD``) = only the + * thread calling this function is permitted to emit icache flushing + * instructions. When the thread is migrated, the corresponding hart's ica= che + * will be guaranteed to be consistent with instruction storage. + * + * On kernels configured without SMP, this function is a nop as migrations + * across harts will not occur. + */ +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope) +{ +#ifdef CONFIG_SMP + switch (ctx) { + case PR_RISCV_CTX_SW_FENCEI_ON: + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + current->mm->context.force_icache_flush =3D true; + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush =3D true; + break; + default: + return -EINVAL; + } + break; + case PR_RISCV_CTX_SW_FENCEI_OFF: + cpumask_t *mask; + + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + bool stale_cpu; + + current->mm->context.force_icache_flush =3D false; + + /* + * Mark every other hart's icache as needing a flush for + * this MM. Maintain the previous value of the current + * cpu to handle the case when this function is called + * concurrently on different harts. + */ + mask =3D ¤t->mm->context.icache_stale_mask; + stale_cpu =3D cpumask_test_cpu(smp_processor_id(), mask); + + cpumask_setall(mask); + assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale= _cpu); + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush =3D false; + + /* + * Mark every other hart's icache as needing a flush for + * this thread. + */ + mask =3D ¤t->thread.icache_stale_mask; + cpumask_setall(mask); + cpumask_clear_cpu(smp_processor_id(), mask); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } +#endif + return 0; +} diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..2eb13b89cced 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #ifdef CONFIG_MMU =20 @@ -297,21 +298,28 @@ static inline void set_mm(struct mm_struct *prev, * * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu, + struct task_struct *task) { #ifdef CONFIG_SMP cpumask_t *mask =3D &mm->context.icache_stale_mask; =20 - if (cpumask_test_cpu(cpu, mask)) { + if (cpumask_test_and_clear_cpu(cpu, mask) || + (task && cpumask_test_and_clear_cpu(cpu, &task->thread.icache_stale_m= ask))) { cpumask_clear_cpu(cpu, mask); + /* * Ensure the remote hart's writes are visible to this hart. * This pairs with a barrier in flush_icache_mm. */ smp_mb(); - local_flush_icache_all(); - } =20 + /* + * If cache will be flushed in switch_to, no need to flush here. + */ + if (!(task && switch_to_should_flush_icache(task))) + local_flush_icache_all(); + } #endif } =20 @@ -332,5 +340,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct= *next, =20 set_mm(prev, next, cpu); =20 - flush_icache_deferred(next, cpu); + flush_icache_deferred(next, cpu, task); } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..524d546d697b 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,10 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f =20 +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 +# define PR_RISCV_CTX_SW_FENCEI_ON 0 +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 +# define PR_RISCV_SCOPE_PER_PROCESS 0 +# define PR_RISCV_SCOPE_PER_THREAD 1 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index e219fcfa112d..69afdd8b430f 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,9 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef RISCV_SET_ICACHE_FLUSH_CTX +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) +#endif =20 /* * this is where the system-wide overflow UID and GID are defined, for @@ -2743,6 +2746,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, ar= g2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error =3D RISCV_V_GET_CONTROL(); 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Mon, 12 Feb 2024 15:36:34 -0800 (PST) From: Charlie Jenkins Date: Mon, 12 Feb 2024 15:36:28 -0800 Subject: [PATCH v11 3/4] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240212-fencei-v11-3-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=4601; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=h5IjKPzf39ifTQj2Z0xAqATqlmjtpC61zariLMJKI0A=; b=vJDezW43wOShNn6FckmWv22EMLkCD0nM7x+UHVRHI3N8+Z+FmM5YXkveip/sA8wovq7Ws6bKO BP+ZSS/Sc9LDs5LKYhUoWvOeHEH9nKsMNE7+MESOdiw9PK7Yb73MHqV X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++= ++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 99 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/= cmodx.rst new file mode 100644 index 000000000000..1c0ca06b6c97 --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V L= inux +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +CMODX is a programming technique where a program executes instructions tha= t were +modified by the program itself. Instruction storage and the instruction ca= che +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefo= re, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new har= t. If +migration occurs after the userspace synchronized the icache and instructi= on +storage with fence.i, the icache on the new hart will no longer be clean. = This +is due to the behavior of fence.i only affecting the hart that it is calle= d on. +Thus, the hart that the task has been migrated to may not have synchronized +instruction storage and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() sys= call, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The p= rctl +changes the Linux ABI to allow userspace to emit icache flushing operation= s. + +As an aside, "deferred" icache flushes can sometimes be triggered in the k= ernel. +At the time of writing, this only occurs during the riscv_flush_icache() s= yscall +and when the kernel uses copy_to_user_page(). These deferred flushes happe= n only +when the memory map being used by a hart changes. If the prctl() context c= aused +an icache flush, this deferred icache flush will be skipped as it is redun= dant. +Therefore, there will be no additional flush when using the riscv_flush_ic= ache() +syscall inside of the prctl() context. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument.= The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. T= he +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a= zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value =3D get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, PR_RISCV= _SCOPE_PER_PROCESS); + modify_instruction(); + // Call prctl after final fence.i is called in process + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_OFF, PR_RISCV_CTX_SW_FENCEI, PR_RISC= V_SCOPE_PER_PROCESS); + + value =3D get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/= index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx =20 features =20 --=20 2.43.0 From nobody Sat Sep 7 23:47:16 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 685F651C31 for ; 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a=ed25519-sha256; t=1707780989; l=1797; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=teNltxEe5ATnvQPKeLgPp6b3k0t1rOkLmnDUUB6OJdA=; b=EiKlcL1ulk4DvUiCSUgvbFtR389U08UGs9J+Mx1NjicMNyA7ytjbg4bgirWaWZZtdE5HGgwHU EVUxZnpx4C/A+JHiRo45OTnP3oYSGtoMtT2ZFchA7WKDMysLkz7sWPx X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Standardize an assign_cpu function for cpumasks. Signed-off-by: Charlie Jenkins --- arch/riscv/mm/cacheflush.c | 2 +- include/linux/cpumask.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6513a0ab8655..d10c2cba8aff 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -234,7 +234,7 @@ int riscv_set_icache_flush_ctx(unsigned long ctx, unsig= ned long scope) stale_cpu =3D cpumask_test_cpu(smp_processor_id(), mask); =20 cpumask_setall(mask); - assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale= _cpu); + cpumask_assign_cpu(smp_processor_id(), mask, stale_cpu); break; case PR_RISCV_SCOPE_PER_THREAD: current->thread.force_icache_flush =3D false; diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index cfb545841a2c..1b85e09c4ba5 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -492,6 +492,22 @@ static __always_inline void __cpumask_clear_cpu(int cp= u, struct cpumask *dstp) __clear_bit(cpumask_check(cpu), cpumask_bits(dstp)); } =20 +/** + * cpumask_assign_cpu - assign a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @dstp: the cpumask pointer + * @bool: the value to assign + */ +static __always_inline void cpumask_assign_cpu(int cpu, struct cpumask *ds= tp, bool value) +{ + assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + +static __always_inline void __cpumask_assign_cpu(int cpu, struct cpumask *= dstp, bool value) +{ + __assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + /** * cpumask_test_cpu - test for a cpu in a cpumask * @cpu: cpu number (< nr_cpu_ids) --=20 2.43.0