From nobody Fri Dec 26 21:39:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA1AA4C600; Sun, 11 Feb 2024 08:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707640239; cv=none; b=bsHlJm0XugTN9Iw+UBqMnI0sHkjvvbQlV2vfPQ89hi/W5ecA41KdCHPRdqq22yQL52u+Aa9TJS+eXtdFeGXprCUHX+a8gF9nCmvSsw5Nfg/STG9JkiuC2tF9i7spXhAJJKyLl2XaWI/h0OReMKdmneMCmLo8t1TbERwinIpOIjw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707640239; c=relaxed/simple; bh=P5YLYD6H2barwQbUJyuy1ic5ANsbxNgTsIlabr1argw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QxMIkW6Z08g5jXZcLLy+qi0fHMqP0qcZlz/JbRM+qsYfGzCpJdsRRCJSTYS+pLeeU0LWXDhVJ7txAfbU18TyD4hRRKFOUEufOfo7v6XtsObQqXZ3aGW8mjuPWBiGNQFJ49LeKcwS5M9a78/o2beNag7Y7uw8JGKSq9QfvD9V7Tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dBDMlzPJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dBDMlzPJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 082B5C43390; Sun, 11 Feb 2024 08:30:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707640239; bh=P5YLYD6H2barwQbUJyuy1ic5ANsbxNgTsIlabr1argw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dBDMlzPJR/r2SJfn/2zj0UVSerbZCfru09XO12kY0UEpIywVi5IEFrqZFUtXLtLyj AqchY12D030mG4uQmMBKfnMEr7CAmkX7RyWhq+lyvX+C4BdEDKNOJX3nvlSDQndWcV hYBAgsBy4oMrTs91I6J5ehwJIsRoXsAmTWximuqA02VDFZqiaq21BOowvRLbPvVx2f jKKtpcuGgwjciZZ4V1oKDYO4Vk4oaGfSA3SDptgLzfvZ/2/3kprL3Ons46D7HfDIhL WzPvy3t6WPqeK245Da6ksmrc9wQd9ad7W+Nbi8WWnipBqO98QyptnNv4uXfWKdLu1B P1JK64R8YDupA== From: Jisheng Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: arm: sunxi: Add Sipeed Longan Module 3H and Longan Pi 3H Date: Sun, 11 Feb 2024 16:17:38 +0800 Message-ID: <20240211081739.395-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240211081739.395-1-jszhang@kernel.org> References: <20240211081739.395-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add name & compatible for the Sipeed Longan Module 3H and Longan PI 3H board. Signed-off-by: Jisheng Zhang Reviewed-by: Andre Przywara Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index a9d8e85565b8..a97d44ba10ac 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -835,6 +835,12 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 =20 + - description: Sipeed Longan Pi 3H board for the Sipeed Longan Modul= e 3H + items: + - const: sipeed,longan-pi-3h + - const: sipeed,longan-module-3h + - const: allwinner,sun50i-h618 + - description: SourceParts PopStick v1.1 items: - const: sourceparts,popstick-v1.1 --=20 2.43.0 From nobody Fri Dec 26 21:39:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5811A4CDEB; Sun, 11 Feb 2024 08:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707640242; cv=none; b=JyhsAERkUsTdMwDr1SqwafE/CuwQ8iTw50D3XaJGgOeHt9JhQZwOZKgORNb7z9lHlKgdrte5MZA2k6F4rKcRbJtv4WeCJocPweVnFnhWPgG/2Q/qdAzqvqGew9+Kt2FdDuMEiX8tfyTTozpGdyteXolreMMjGwZ40dLKTc7N8Vg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707640242; c=relaxed/simple; bh=hlTXI6UMycx+TmqfADYS2mcyoWnWOeTxWDUhNcbZ2Lc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NngDtV5WXF4Z8kRxX0i9VZe88cWhyk6q4NxZGEHouGTThAo7PTbyxTBHT2ebRy6aq0PKuRll4qAF2RtUN1LzJGswLFKj5dULpFgYQceR2YnMt9FuBnru8+0g3+6fZDtDIO7OQoLJaHXWmmXlmmkeW1bCp1BSSGB1PZM7DTZVsp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iy3X3sVN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iy3X3sVN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AED75C433C7; Sun, 11 Feb 2024 08:30:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707640241; bh=hlTXI6UMycx+TmqfADYS2mcyoWnWOeTxWDUhNcbZ2Lc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iy3X3sVNKk801bGIoz3l2BA6iHEWjb4xDKo26QHWe5a90yoV1XpdBGvOmyy9KaRse AKJJ7/Ruv0SaB9bxNAJcejGwJ5xvD8duOPopzP7ixW80lBMVIHmZW/HXQnsOmpw6PX OFWbRpMRvTjijmiJhZmvWoNj2CZOVrhFkueiJoHJam77m1PDMGSllT3CfZMK0yM/d6 TqiLeZfZxLyBvapyMr2nvYHKv0jBVWGkyq9Ab/F+E7oKjyPqYYZhwc4Bsal/JfSWLB fiCwe5oGV30oHFNjWVyzPhdY/N1R44AKQ1IUnHud3N4gsH0Jxgeks1zjZrFIdsBJEA SjL6VpWwqOUEQ== From: Jisheng Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] arm64: dts: allwinner: h616: Add Sipeed Longan SoM 3H and Pi 3H board support Date: Sun, 11 Feb 2024 16:17:39 +0800 Message-ID: <20240211081739.395-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240211081739.395-1-jszhang@kernel.org> References: <20240211081739.395-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Sipeed Longan SoM 3H is a system on module based on the Allwinner H618 SoC. The SoM features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 2/4 GiB LPDDR4 DRAM SoMs - AXP313a PMIC - eMMC The Sipeed Longan PI 3H is a development board based on the above SoM. The board features: - Longan SoM 3H - Raspberry-Pi-1 compatible GPIO header - 2 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - 1Gbps Ethernet port (via RTL8211 PHY) - HDMI port - WiFi/BT chip Add the devicetree file describing the currently supported features, namely PMIC, LEDs, UART, SD card, eMMC, USB and Ethernet. Signed-off-by: Jisheng Zhang Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h618-longan-module-3h.dtsi | 75 +++++++++ .../dts/allwinner/sun50i-h618-longanpi-3h.dts | 144 ++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module= -3h.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.d= ts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 91d505b385de..4b9173a16efe 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -42,5 +42,6 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-bigtreetech-cb1= -manta.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-bigtreetech-pi.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-transpeed-8k618-t.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dts= i b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi new file mode 100644 index 000000000000..8c1263a3939e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang + */ + +#include "sun50i-h616.dtsi" + +&mmc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + vmmc-supply =3D <®_dldo1>; + vqmmc-supply =3D <®_aldo1>; + bus-width =3D <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; + +&r_i2c { + status =3D "okay"; + + axp313: pmic@36 { + compatible =3D "x-powers,axp313a"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-3v3-io"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <990000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply =3D <®_dldo1>; + vcc-pf-supply =3D <®_dldo1>; + vcc-pg-supply =3D <®_aldo1>; + vcc-ph-supply =3D <®_dldo1>; + vcc-pi-supply =3D <®_dldo1>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts b/ar= ch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts new file mode 100644 index 000000000000..18b29c6b867f --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang + */ + +/dts-v1/; + +#include "sun50i-h618-longan-module-3h.dtsi" + +#include +#include +#include + +/ { + model =3D "Sipeed Longan Pi 3H"; + compatible =3D "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinn= er,sun50i-h618"; + + aliases { + ethernet0 =3D &emac0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + function-enumerator =3D <0>; + gpios =3D <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ + }; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + function-enumerator =3D <1>; + gpios =3D <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ + }; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <®_vcc5v>; + }; +}; + +&axp313 { + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; +}; + +&ehci1 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&ehci2 { + status =3D "okay"; +}; + +&ohci2 { + status =3D "okay"; +}; + +/* WiFi & BT combo module is connected to this Host */ +&ehci3 { + status =3D "okay"; +}; + +&ohci3 { + status =3D "okay"; +}; + +&emac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ext_rgmii_pins>; + phy-mode =3D "rgmii"; + phy-handle =3D <&ext_rgmii_phy>; + allwinner,rx-delay-ps =3D <3100>; + allwinner,tx-delay-ps =3D <700>; + phy-supply =3D <®_vcc3v3>; + status =3D "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + vmmc-supply =3D <®_vcc3v3>; + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb1_vbus-supply =3D <®_vcc5v>; + usb2_vbus-supply =3D <®_vcc5v>; + status =3D "okay"; +}; --=20 2.43.0