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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id z16-20020aa78890000000b006dff3ca9e26sm1635066pfe.102.2024.02.09.23.09.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:40 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Benson Leung , Guenter Roeck , linux-gpio@vger.kernel.org Subject: [PATCH 01/22] dt-bindings: gpio: Add binding for ChromeOS EC GPIO controller Date: Fri, 9 Feb 2024 23:09:12 -0800 Message-ID: <20240210070934.2549994-2-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ChromeOS embedded controller (EC) supports setting the state of GPIOs when the system is unlocked, and getting the state of GPIOs in all cases. The GPIOs are on the EC itself, so the EC acts similar to a GPIO expander. Add a binding to describe these GPIOs in DT so that other devices described in DT can read the GPIOs on the EC. Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Lee Jones Cc: Benson Leung Cc: Guenter Roeck Cc: Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- .../bindings/gpio/google,cros-ec-gpio.yaml | 49 +++++++++++++++++++ .../bindings/mfd/google,cros-ec.yaml | 3 ++ 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/google,cros-ec-g= pio.yaml diff --git a/Documentation/devicetree/bindings/gpio/google,cros-ec-gpio.yam= l b/Documentation/devicetree/bindings/gpio/google,cros-ec-gpio.yaml new file mode 100644 index 000000000000..a9f1d7784070 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/google,cros-ec-gpio.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/google,cros-ec-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIOs controlled by ChromeOS EC + +maintainers: + - Stephen Boyd + +description: + Google's ChromeOS EC has a gpio controller inside the Embedded Controller + (EC) and controlled via a host-command interface. The node for this + device should be under a cros-ec node like google,cros-ec-spi. + +properties: + compatible: + const: google,cros-ec-gpio + + '#gpio-cells': + const: 2 + + gpio-controller: true + +required: + - compatible + - '#gpio-cells' + - gpio-controller + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cros-ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts =3D <101 0>; + gpio { + compatible =3D "google,cros-ec-gpio"; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Do= cumentation/devicetree/bindings/mfd/google,cros-ec.yaml index e1ca4f297c6d..ded396b28fba 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -93,6 +93,9 @@ properties: '#size-cells': const: 0 =20 + gpio: + $ref: /schemas/gpio/google,cros-ec-gpio.yaml# + typec: $ref: /schemas/chrome/google,cros-ec-typec.yaml# =20 --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7E1200DC for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id r8-20020a17090ad40800b002967bc2c852sm2903295pju.43.2024.02.09.23.09.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:42 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Linus Walleij , Bartosz Golaszewski , Benson Leung , Guenter Roeck , linux-gpio@vger.kernel.org Subject: [PATCH 02/22] gpio: Add ChromeOS EC GPIO driver Date: Fri, 9 Feb 2024 23:09:13 -0800 Message-ID: <20240210070934.2549994-3-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ChromeOS embedded controller (EC) supports setting the state of GPIOs when the system is unlocked, and getting the state of GPIOs in all cases. The GPIOs are on the EC itself, so the EC acts similar to a GPIO expander. Add a driver to get and set the GPIOs on the EC through the host command interface. Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Benson Leung Cc: Guenter Roeck Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-cros-ec.c | 218 ++++++++++++++++++++++++++++++++++++ 3 files changed, 229 insertions(+) create mode 100644 drivers/gpio/gpio-cros-ec.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b3a133ed31ee..62b0ae25a727 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1220,6 +1220,16 @@ config GPIO_BD9571MWV This driver can also be built as a module. If so, the module will be called gpio-bd9571mwv. =20 +config GPIO_CROS_EC + tristate "ChromeOS EC GPIO support" + depends on CROS_EC + help + GPIO driver for exposing GPIOs on the ChromeOS Embedded + Controller. + + This driver can also be built as a module. If so, the module + will be called gpio-cros-ec. + config GPIO_CRYSTAL_COVE tristate "GPIO support for Crystal Cove PMIC" depends on (X86 || COMPILE_TEST) && INTEL_SOC_PMIC diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index eb73b5d633eb..2e66410c1da6 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_GPIO_BT8XX) +=3D gpio-bt8xx.o obj-$(CONFIG_GPIO_CADENCE) +=3D gpio-cadence.o obj-$(CONFIG_GPIO_CLPS711X) +=3D gpio-clps711x.o obj-$(CONFIG_GPIO_SNPS_CREG) +=3D gpio-creg-snps.o +obj-$(CONFIG_GPIO_CROS_EC) +=3D gpio-cros-ec.o obj-$(CONFIG_GPIO_CRYSTAL_COVE) +=3D gpio-crystalcove.o obj-$(CONFIG_GPIO_CS5535) +=3D gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) +=3D gpio-da9052.o diff --git a/drivers/gpio/gpio-cros-ec.c b/drivers/gpio/gpio-cros-ec.c new file mode 100644 index 000000000000..0d35558304bf --- /dev/null +++ b/drivers/gpio/gpio-cros-ec.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2024 Google LLC + * + * This driver provides the ability to control GPIOs on the Chrome OS EC. + * There isn't any direction control, and setting values on GPIOs is only + * possible when the system is unlocked. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Setting gpios is only supported when the system is unlocked */ +static void cros_ec_gpio_set(struct gpio_chip *gc, unsigned int gpio, int = val) +{ + const char *name =3D gc->names[gpio]; + struct cros_ec_device *cros_ec =3D gpiochip_get_data(gc); + struct ec_params_gpio_set params =3D { + .val =3D val, + }; + int ret; + ssize_t copied; + + copied =3D strscpy(params.name, name, sizeof(params.name)); + if (copied < 0) + return; + + ret =3D cros_ec_cmd(cros_ec, 0, EC_CMD_GPIO_SET, ¶ms, + sizeof(params), NULL, 0); + if (ret < 0) + dev_err(gc->parent, "error setting gpio%d (%s) on EC: %d\n", gpio, name,= ret); +} + +static int cros_ec_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + const char *name =3D gc->names[gpio]; + struct cros_ec_device *cros_ec =3D gpiochip_get_data(gc); + struct ec_params_gpio_get params; + struct ec_response_gpio_get response; + int ret; + ssize_t copied; + + copied =3D strscpy(params.name, name, sizeof(params.name)); + if (copied < 0) + return -EINVAL; + + ret =3D cros_ec_cmd(cros_ec, 0, EC_CMD_GPIO_GET, ¶ms, + sizeof(params), &response, sizeof(response)); + if (ret < 0) { + dev_err(gc->parent, "error getting gpio%d (%s) on EC: %d\n", gpio, name,= ret); + return ret; + } + + return response.val; +} + +#define CROS_EC_GPIO_INPUT BIT(8) +#define CROS_EC_GPIO_OUTPUT BIT(9) + +static int cros_ec_gpio_get_direction(struct gpio_chip *gc, unsigned int g= pio) +{ + const char *name =3D gc->names[gpio]; + struct cros_ec_device *cros_ec =3D gpiochip_get_data(gc); + struct ec_params_gpio_get_v1 params =3D { + .subcmd =3D EC_GPIO_GET_INFO, + .get_info.index =3D gpio, + }; + struct ec_response_gpio_get_v1 response; + int ret; + + ret =3D cros_ec_cmd(cros_ec, 1, EC_CMD_GPIO_GET, ¶ms, + sizeof(params), &response, sizeof(response)); + if (ret < 0) { + dev_err(gc->parent, "error getting direction of gpio%d (%s) on EC: %d\n"= , gpio, name, ret); + return ret; + } + + if (response.get_info.flags & CROS_EC_GPIO_INPUT) + return GPIO_LINE_DIRECTION_IN; + + if (response.get_info.flags & CROS_EC_GPIO_OUTPUT) + return GPIO_LINE_DIRECTION_OUT; + + return -EINVAL; +} + +static int cros_ec_gpio_request(struct gpio_chip *chip, unsigned gpio_pin) +{ + if (gpio_pin < chip->ngpio) + return 0; + + return -EINVAL; +} + +/* Query EC for all gpio line names */ +static int cros_ec_gpio_init_names(struct cros_ec_device *cros_ec, struct = gpio_chip *gc) +{ + struct ec_params_gpio_get_v1 params =3D { + .subcmd =3D EC_GPIO_GET_INFO, + }; + struct ec_response_gpio_get_v1 response; + int ret, i; + /* EC may not NUL terminate */ + size_t name_len =3D sizeof(response.get_info.name) + 1; + ssize_t copied; + const char **names; + char *str; + + names =3D devm_kcalloc(gc->parent, gc->ngpio, sizeof(*names), GFP_KERNEL); + if (!names) + return -ENOMEM; + gc->names =3D names; + + str =3D devm_kcalloc(gc->parent, gc->ngpio, name_len, GFP_KERNEL); + if (!str) + return -ENOMEM; + + /* Get gpio line names one at a time */ + for (i =3D 0; i < gc->ngpio; i++) { + params.get_info.index =3D i; + ret =3D cros_ec_cmd(cros_ec, 1, EC_CMD_GPIO_GET, ¶ms, + sizeof(params), &response, sizeof(response)); + if (ret < 0) { + dev_err_probe(gc->parent, ret, "error getting gpio%d info\n", i); + return ret; + } + + names[i] =3D str; + copied =3D strscpy(str, response.get_info.name, name_len); + if (copied < 0) + return copied; + + str +=3D copied + 1; + } + + return 0; +} + +/* Query EC for number of gpios */ +static int cros_ec_gpio_ngpios(struct cros_ec_device *cros_ec) +{ + struct ec_params_gpio_get_v1 params =3D { + .subcmd =3D EC_GPIO_GET_COUNT, + }; + struct ec_response_gpio_get_v1 response; + int ret; + + ret =3D cros_ec_cmd(cros_ec, 1, EC_CMD_GPIO_GET, ¶ms, + sizeof(params), &response, sizeof(response)); + if (ret < 0) + return ret; + + return response.get_count.val; +} + +static int cros_ec_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cros_ec_device *cros_ec =3D dev_get_drvdata(dev->parent); + struct gpio_chip *gc; + int ngpios; + int ret; + + ngpios =3D cros_ec_gpio_ngpios(cros_ec); + if (ngpios < 0) { + dev_err_probe(dev, ngpios, "error getting gpio count\n"); + return ngpios; + } + + gc =3D devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); + if (!gc) + return -ENOMEM; + + gc->ngpio =3D ngpios; + gc->parent =3D dev; + ret =3D cros_ec_gpio_init_names(cros_ec, gc); + if (ret) + return ret; + + gc->can_sleep =3D true; + gc->label =3D dev_name(dev); + gc->base =3D -1; + gc->set =3D cros_ec_gpio_set; + gc->get =3D cros_ec_gpio_get; + gc->get_direction =3D cros_ec_gpio_get_direction; + gc->request =3D cros_ec_gpio_request; + + return devm_gpiochip_add_data(&pdev->dev, gc, cros_ec); +} + +#ifdef CONFIG_OF +static const struct of_device_id cros_ec_gpio_of_match[] =3D { + { .compatible =3D "google,cros-ec-gpio" }, + {} +}; +MODULE_DEVICE_TABLE(of, cros_ec_gpio_of_match); +#endif + +static struct platform_driver cros_ec_gpio_driver =3D { + .probe =3D cros_ec_gpio_probe, + .driver =3D { + .name =3D "cros-ec-gpio", + .of_match_table =3D of_match_ptr(cros_ec_gpio_of_match), + }, +}; +module_platform_driver(cros_ec_gpio_driver); + +MODULE_DESCRIPTION("ChromeOS EC GPIO Driver"); +MODULE_LICENSE("GPL"); --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65415360BC for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id d4-20020a170903230400b001d90a67e10bsm2489560plh.109.2024.02.09.23.09.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:44 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Kaehlcke , linux-usb@vger.kernel.org, maciek swiech Subject: [PATCH 03/22] dt-bindings: usb: Add downstream facing ports to realtek binding Date: Fri, 9 Feb 2024 23:09:14 -0800 Message-ID: <20240210070934.2549994-4-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a graph with 4 output endpoints to this hub binding to support the scenario where a downstream facing port is connected to a device that isn't a connector or a USB device with a VID:PID. This will be used to connect downstream facing ports to USB type-c switches so the USB superspeed and high speed lanes can be put onto USB connectors. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Matthias Kaehlcke Cc: Cc: Cc: Pin-yen Lin Cc: maciek swiech Signed-off-by: Stephen Boyd --- .../bindings/usb/realtek,rts5411.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml b/D= ocumentation/devicetree/bindings/usb/realtek,rts5411.yaml index f0784d2e86da..5480a31698be 100644 --- a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml +++ b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml @@ -21,6 +21,12 @@ properties: =20 reg: true =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + vdd-supply: description: phandle to the regulator that provides power to the hub. @@ -30,6 +36,36 @@ properties: description: phandle to the peer hub on the controller. =20 + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + 1st downstream facing USB port + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + 2nd downstream facing USB port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: + 3rd downstream facing USB port + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: + 4th downstream facing USB port + +patternProperties: + "^.*@[1-4]$": + description: The hard wired USB devices + type: object + $ref: /schemas/usb/usb-device.yaml + required: - peer-hub - compatible @@ -50,6 +86,11 @@ examples: reg =3D <1>; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id s7-20020a170903320700b001d9b749d281sm2493240plh.53.2024.02.09.23.09.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:45 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Greg Kroah-Hartman , Matthias Kaehlcke , linux-usb@vger.kernel.org, maciek swiech Subject: [PATCH 04/22] usb: core: Set connect_type of ports based on DT node Date: Fri, 9 Feb 2024 23:09:15 -0800 Message-ID: <20240210070934.2549994-5-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When a USB hub is described in DT, such as any device that matches the onboard-hub driver, the connect_type is set to "unknown" or USB_PORT_CONNECT_TYPE_UNKNOWN. This makes any device plugged into that USB port report their 'removable' device attribute as "unknown". Improve the connect_type attribute for ports, and in turn the removable attribute for USB devices, by looking for child devices with a reg property or an OF graph when the device is described in DT. If the graph exists, endpoints that are connected to a remote node must be something like a usb-{a,b,c}-connector compatible node, or an intermediate node like a redriver, and not a hardwired USB device on the board. Set the connect_type to USB_PORT_CONNECT_TYPE_HOT_PLUG in this case because the device is going to be plugged in. Set the connect_type to USB_PORT_CONNECT_TYPE_HARD_WIRED if there's a child node for the port like 'device@2' for port2. Set the connect_type to USB_PORT_NOT_USED if there isn't an endpoint or child node corresponding to the port number. To make sure things don't change, only set the port to not used if there are child nodes. This way an onboard hub connect_type doesn't change until ports are added or child nodes are added to describe hardwired devices. It's assumed that all ports or no ports will be described for a device. Cc: Greg Kroah-Hartman Cc: Matthias Kaehlcke Cc: Cc: Cc: Pin-yen Lin Cc: maciek swiech Signed-off-by: Stephen Boyd --- drivers/usb/core/port.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/usb/core/port.c b/drivers/usb/core/port.c index c628c1abc907..622b8ada157c 100644 --- a/drivers/usb/core/port.c +++ b/drivers/usb/core/port.c @@ -9,6 +9,8 @@ =20 #include #include +#include +#include #include #include =20 @@ -696,7 +698,10 @@ int usb_hub_create_port_device(struct usb_hub *hub, in= t port1) { struct usb_port *port_dev; struct usb_device *hdev =3D hub->hdev; + struct device_node *np, *child, *ep, *remote_np, *port_np; int retval; + enum usb_port_connect_type connect_type =3D USB_PORT_CONNECT_TYPE_UNKNOWN; + u32 reg; =20 port_dev =3D kzalloc(sizeof(*port_dev), GFP_KERNEL); if (!port_dev) @@ -708,6 +713,38 @@ int usb_hub_create_port_device(struct usb_hub *hub, in= t port1) return -ENOMEM; } =20 + np =3D hdev->dev.of_node; + /* Only set connect_type if binding has ports/hardwired devices. */ + if (of_get_child_count(np)) + connect_type =3D USB_PORT_NOT_USED; + + /* Hotplug ports are connected and available in the OF graph. */ + if (of_graph_is_present(np)) { + port_np =3D of_graph_get_port_by_id(np, port1); + if (port_np) { + ep =3D of_graph_get_endpoint_by_regs(np, port1, -1); + if (ep) { + remote_np =3D of_graph_get_remote_port_parent(ep); + of_node_put(ep); + if (of_device_is_available(remote_np)) + connect_type =3D USB_PORT_CONNECT_TYPE_HOT_PLUG; + of_node_put(remote_np); + } + } + of_node_put(port_np); + } + + /* + * Hard-wired ports are child nodes with a reg property corresponding + * to the port number. + */ + for_each_available_child_of_node(np, child) { + if (!of_property_read_u32(child, "reg", ®) && reg =3D=3D port1) + connect_type =3D USB_PORT_CONNECT_TYPE_HARD_WIRED; + } + + port_dev->connect_type =3D connect_type; + hub->ports[port1 - 1] =3D port_dev; port_dev->portnum =3D port1; set_bit(port1, hub->power_bits); --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-oi1-f171.google.com (mail-oi1-f171.google.com [209.85.167.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C107376ED for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id y2-20020aa78542000000b006e096ff7c91sm1645603pfn.100.2024.02.09.23.09.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:47 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: [PATCH 05/22] drm/atomic-helper: Introduce lane remapping support to bridges Date: Fri, 9 Feb 2024 23:09:16 -0800 Message-ID: <20240210070934.2549994-6-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to the DRM atomic logic to support lane remapping between bridges, encoders and connectors. Typically lane mapping is handled statically in firmware, e.g. on DT we use the data-lanes property to assign lanes when connecting display bridges. Lane assignment is dynamic with USB-C DisplayPort altmodes, e.g. pin conf D assigns 2 lanes of DP to pins on the USB-C connector while pin conf C assigns 4 lanes of DP to pins on the USB-C connector. The lane assignment can't be set statically because the DP altmode repurposes USB-C pins for the DP lanes while also limiting the number of DP lanes or their pin assignment at runtime. Bridge drivers should point their 'struct drm_bus_cfg::lanes' pointer to an allocated array of 'struct drm_lane_cfg' structures and indicate the size of this allocated array with 'struct drm_bus_cfg::num_lanes' in their atomic_check() callback. The previous bridge in the bridge chain can look at this information by calling drm_bridge_next_bridge_lane_cfg() in their atomic_check() callback to figure out what lanes need to be logically assigned to the physical output lanes to satisfy the next bridge's lane assignment. Cc: Andrzej Hajda Cc: Neil Armstrong Cc: Robert Foss Cc: Laurent Pinchart Cc: Jonas Karlman Cc: Jernej Skrabec Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/gpu/drm/drm_atomic_state_helper.c | 2 ++ drivers/gpu/drm/drm_bridge.c | 34 +++++++++++++++++++++++ include/drm/drm_atomic.h | 31 +++++++++++++++++++++ include/drm/drm_bridge.h | 4 +++ 4 files changed, 71 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/dr= m_atomic_state_helper.c index 784e63d70a42..2e989fbeb503 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -764,6 +764,8 @@ EXPORT_SYMBOL(drm_atomic_helper_bridge_duplicate_state); void drm_atomic_helper_bridge_destroy_state(struct drm_bridge *bridge, struct drm_bridge_state *state) { + kfree(state->input_bus_cfg.lanes); + kfree(state->output_bus_cfg.lanes); kfree(state); } EXPORT_SYMBOL(drm_atomic_helper_bridge_destroy_state); diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 30d66bee0ec6..3fce0d8d7dcb 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -843,6 +843,40 @@ void drm_atomic_bridge_chain_enable(struct drm_bridge = *bridge, } EXPORT_SYMBOL(drm_atomic_bridge_chain_enable); =20 +/** + * drm_bridge_next_bridge_lane_cfg - get the lane configuration of the nex= t bridge + * @bridge: bridge control structure + * @state: new atomic state + * @num_lanes: will contain the size of the returned array + * + * This function is typically called from &drm_bridge_funcs.atomic_check(). + * The @bridge driver calls this function to determine what the next bridg= e in + * the bridge chain requires for the physical to logical lane assignments. + * + * Return: Lane configuration array of size @num_lanes for the next bridge + * after @bridge in the bridge chain, or NULL if the lane configuration is + * unchanged from the default. + */ +const struct drm_lane_cfg * +drm_bridge_next_bridge_lane_cfg(struct drm_bridge *bridge, + struct drm_atomic_state *state, + u8 *num_lanes) +{ + const struct drm_bridge_state *next_bridge_state; + struct drm_bridge *next_bridge =3D drm_bridge_get_next_bridge(bridge); + + next_bridge_state =3D drm_atomic_get_new_bridge_state(state, next_bridge); + if (!next_bridge_state) { + *num_lanes =3D 0; + return NULL; + } + + *num_lanes =3D next_bridge_state->input_bus_cfg.num_lanes; + + return next_bridge_state->input_bus_cfg.lanes; +} +EXPORT_SYMBOL(drm_bridge_next_bridge_lane_cfg); + static int drm_atomic_bridge_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index cf8e1220a4ac..b206ae2654d8 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -1074,6 +1074,27 @@ drm_atomic_crtc_effectively_active(const struct drm_= crtc_state *state) return state->active || state->self_refresh_active; } =20 +/** + * struct drm_lane_cfg - lane configuration + * + * This structure stores the lange configuration of a physical bus between + * two components in an output pipeline, usually between two bridges, an + * encoder and a bridge, or a bridge and a connector. + * + * The lane configuration is stored in &drm_bus_cfg. + */ +struct drm_lane_cfg { + /** + * @logical: Logical lane number + */ + u8 logical; + + /** + * @inverted: True if lane polarity is inverted, false otherwise + */ + bool inverted; +}; + /** * struct drm_bus_cfg - bus configuration * @@ -1104,6 +1125,16 @@ struct drm_bus_cfg { * @flags: DRM_BUS_* flags used on this bus */ u32 flags; + + /** + * @lanes: Lane mapping for this bus + */ + struct drm_lane_cfg *lanes; + + /** + * @num_lanes: Number of lanes in @lanes + */ + u8 num_lanes; }; =20 /** diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h index cfb7dcdb66c4..5f64f6e822e1 100644 --- a/include/drm/drm_bridge.h +++ b/include/drm/drm_bridge.h @@ -884,6 +884,10 @@ drm_atomic_helper_bridge_propagate_bus_fmt(struct drm_= bridge *bridge, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts); +const struct drm_lane_cfg * +drm_bridge_next_bridge_lane_cfg(struct drm_bridge *bridge, + struct drm_atomic_state *state, + u8 *num_lanes); =20 enum drm_connector_status drm_bridge_detect(struct drm_bridge *bridge); int drm_bridge_get_modes(struct drm_bridge *bridge, --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A84DA383AF for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id se14-20020a17090b518e00b00296d3598f9asm2910769pjb.35.2024.02.09.23.09.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:49 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: [PATCH 06/22] drm/bridge: Verify lane assignment is going to work during atomic_check Date: Fri, 9 Feb 2024 23:09:17 -0800 Message-ID: <20240210070934.2549994-7-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Verify during drm_atomic_bridge_check() that the lane assignment set in a bridge's atomic_check() callback is going to be satisfied by the previous bridge. If the next bridge is requiring something besides the default 1:1 lane assignment on its input then there must be an output lane assignment on the previous bridge's output. Otherwise the next bridge won't get the lanes assigned that it needs. Cc: Andrzej Hajda Cc: Neil Armstrong Cc: Robert Foss Cc: Laurent Pinchart Cc: Jonas Karlman Cc: Jernej Skrabec Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/gpu/drm/drm_bridge.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 3fce0d8d7dcb..5097e7c65ddf 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -881,6 +881,10 @@ static int drm_atomic_bridge_check(struct drm_bridge *= bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + u8 num_input_lanes, num_output_lanes =3D 0; + const struct drm_lane_cfg *input_lanes; + int i; + if (bridge->funcs->atomic_check) { struct drm_bridge_state *bridge_state; int ret; @@ -894,12 +898,24 @@ static int drm_atomic_bridge_check(struct drm_bridge = *bridge, crtc_state, conn_state); if (ret) return ret; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id y30-20020a63b51e000000b005dc5289c4edsm2717207pge.64.2024.02.09.23.09.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:51 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Vinod Koul , "Rafael J. Wysocki" , Mika Westerberg , Alexandre Belloni , Ivan Orlov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-usb@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH 07/22] device property: Add remote endpoint to devcon matcher Date: Fri, 9 Feb 2024 23:09:18 -0800 Message-ID: <20240210070934.2549994-8-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When a single DT node has a graph connected to more than one usb-c-connector node we can't differentiate which typec switch registered for the device is associated with the USB connector because the devcon matcher code assumes a 1:1 relationship between remote node and typec switch. Furthermore, we don't have a #typec-switch-cells property so there can only be one node per typec switch. Support multiple USB typec switches exposed by one node by passing the remote endpoint node in addition to the remote node to the devcon matcher function (devcon_match_fn_t). With this change, typec switch drivers can register switches with the device node pointer for a graph endpoint so that they can support more than one typec switch if necessary. Either way, a DT property like 'mode-switch' is always in the graph's parent node and not in the endpoint node. Cc: Andy Shevchenko Cc: Daniel Scally Cc: Heikki Krogerus Cc: Sakari Ailus Cc: Greg Kroah-Hartman Cc: Vinod Koul Cc: "Rafael J. Wysocki" Cc: Mika Westerberg Cc: Alexandre Belloni Cc: Ivan Orlov Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/base/property.c | 7 +++++-- drivers/usb/roles/class.c | 4 ++-- drivers/usb/typec/mux.c | 8 ++++++++ drivers/usb/typec/retimer.c | 7 ++++++- include/linux/property.h | 5 +++-- 5 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/base/property.c b/drivers/base/property.c index 8c40abed7852..cae81ed4e298 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -1289,6 +1289,7 @@ static unsigned int fwnode_graph_devcon_matches(const= struct fwnode_handle *fwno { struct fwnode_handle *node; struct fwnode_handle *ep; + struct fwnode_handle *remote_ep; unsigned int count =3D 0; void *ret; =20 @@ -1304,7 +1305,9 @@ static unsigned int fwnode_graph_devcon_matches(const= struct fwnode_handle *fwno continue; } =20 - ret =3D match(node, con_id, data); + remote_ep =3D fwnode_graph_get_remote_endpoint(ep); + ret =3D match(node, remote_ep, con_id, data); + fwnode_handle_put(remote_ep); fwnode_handle_put(node); if (ret) { if (matches) @@ -1334,7 +1337,7 @@ static unsigned int fwnode_devcon_matches(const struc= t fwnode_handle *fwnode, if (IS_ERR(node)) break; =20 - ret =3D match(node, NULL, data); + ret =3D match(node, NULL, NULL, data); fwnode_handle_put(node); if (ret) { if (matches) diff --git a/drivers/usb/roles/class.c b/drivers/usb/roles/class.c index ae41578bd014..9a0ef5fa0a19 100644 --- a/drivers/usb/roles/class.c +++ b/drivers/usb/roles/class.c @@ -89,8 +89,8 @@ enum usb_role usb_role_switch_get_role(struct usb_role_sw= itch *sw) } EXPORT_SYMBOL_GPL(usb_role_switch_get_role); =20 -static void *usb_role_switch_match(const struct fwnode_handle *fwnode, con= st char *id, - void *data) +static void *usb_role_switch_match(const struct fwnode_handle *fwnode, con= st struct fwnode_handle *endpoint, + const char *id, void *data) { struct device *dev; =20 diff --git a/drivers/usb/typec/mux.c b/drivers/usb/typec/mux.c index 80dd91938d96..3eabd0d62f47 100644 --- a/drivers/usb/typec/mux.c +++ b/drivers/usb/typec/mux.c @@ -33,6 +33,7 @@ static int switch_fwnode_match(struct device *dev, const = void *fwnode) } =20 static void *typec_switch_match(const struct fwnode_handle *fwnode, + const struct fwnode_handle *endpoint, const char *id, void *data) { struct device *dev; @@ -55,6 +56,9 @@ static void *typec_switch_match(const struct fwnode_handl= e *fwnode, */ dev =3D class_find_device(&typec_mux_class, NULL, fwnode, switch_fwnode_match); + if (!dev) + dev =3D class_find_device(&typec_mux_class, NULL, endpoint, + switch_fwnode_match); =20 return dev ? to_typec_switch_dev(dev) : ERR_PTR(-EPROBE_DEFER); } @@ -263,6 +267,7 @@ static int mux_fwnode_match(struct device *dev, const v= oid *fwnode) } =20 static void *typec_mux_match(const struct fwnode_handle *fwnode, + const struct fwnode_handle *endpoint, const char *id, void *data) { struct device *dev; @@ -280,6 +285,9 @@ static void *typec_mux_match(const struct fwnode_handle= *fwnode, =20 dev =3D class_find_device(&typec_mux_class, NULL, fwnode, mux_fwnode_match); + if (!dev) + dev =3D class_find_device(&typec_mux_class, NULL, endpoint, + mux_fwnode_match); =20 return dev ? to_typec_mux_dev(dev) : ERR_PTR(-EPROBE_DEFER); } diff --git a/drivers/usb/typec/retimer.c b/drivers/usb/typec/retimer.c index 4a7d1b5c4d86..eb74abee6619 100644 --- a/drivers/usb/typec/retimer.c +++ b/drivers/usb/typec/retimer.c @@ -22,7 +22,9 @@ static int retimer_fwnode_match(struct device *dev, const= void *fwnode) return is_typec_retimer(dev) && device_match_fwnode(dev, fwnode); } =20 -static void *typec_retimer_match(const struct fwnode_handle *fwnode, const= char *id, void *data) +static void *typec_retimer_match(const struct fwnode_handle *fwnode, + const struct fwnode_handle *endpoint, + const char *id, void *data) { struct device *dev; =20 @@ -31,6 +33,9 @@ static void *typec_retimer_match(const struct fwnode_hand= le *fwnode, const char =20 dev =3D class_find_device(&retimer_class, NULL, fwnode, retimer_fwnode_match); + if (!dev) + dev =3D class_find_device(&retimer_class, NULL, endpoint, + retimer_fwnode_match); =20 return dev ? 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id bj13-20020a17090b088d00b0029552a03219sm2883297pjb.29.2024.02.09.23.09.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:53 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: Prashant Malani , linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Chen-Yu Tsai , AngeloGioacchino Del Regno , Heikki Krogerus Subject: [PATCH 08/22] platform/chrome: cros_ec_typec: Purge blocking switch devlinks Date: Fri, 9 Feb 2024 23:09:19 -0800 Message-ID: <20240210070934.2549994-9-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Prashant Malani When using OF graph, the fw_devlink code will create links between the individual port driver (cros-ec-typec here) and the parent device for a Type-C switch (like mode-switch). Since the mode-switch will in turn have the usb-c-connector (i.e the child of the port driver) as a supplier, fw_devlink will not be able to resolve the cyclic dependency correctly. As a result, the mode-switch driver probe() never runs, so mode-switches are never registered. Because of that, the port driver probe constantly fails with -EPROBE_DEFER, because the Type-C connector class requires all switch devices to be registered prior to port registration. To break this deadlock and allow the mode-switch registration to occur, purge all the usb-c-connector nodes' absent suppliers. This eliminates the connector as a supplier for a switch and allows it to be probed. Signed-off-by: Prashant Malani Signed-off-by: Pin-yen Lin Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Acked-by: Heikki Krogerus Link: https://lore.kernel.org/r/20230331091145.737305-3-treapking@chromium.= org Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_ec_typec.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index 2b2f14a1b711..cc5269a4b2f1 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -325,6 +325,16 @@ static int cros_typec_init_ports(struct cros_typec_dat= a *typec) return -EINVAL; } =20 + /* + * OF graph may have set up some device links with switches, + * since connectors have their own compatible. Purge these + * to avoid a deadlock in switch probe (the switch mistakenly + * assumes the connector is a supplier). + */ + if (dev_of_node(dev)) + device_for_each_child_node(dev, fwnode) + fw_devlink_purge_absent_suppliers(fwnode); + /* DT uses "reg" to specify port number. */ port_prop =3D dev->of_node ? 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id ip3-20020a17090b314300b00296fd5e0de1sm2828227pjb.34.2024.02.09.23.09.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:54 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 09/22] platform/chrome: cros_typec_switch: Use read_poll_timeout helper Date: Fri, 9 Feb 2024 23:09:20 -0800 Message-ID: <20240210070934.2549994-10-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's possible for this polling loop to get scheduled away for a long time right after checking the status on the EC. If that happens, we will never try to check the status at least one more time before giving up and saying that it timed out. Let's use the read_poll_timeout() macro to construct the loop with a proper timeout mechanism and the ability to check that the condition is true once more when the timeout hits. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index 07a19386dc4e..a23fe80d9d4b 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -8,7 +8,7 @@ =20 #include #include -#include +#include #include #include #include @@ -108,7 +108,6 @@ static bool cros_typec_check_event(struct cros_typec_sw= itch_data *sdata, int por static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, = int port_num, int index, unsigned long mode, struct typec_altmode *alt) { - unsigned long end; u32 event_mask; u8 mux_state; int ret; @@ -134,18 +133,14 @@ static int cros_typec_configure_mux(struct cros_typec= _switch_data *sdata, int po return ret; =20 /* Check for the mux set done event. */ - end =3D jiffies + msecs_to_jiffies(1000); - do { - if (cros_typec_check_event(sdata, port_num, event_mask)) - return 0; + if (read_poll_timeout(cros_typec_check_event, ret, ret =3D=3D 0, 1000, + 1000 * 1000UL, false, sdata, port_num, event_mask)) { + dev_err(sdata->dev, "Timed out waiting for mux set done on index: %d, st= ate: %d\n", + index, mux_state); + return -ETIMEDOUT; + } =20 - usleep_range(500, 1000); - } while (time_before(jiffies, end)); - - dev_err(sdata->dev, "Timed out waiting for mux set done on index: %d, sta= te: %d\n", - index, mux_state); - - return -ETIMEDOUT; + return 0; } =20 static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A95939FD6 for ; Sat, 10 Feb 2024 07:09:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id ko13-20020a17090307cd00b001d88d791eccsm2507677plb.160.2024.02.09.23.09.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:56 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 10/22] platform/chrome: cros_typec_switch: Move port creation code to sub-function Date: Fri, 9 Feb 2024 23:09:21 -0800 Message-ID: <20240210070934.2549994-11-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This driver will soon support devicetree firmwares. Extract the struct cros_typec_port creation part of cros_typec_register_switches() into a sub-function so that we can extend it for DT, where a graph is used instead of child nodes. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 113 +++++++++++--------- 1 file changed, 62 insertions(+), 51 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index a23fe80d9d4b..1a718b661203 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -201,13 +201,69 @@ static int cros_typec_register_retimer(struct cros_ty= pec_port *port, struct fwno return PTR_ERR_OR_ZERO(port->retimer); } =20 -static int cros_typec_register_switches(struct cros_typec_switch_data *sda= ta) +static int cros_typec_register_port(struct cros_typec_switch_data *sdata, + struct fwnode_handle *fwnode) { struct cros_typec_port *port; struct device *dev =3D sdata->dev; - struct fwnode_handle *fwnode; struct acpi_device *adev; unsigned long long index; + int ret; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + adev =3D to_acpi_device_node(fwnode); + if (adev) { + ret =3D acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); + if (ACPI_FAILURE(ret)) { + dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); + return -ENODATA; + } + } + + if (!adev) { + dev_err(fwnode->dev, "Couldn't get ACPI handle\n"); + return -ENODEV; + } + + if (index >=3D EC_USB_PD_MAX_PORTS) { + dev_err(fwnode->dev, "Invalid port index number: %llu\n", index); + return -EINVAL; + } + port->sdata =3D sdata; + port->port_num =3D index; + sdata->ports[index] =3D port; + + if (fwnode_property_present(fwnode, "retimer-switch")) { + ret =3D cros_typec_register_retimer(port, fwnode); + if (ret) { + dev_err(dev, "Retimer switch register failed\n"); + return ret; + } + + dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + } + + if (!fwnode_property_present(fwnode, "mode-switch")) + return 0; + + ret =3D cros_typec_register_mode_switch(port, fwnode); + if (ret) { + dev_err(dev, "Mode switch register failed\n"); + return ret; + } + + dev_dbg(dev, "Mode switch registered for index %llu\n", index); + + return ret; +} + +static int cros_typec_register_switches(struct cros_typec_switch_data *sda= ta) +{ + struct device *dev =3D sdata->dev; + struct fwnode_handle *fwnode; int nports, ret; =20 nports =3D device_get_child_node_count(dev); @@ -217,60 +273,15 @@ static int cros_typec_register_switches(struct cros_t= ypec_switch_data *sdata) } =20 device_for_each_child_node(dev, fwnode) { - port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); - if (!port) { - ret =3D -ENOMEM; - goto err_switch; - } - - adev =3D to_acpi_device_node(fwnode); - if (!adev) { - dev_err(fwnode->dev, "Couldn't get ACPI device handle\n"); - ret =3D -ENODEV; - goto err_switch; - } - - ret =3D acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); - if (ACPI_FAILURE(ret)) { - dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); - ret =3D -ENODATA; - goto err_switch; - } - - if (index >=3D EC_USB_PD_MAX_PORTS) { - dev_err(fwnode->dev, "Invalid port index number: %llu\n", index); - ret =3D -EINVAL; - goto err_switch; - } - port->sdata =3D sdata; - port->port_num =3D index; - sdata->ports[index] =3D port; - - if (fwnode_property_present(fwnode, "retimer-switch")) { - ret =3D cros_typec_register_retimer(port, fwnode); - if (ret) { - dev_err(dev, "Retimer switch register failed\n"); - goto err_switch; - } - - dev_dbg(dev, "Retimer switch registered for index %llu\n", index); - } - - if (!fwnode_property_present(fwnode, "mode-switch")) - continue; - - ret =3D cros_typec_register_mode_switch(port, fwnode); + ret =3D cros_typec_register_port(sdata, fwnode); if (ret) { - dev_err(dev, "Mode switch register failed\n"); - goto err_switch; + fwnode_handle_put(fwnode); + goto err; } - - dev_dbg(dev, "Mode switch registered for index %llu\n", index); } =20 return 0; -err_switch: - fwnode_handle_put(fwnode); +err: cros_typec_unregister_switches(sdata); return ret; } --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A81439FFB for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id h9-20020a170902f2c900b001d921bcc621sm2478144plc.243.2024.02.09.23.09.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:57 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 11/22] platform/chrome: cros_typec_switch: Use fwnode instead of ACPI APIs Date: Fri, 9 Feb 2024 23:09:22 -0800 Message-ID: <20240210070934.2549994-12-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use fwnode APIs instead of ACPI ones because this driver will soon support devicetree firmwares. Using fwnode APIs makes it easier to support either ACPI or DT. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 24 +++++++++++---------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index 1a718b661203..373e0e86ebfc 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -207,29 +207,31 @@ static int cros_typec_register_port(struct cros_typec= _switch_data *sdata, struct cros_typec_port *port; struct device *dev =3D sdata->dev; struct acpi_device *adev; - unsigned long long index; + u32 index; int ret; + const char *prop_name; =20 port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; =20 adev =3D to_acpi_device_node(fwnode); - if (adev) { - ret =3D acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); - if (ACPI_FAILURE(ret)) { - dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); - return -ENODATA; - } - } + if (adev) + prop_name =3D "_ADR"; =20 if (!adev) { dev_err(fwnode->dev, "Couldn't get ACPI handle\n"); return -ENODEV; } =20 + ret =3D fwnode_property_read_u32(fwnode, prop_name, &index); + if (ret) { + dev_err(fwnode->dev, "%s property wasn't found\n", prop_name); + return ret; + } + if (index >=3D EC_USB_PD_MAX_PORTS) { - dev_err(fwnode->dev, "Invalid port index number: %llu\n", index); + dev_err(fwnode->dev, "Invalid port index number: %u\n", index); return -EINVAL; } port->sdata =3D sdata; @@ -243,7 +245,7 @@ static int cros_typec_register_port(struct cros_typec_s= witch_data *sdata, return ret; } =20 - dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + dev_dbg(dev, "Retimer switch registered for index %u\n", index); } =20 if (!fwnode_property_present(fwnode, "mode-switch")) @@ -255,7 +257,7 @@ static int cros_typec_register_port(struct cros_typec_s= witch_data *sdata, return ret; } =20 - dev_dbg(dev, "Mode switch registered for index %llu\n", index); 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id kw3-20020a170902f90300b001d9fc6cbc51sm2487629plb.244.2024.02.09.23.09.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:09:59 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 12/22] platform/chrome: cros_typec_switch: Use dev_err_probe() Date: Fri, 9 Feb 2024 23:09:23 -0800 Message-ID: <20240210070934.2549994-13-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use dev_err_probe() helper so we can get better diagnostics when driver probes fails for any reason. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 36 +++++++-------------- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index 373e0e86ebfc..769de2889f2f 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -219,31 +219,23 @@ static int cros_typec_register_port(struct cros_typec= _switch_data *sdata, if (adev) prop_name =3D "_ADR"; =20 - if (!adev) { - dev_err(fwnode->dev, "Couldn't get ACPI handle\n"); - return -ENODEV; - } + if (!adev) + return dev_err_probe(fwnode->dev, -ENODEV, "Couldn't get ACPI handle\n"); =20 ret =3D fwnode_property_read_u32(fwnode, prop_name, &index); - if (ret) { - dev_err(fwnode->dev, "%s property wasn't found\n", prop_name); - return ret; - } + if (ret) + return dev_err_probe(fwnode->dev, ret, "%s property wasn't found\n", pro= p_name); =20 - if (index >=3D EC_USB_PD_MAX_PORTS) { - dev_err(fwnode->dev, "Invalid port index number: %u\n", index); - return -EINVAL; - } + if (index >=3D EC_USB_PD_MAX_PORTS) + return dev_err_probe(fwnode->dev, -EINVAL, "Invalid port index number: %= u\n", index); port->sdata =3D sdata; port->port_num =3D index; sdata->ports[index] =3D port; =20 if (fwnode_property_present(fwnode, "retimer-switch")) { ret =3D cros_typec_register_retimer(port, fwnode); - if (ret) { - dev_err(dev, "Retimer switch register failed\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "Retimer switch register failed\n"); =20 dev_dbg(dev, "Retimer switch registered for index %u\n", index); } @@ -252,10 +244,8 @@ static int cros_typec_register_port(struct cros_typec_= switch_data *sdata, return 0; =20 ret =3D cros_typec_register_mode_switch(port, fwnode); - if (ret) { - dev_err(dev, "Mode switch register failed\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "Mode switch register failed\n"); =20 dev_dbg(dev, "Mode switch registered for index %u\n", index); =20 @@ -269,10 +259,8 @@ static int cros_typec_register_switches(struct cros_ty= pec_switch_data *sdata) int nports, ret; =20 nports =3D device_get_child_node_count(dev); - if (nports =3D=3D 0) { - dev_err(dev, "No switch devices found.\n"); - return -ENODEV; - } + if (nports =3D=3D 0) + return dev_err_probe(dev, -ENODEV, "No switch devices found\n"); =20 device_for_each_child_node(dev, fwnode) { ret =3D cros_typec_register_port(sdata, fwnode); --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-oi1-f178.google.com (mail-oi1-f178.google.com [209.85.167.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 950813A8EA for ; Sat, 10 Feb 2024 07:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id b18-20020aa78712000000b006dfbecb5027sm1687313pfo.171.2024.02.09.23.10.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:01 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Benson Leung , Guenter Roeck , Prashant Malani , Tzung-Bi Shih Subject: [PATCH 13/22] dt-bindings: chrome: Add google,cros-ec-typec-switch binding Date: Fri, 9 Feb 2024 23:09:24 -0800 Message-ID: <20240210070934.2549994-14-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a binding for the USB type-c switch controls found on some ChromeOS Embedded Controllers (ECs). When this device is a mode switch, it takes one DisplayPort (DP) port as input and some number (possibly zero) of USB SuperSpeed ports (bundles of USB SS lanes) as input, and muxes those lanes into USB type-c SuperSpeed lanes suitable for the SSTRX1/2 pins on a usb-c-connector. When this device is an orientation switch, it redirects the DP lanes to the proper USB type-c SSTRX lanes. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Lee Jones Cc: Benson Leung Cc: Guenter Roeck Cc: Prashant Malani Cc: Tzung-Bi Shih Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- .../chrome/google,cros-ec-typec-switch.yaml | 365 ++++++++++++++++++ .../bindings/mfd/google,cros-ec.yaml | 5 + 2 files changed, 370 insertions(+) create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec= -typec-switch.yaml diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec-= switch.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec= -switch.yaml new file mode 100644 index 000000000000..17a0ba928f5d --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec-switch.= yaml @@ -0,0 +1,365 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Chrome OS EC(Embedded Controller) USB Type C Switch + +maintainers: + - Benson Leung + - Prashant Malani + - Stephen Boyd + +description: + Chrome OS devices have an Embedded Controller(EC) which has access to USB + Type C switching. This node is intended to allow the OS to control Type C + signal muxing for USB-C orientation and alternate modes. The node for th= is + device should be under a cros-ec node like google,cros-ec-spi. + +properties: + compatible: + const: google,cros-ec-typec-switch + + mode-switch: + description: Indicates this device controls altmode switching + type: boolean + + orientation-switch: + description: Indicates this device controls orientation switching + type: boolean + + mux-gpios: + description: GPIOs indicating which way the DP mux is steered + + no-hpd: + description: Indicates this device doesn't signal HPD for DisplayPort + type: boolean + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: Input port to receive DisplayPort (DP) data + unevaluatedProperties: false + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: DisplayPort data + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical DP data lane indexes + - 0 is DP ML0 lane + - 1 is DP ML1 lane + - 2 is DP ML2 lane + - 3 is DP ML3 lane + oneOf: + - items: + - const: 0 + - const: 1 + - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + + required: + - endpoint@0 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port to receive USB SuperSpeed (SS) data + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: USB SS data + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: USB SS data + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output port for USB-C data + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@1: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 1st type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@2: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 2nd type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@3: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 3rd type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@4: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 4th type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@5: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 5th type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@6: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 6th type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + endpoint@7: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB-C data for EC's 7th type-c port + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of physical USB-C data lane indexes. + - 0 is SSRX1 lane + - 1 is SSTX1 lane + - 2 is SSTX2 lane + - 3 is SSRX2 lane + minItems: 4 + maxItems: 4 + items: + maximum: 3 + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + - required: + - endpoint@2 + - required: + - endpoint@3 + - required: + - endpoint@4 + - required: + - endpoint@5 + - required: + - endpoint@6 + - required: + - endpoint@7 + + required: + - port@2 + anyOf: + - required: + - port@0 + - required: + - port@1 + +required: + - compatible + - ports + +allOf: + - if: + properties: + no-hpd: true + required: + - no-hpd + then: + properties: + ports: + required: + - port@0 + - if: + properties: + mode-switch: true + required: + - mode-switch + then: + properties: + ports: + required: + - port@0 + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts =3D <35 0>; + + typec-switch { + compatible =3D "google,cros-ec-typec-switch"; + mode-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + dp_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dp_phy>; + data-lanes =3D <0 1>; + }; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_in_0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_ss_0_out>; + }; + + usb_in_1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&usb_ss_1_out>; + }; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cros_typec_c0_ss: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_c0_ss>; + }; + + cros_typec_c1_ss: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&usb_c1_ss>; + }; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Do= cumentation/devicetree/bindings/mfd/google,cros-ec.yaml index ded396b28fba..563c51a4a39c 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -164,6 +164,10 @@ patternProperties: type: object $ref: /schemas/extcon/extcon-usbc-cros-ec.yaml# =20 + "^typec-switch[0-9]*$": + type: object + $ref: /schemas/chrome/google,cros-ec-typec-switch.yaml# + required: - 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id r19-20020aa78b93000000b006e02cdad499sm1693139pfd.99.2024.02.09.23.10.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:02 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 14/22] platform/chrome: cros_typec_switch: Add support for signaling HPD to drm_bridge Date: Fri, 9 Feb 2024 23:09:25 -0800 Message-ID: <20240210070934.2549994-15-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We can imagine that logically the EC is a device that has some number of DisplayPort (DP) connector inputs, some number of USB3 connector inputs, and some number of USB type-c connector outputs. If you squint enough it looks like a USB type-c dock. Logically there's a crossbar pin assignment capability within the EC that can assign USB and DP lanes to USB type-c lanes in the connector (i.e. USB type-c pin configurations). In reality, the EC is a microcontroller that has some TCPCs and redrivers connected to it over something like i2c and DP/USB from the AP is wired directly to those ICs, not the EC. This design allows the EC to abstract many possible USB and DP hardware configurations away from the AP (kernel) so that the AP can largely deal with USB and DP without thinking about USB Type-C much at all. The DP and USB data originate in the AP, not the EC, so it helps to think that the EC takes the DP and USB data as input to mux onto USB type-c ports even if it really doesn't do that. With this split design, the EC forwards the DP HPD state to the AP via a GPIO that's connected to the DP phy. Having that HPD state signaled directly to the DP phy uses precious hardware resources, a GPIO or two and a wire, and it also forces the TCPM to live on the EC. If we want to save costs and move more control of USB type-c to the kernel it's in our interest to get rid of the HPD GPIO entirely and signal HPD to the DP phy some other way. Luckily, the EC already exposes information about the USB Type-C stack to the kernel via the host command interface in the "google,cros-ec-typec" compatible driver, which parses EC messages related to USB type-c and effectively "replays" those messages to the kernel's USB typec subsystem. This includes the state of HPD, which can be interrogated and acted upon by registering a 'struct typec_mux_dev' with the typec subsystem. On DT based systems, the DP display pipeline is abstracted via a 'struct drm_bridge'. If we want to signal HPD state within the kernel we need to hook into the drm_bridge framework somehow to call drm_bridge_hpd_notify() when HPD state changes in the typec framework. Make a drm_bridge in the EC that attaches onto the end of the DP bridge chain and logically moves the display data onto a usb-c-connector. Signal HPD when the typec HPD state changes, as long as this new drm_bridge is the one that's supposed to signal HPD. Do that by registering a 'struct typec_mux_dev' with the typec framework and associating that struct with a usb-c-connector node and a drm_bridge. To keep this patch minimal, just signal HPD state to the drm_bridge chain. Later patches will add more features. Eventually we'll be able to inform userspace about which usb-c-connector node is displaying DP and what USB devices are connected to a connector. Note that this code is placed in the cros_typec_switch driver because that's where mode-switch devices on the EC are controlled by the AP. Logically this drm_bridge sits in front of the mode-switch on the EC, and if there is anything to control on the EC the 'EC_FEATURE_TYPEC_AP_MUX_SET' feature will be set. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/Kconfig | 3 +- drivers/platform/chrome/cros_typec_switch.c | 218 ++++++++++++++++++-- 2 files changed, 204 insertions(+), 17 deletions(-) diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kcon= fig index 7a83346bfa53..910aa8be9c84 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -287,7 +287,8 @@ config CHROMEOS_PRIVACY_SCREEN =20 config CROS_TYPEC_SWITCH tristate "ChromeOS EC Type-C Switch Control" - depends on MFD_CROS_EC_DEV && TYPEC && ACPI + depends on MFD_CROS_EC_DEV + depends on TYPEC default MFD_CROS_EC_DEV help If you say Y here, you get support for configuring the ChromeOS EC Type= -C diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index 769de2889f2f..d8fb6662cf8d 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,15 @@ #include #include =20 +#include +#include + +struct cros_typec_dp_bridge { + struct cros_typec_switch_data *sdata; + bool hpd_enabled; + struct drm_bridge bridge; +}; + /* Handles and other relevant data required for each port's switches. */ struct cros_typec_port { int port_num; @@ -30,7 +40,9 @@ struct cros_typec_port { struct cros_typec_switch_data { struct device *dev; struct cros_ec_device *ec; + bool typec_cmd_supported; struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; + struct cros_typec_dp_bridge *typec_dp_bridge; }; =20 static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, in= t port_num, u8 index, @@ -143,13 +155,60 @@ static int cros_typec_configure_mux(struct cros_typec= _switch_data *sdata, int po return 0; } =20 +static int cros_typec_dp_port_switch_set(struct typec_mux_dev *mode_switch, + struct typec_mux_state *state) +{ + struct cros_typec_port *port; + const struct typec_displayport_data *dp_data; + struct cros_typec_dp_bridge *typec_dp_bridge; + struct drm_bridge *bridge; + bool hpd_asserted; + + port =3D typec_mux_get_drvdata(mode_switch); + typec_dp_bridge =3D port->sdata->typec_dp_bridge; + if (!typec_dp_bridge) + return 0; + + bridge =3D &typec_dp_bridge->bridge; + + if (state->mode =3D=3D TYPEC_STATE_SAFE || state->mode =3D=3D TYPEC_STATE= _USB) { + if (typec_dp_bridge->hpd_enabled) + drm_bridge_hpd_notify(bridge, connector_status_disconnected); + + return 0; + } + + if (state->alt && state->alt->svid =3D=3D USB_TYPEC_DP_SID) { + if (typec_dp_bridge->hpd_enabled) { + dp_data =3D state->data; + hpd_asserted =3D dp_data->status & DP_STATUS_HPD_STATE; + + if (hpd_asserted) + drm_bridge_hpd_notify(bridge, connector_status_connected); + else + drm_bridge_hpd_notify(bridge, connector_status_disconnected); + } + } + + return 0; +} + static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, struct typec_mux_state *state) { struct cros_typec_port *port =3D typec_mux_get_drvdata(mode_switch); + struct cros_typec_switch_data *sdata =3D port->sdata; + int ret; + + ret =3D cros_typec_dp_port_switch_set(mode_switch, state); + if (ret) + return ret; =20 /* Mode switches have index 0. */ - return cros_typec_configure_mux(port->sdata, port->port_num, 0, state->mo= de, state->alt); + if (sdata->typec_cmd_supported) + return cros_typec_configure_mux(port->sdata, port->port_num, 0, state->m= ode, state->alt); + + return 0; } =20 static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) @@ -201,12 +260,77 @@ static int cros_typec_register_retimer(struct cros_ty= pec_port *port, struct fwno return PTR_ERR_OR_ZERO(port->retimer); } =20 +static int +cros_typec_dp_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_ERROR("Fix bridge driver to make connector optional!\n"); + return -EINVAL; + } + + return 0; +} + +static struct cros_typec_dp_bridge * +bridge_to_cros_typec_dp_bridge(struct drm_bridge *bridge) +{ + return container_of(bridge, struct cros_typec_dp_bridge, bridge); +} + +static void cros_typec_dp_bridge_hpd_enable(struct drm_bridge *bridge) +{ + struct cros_typec_dp_bridge *typec_dp_bridge; + + typec_dp_bridge =3D bridge_to_cros_typec_dp_bridge(bridge); + typec_dp_bridge->hpd_enabled =3D true; +} + +static void cros_typec_dp_bridge_hpd_disable(struct drm_bridge *bridge) +{ + struct cros_typec_dp_bridge *typec_dp_bridge; + + typec_dp_bridge =3D bridge_to_cros_typec_dp_bridge(bridge); + typec_dp_bridge->hpd_enabled =3D false; +} + +static const struct drm_bridge_funcs cros_typec_dp_bridge_funcs =3D { + .attach =3D cros_typec_dp_bridge_attach, + .hpd_enable =3D cros_typec_dp_bridge_hpd_enable, + .hpd_disable =3D cros_typec_dp_bridge_hpd_disable, +}; + +static int cros_typec_register_dp_bridge(struct cros_typec_switch_data *sd= ata, + struct fwnode_handle *fwnode) +{ + struct cros_typec_dp_bridge *typec_dp_bridge; + struct drm_bridge *bridge; + struct device *dev =3D sdata->dev; + + typec_dp_bridge =3D devm_kzalloc(dev, sizeof(*typec_dp_bridge), GFP_KERNE= L); + if (!typec_dp_bridge) + return -ENOMEM; + + typec_dp_bridge->sdata =3D sdata; + sdata->typec_dp_bridge =3D typec_dp_bridge; + bridge =3D &typec_dp_bridge->bridge; + + bridge->funcs =3D &cros_typec_dp_bridge_funcs; + bridge->of_node =3D dev->of_node; + bridge->type =3D DRM_MODE_CONNECTOR_DisplayPort; + bridge->ops |=3D DRM_BRIDGE_OP_HPD; + + return devm_drm_bridge_add(dev, bridge); +} + static int cros_typec_register_port(struct cros_typec_switch_data *sdata, struct fwnode_handle *fwnode) { struct cros_typec_port *port; struct device *dev =3D sdata->dev; struct acpi_device *adev; + struct device_node *np; + struct fwnode_handle *port_node; u32 index; int ret; const char *prop_name; @@ -218,9 +342,12 @@ static int cros_typec_register_port(struct cros_typec_= switch_data *sdata, adev =3D to_acpi_device_node(fwnode); if (adev) prop_name =3D "_ADR"; + np =3D to_of_node(fwnode); + if (np) + prop_name =3D "reg"; =20 - if (!adev) - return dev_err_probe(fwnode->dev, -ENODEV, "Couldn't get ACPI handle\n"); + if (!adev && !np) + return dev_err_probe(fwnode->dev, -ENODEV, "Couldn't get ACPI/OF device = handle\n"); =20 ret =3D fwnode_property_read_u32(fwnode, prop_name, &index); if (ret) @@ -232,41 +359,84 @@ static int cros_typec_register_port(struct cros_typec= _switch_data *sdata, port->port_num =3D index; sdata->ports[index] =3D port; =20 + port_node =3D fwnode; + if (np) + fwnode =3D fwnode_graph_get_port_parent(fwnode); + if (fwnode_property_present(fwnode, "retimer-switch")) { - ret =3D cros_typec_register_retimer(port, fwnode); - if (ret) - return dev_err_probe(dev, ret, "Retimer switch register failed\n"); + ret =3D cros_typec_register_retimer(port, port_node); + if (ret) { + dev_err_probe(dev, ret, "Retimer switch register failed\n"); + goto out; + } =20 dev_dbg(dev, "Retimer switch registered for index %u\n", index); } =20 - if (!fwnode_property_present(fwnode, "mode-switch")) - return 0; + if (fwnode_property_present(fwnode, "mode-switch")) { + ret =3D cros_typec_register_mode_switch(port, port_node); + if (ret) { + dev_err_probe(dev, ret, "Mode switch register failed\n"); + goto out; + } =20 - ret =3D cros_typec_register_mode_switch(port, fwnode); - if (ret) - return dev_err_probe(dev, ret, "Mode switch register failed\n"); + dev_dbg(dev, "Mode switch registered for index %u\n", index); + } =20 - dev_dbg(dev, "Mode switch registered for index %u\n", index); =20 +out: + if (np) + fwnode_handle_put(fwnode); return ret; } =20 static int cros_typec_register_switches(struct cros_typec_switch_data *sda= ta) { struct device *dev =3D sdata->dev; + struct fwnode_handle *devnode; struct fwnode_handle *fwnode; + struct fwnode_endpoint endpoint; int nports, ret; =20 nports =3D device_get_child_node_count(dev); if (nports =3D=3D 0) return dev_err_probe(dev, -ENODEV, "No switch devices found\n"); =20 - device_for_each_child_node(dev, fwnode) { - ret =3D cros_typec_register_port(sdata, fwnode); - if (ret) { + devnode =3D dev_fwnode(dev); + if (fwnode_graph_get_endpoint_count(devnode, 0)) { + fwnode_graph_for_each_endpoint(devnode, fwnode) { + ret =3D fwnode_graph_parse_endpoint(fwnode, &endpoint); + if (ret) { + fwnode_handle_put(fwnode); + goto err; + } + /* Skip if not a type-c output port */ + if (endpoint.port !=3D 2) + continue; + + ret =3D cros_typec_register_port(sdata, fwnode); + if (ret) { + fwnode_handle_put(fwnode); + goto err; + } + } + } else { + device_for_each_child_node(dev, fwnode) { + ret =3D cros_typec_register_port(sdata, fwnode); + if (ret) { + fwnode_handle_put(fwnode); + goto err; + } + } + } + + if (fwnode_property_present(devnode, "mode-switch")) { + fwnode =3D fwnode_graph_get_endpoint_by_id(devnode, 0, 0, 0); + if (fwnode) { + ret =3D cros_typec_register_dp_bridge(sdata, fwnode); fwnode_handle_put(fwnode); - goto err; + if (ret) + goto err; } } =20 @@ -280,6 +450,7 @@ static int cros_typec_switch_probe(struct platform_devi= ce *pdev) { struct device *dev =3D &pdev->dev; struct cros_typec_switch_data *sdata; + struct cros_ec_dev *ec_dev; =20 sdata =3D devm_kzalloc(dev, sizeof(*sdata), GFP_KERNEL); if (!sdata) @@ -288,6 +459,12 @@ static int cros_typec_switch_probe(struct platform_dev= ice *pdev) sdata->dev =3D dev; sdata->ec =3D dev_get_drvdata(pdev->dev.parent); =20 + ec_dev =3D dev_get_drvdata(&sdata->ec->ec->dev); + if (!ec_dev) + return -EPROBE_DEFER; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id e12-20020a17090ab38c00b0029652c53a32sm2831885pjr.33.2024.02.09.23.10.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:04 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 15/22] platform/chrome: cros_typec_switch: Support DP muxing via DRM lane assignment Date: Fri, 9 Feb 2024 23:09:26 -0800 Message-ID: <20240210070934.2549994-16-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement DP lane assignment in the drm_bridge atomic_check() callback so that DP altmode configurations like pinconf D can be supported and DP muxing can be implemented. In the DP altmode spec, pinconf C assigns all 4 SuperSpeed lanes in the usb-c-connector node to DP, while pinconf D assigns 2 SuperSpeed lanes to DP and 2 SuperSpeed lanes to USB. Use the 'data-lanes' property from the input DP graph port to calculate the maximum number of lanes coming from the DP source (either 2 or 4) and limit the lanes requested to the smaller of this or the pin configuration. Once we know the maximum number of lanes that can be assigned, map the DP lanes to the active type-c output port with the assigned pin configuration. Use the 'data-lanes' property from the active type-c output port to determine which logical DP lanes should be assigned to the output of the drm_bridge. For now assume the type-c pins are in the normal orientation. This design supports different DP altmode pin configurations and also allows us to effectively mux one DP phy to two different USB type-c connectors by wiring the physical DP lanes to one or the other USB type-c connectors in the hardware. For example, DP ML0/ML1 are hardwired to one USB type-c connector and DP ML2/ML3 are hardwired to the other connector. The 'data-lanes' of the first USB type-c port would be the default "<0 1 2 3>" while the 'data-lanes' of the second USB type-c port would be "<2 3 0 1>". Depending on the active USB type-c port, map the logical DP lane to the logical type-c lane, and then find the physical type-c lane corresponding to that logical lane from the type-c port's 'data-lanes' property. Once we have that, map the physical type-c lane to the physical DP lane and request that physical DP lane as the logical DP lane through the DRM lane assignment logic on the input of the drm_bridge. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 136 +++++++++++++++++++- 1 file changed, 131 insertions(+), 5 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index d8fb6662cf8d..adcbf8f44c98 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -19,20 +19,28 @@ #include #include =20 +#include #include #include =20 struct cros_typec_dp_bridge { + /* TODO: Add mutex lock to protect active_port with respect to drm/typec = framework calls */ + struct cros_typec_port *active_port; struct cros_typec_switch_data *sdata; + size_t max_lanes; bool hpd_enabled; struct drm_bridge bridge; }; =20 +#define USBC_LANES_COUNT 4 + /* Handles and other relevant data required for each port's switches. */ struct cros_typec_port { int port_num; struct typec_mux_dev *mode_switch; struct typec_retimer *retimer; + size_t num_dp_lanes; + u32 lane_mapping[USBC_LANES_COUNT]; struct cros_typec_switch_data *sdata; }; =20 @@ -163,6 +171,8 @@ static int cros_typec_dp_port_switch_set(struct typec_m= ux_dev *mode_switch, struct cros_typec_dp_bridge *typec_dp_bridge; struct drm_bridge *bridge; bool hpd_asserted; + u8 pin_assign; + size_t num_lanes, max_lanes; =20 port =3D typec_mux_get_drvdata(mode_switch); typec_dp_bridge =3D port->sdata->typec_dp_bridge; @@ -172,17 +182,41 @@ static int cros_typec_dp_port_switch_set(struct typec= _mux_dev *mode_switch, bridge =3D &typec_dp_bridge->bridge; =20 if (state->mode =3D=3D TYPEC_STATE_SAFE || state->mode =3D=3D TYPEC_STATE= _USB) { - if (typec_dp_bridge->hpd_enabled) - drm_bridge_hpd_notify(bridge, connector_status_disconnected); + /* Clear active port when port isn't in DP mode */ + port->num_dp_lanes =3D 0; + if (typec_dp_bridge->active_port =3D=3D port) { + typec_dp_bridge->active_port =3D NULL; + if (typec_dp_bridge->hpd_enabled) + drm_bridge_hpd_notify(bridge, connector_status_disconnected); + } =20 return 0; } =20 if (state->alt && state->alt->svid =3D=3D USB_TYPEC_DP_SID) { - if (typec_dp_bridge->hpd_enabled) { - dp_data =3D state->data; - hpd_asserted =3D dp_data->status & DP_STATUS_HPD_STATE; + dp_data =3D state->data; + hpd_asserted =3D dp_data->status & DP_STATUS_HPD_STATE; + /* + * Assume the first port to have HPD asserted is the one muxed + * to DP (i.e. active_port). When there's only one port this + * delays setting the active_port until HPD is asserted, but + * before that the drm_connector looks disconnected so + * active_port doesn't need to be set. + */ + if (hpd_asserted && !typec_dp_bridge->active_port) + typec_dp_bridge->active_port =3D port; =20 + /* Determine number of logical DP lanes from pin assignment */ + pin_assign =3D DP_CONF_GET_PIN_ASSIGN(dp_data->conf); + if (pin_assign =3D=3D DP_PIN_ASSIGN_D) + num_lanes =3D 2; + else + num_lanes =3D 4; + max_lanes =3D typec_dp_bridge->max_lanes; + port->num_dp_lanes =3D min(num_lanes, max_lanes); + + /* Only notify hpd state for the port that has entered DP mode. */ + if (typec_dp_bridge->hpd_enabled && typec_dp_bridge->active_port =3D=3D = port) { if (hpd_asserted) drm_bridge_hpd_notify(bridge, connector_status_connected); else @@ -278,6 +312,81 @@ bridge_to_cros_typec_dp_bridge(struct drm_bridge *brid= ge) return container_of(bridge, struct cros_typec_dp_bridge, bridge); } =20 +static int dp_lane_to_typec_lane(unsigned int dp_lane) +{ + switch (dp_lane) { + case 0: + return 2; + case 1: + return 3; + case 2: + return 1; + case 3: + return 0; + } + + return -EINVAL; +} + +static int typec_to_dp_lane(unsigned int typec_lane) +{ + switch (typec_lane) { + case 0: + return 3; + case 1: + return 2; + case 2: + return 0; + case 3: + return 1; + } + + return -EINVAL; +} + +static int cros_typec_dp_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct cros_typec_dp_bridge *typec_dp_bridge; + struct drm_lane_cfg *in_lanes; + size_t num_lanes; + struct cros_typec_port *port; + int i, typec_lane; + + typec_dp_bridge =3D bridge_to_cros_typec_dp_bridge(bridge); + if (!typec_dp_bridge->active_port) + return -ENODEV; + + port =3D typec_dp_bridge->active_port; + + num_lanes =3D port->num_dp_lanes; + in_lanes =3D kcalloc(num_lanes, sizeof(*in_lanes), GFP_KERNEL); + if (!in_lanes) + return -ENOMEM; + + bridge_state->input_bus_cfg.lanes =3D in_lanes; + bridge_state->input_bus_cfg.num_lanes =3D num_lanes; + + for (i =3D 0; i < num_lanes; i++) { + /* Get physical type-c lane for DP lane */ + typec_lane =3D dp_lane_to_typec_lane(i); + if (typec_lane < 0) { + DRM_ERROR("Invalid type-c lane configuration\n"); + return -EINVAL; + } + + /* Map to logical type-c lane */ + typec_lane =3D port->lane_mapping[typec_lane]; + + /* Map logical type-c lane to logical DP lane */ + in_lanes[i].logical =3D typec_to_dp_lane(typec_lane); + } + + return 0; +} + static void cros_typec_dp_bridge_hpd_enable(struct drm_bridge *bridge) { struct cros_typec_dp_bridge *typec_dp_bridge; @@ -296,6 +405,10 @@ static void cros_typec_dp_bridge_hpd_disable(struct dr= m_bridge *bridge) =20 static const struct drm_bridge_funcs cros_typec_dp_bridge_funcs =3D { .attach =3D cros_typec_dp_bridge_attach, + .atomic_check =3D cros_typec_dp_bridge_atomic_check, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, .hpd_enable =3D cros_typec_dp_bridge_hpd_enable, .hpd_disable =3D cros_typec_dp_bridge_hpd_disable, }; @@ -305,6 +418,7 @@ static int cros_typec_register_dp_bridge(struct cros_ty= pec_switch_data *sdata, { struct cros_typec_dp_bridge *typec_dp_bridge; struct drm_bridge *bridge; + int num_lanes; struct device *dev =3D sdata->dev; =20 typec_dp_bridge =3D devm_kzalloc(dev, sizeof(*typec_dp_bridge), GFP_KERNE= L); @@ -313,6 +427,12 @@ static int cros_typec_register_dp_bridge(struct cros_t= ypec_switch_data *sdata, =20 typec_dp_bridge->sdata =3D sdata; sdata->typec_dp_bridge =3D typec_dp_bridge; + + num_lanes =3D fwnode_property_count_u32(fwnode, "data-lanes"); + if (num_lanes < 0) + num_lanes =3D 4; + typec_dp_bridge->max_lanes =3D num_lanes; + bridge =3D &typec_dp_bridge->bridge; =20 bridge->funcs =3D &cros_typec_dp_bridge_funcs; @@ -333,6 +453,7 @@ static int cros_typec_register_port(struct cros_typec_s= witch_data *sdata, struct fwnode_handle *port_node; u32 index; int ret; + const u32 default_lane_mapping[] =3D { 0, 1, 2, 3 }; const char *prop_name; =20 port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id p6-20020a625b06000000b006db05eb1301sm1726988pfb.21.2024.02.09.23.10.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:06 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 16/22] platform/chrome: cros_typec_switch: Support orientation-switch Date: Fri, 9 Feb 2024 23:09:27 -0800 Message-ID: <20240210070934.2549994-17-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register an orientation switch with the typec subsystem when the 'orientation-switch' DT property is present. In these sorts of hardware designs, the DP phy lanes are wired directly to the usb-c-connector. The EC signals entry and exit of DP mode on the port, and the DP phy lanes are assigned to the pins based on the port orientation (normal or reverse). Stash the orientation of the port and simply wait for the atomic_check phase to request the desired DP lane assignment (normal or reverse). Don't restrict this to the presence of the mode-switch property because it's possible for this device to only be an orientation-switch, in which case the DP mode entry is signaled externally (e.g. through an HPD pin on the DP source). Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 84 ++++++++++++++++++--- 1 file changed, 72 insertions(+), 12 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index adcbf8f44c98..c22c2531327a 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -38,9 +38,11 @@ struct cros_typec_dp_bridge { struct cros_typec_port { int port_num; struct typec_mux_dev *mode_switch; + struct typec_switch_dev *orientation_switch; struct typec_retimer *retimer; size_t num_dp_lanes; u32 lane_mapping[USBC_LANES_COUNT]; + enum typec_orientation orientation; struct cros_typec_switch_data *sdata; }; =20 @@ -245,6 +247,21 @@ static int cros_typec_mode_switch_set(struct typec_mux= _dev *mode_switch, return 0; } =20 +static int cros_typec_dp_port_orientation_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct cros_typec_port *port =3D typec_switch_get_drvdata(sw); + + /* + * Lane remapping is in cros_typec_dp_bridge_atomic_check(). Whenever + * an orientation changes HPD will go low and then high again so the + * atomic check handles the orientation change. + */ + port->orientation =3D orientation; + + return 0; +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) { struct cros_typec_port *port =3D typec_retimer_get_drvdata(retimer); @@ -280,6 +297,21 @@ static int cros_typec_register_mode_switch(struct cros= _typec_port *port, return PTR_ERR_OR_ZERO(port->mode_switch); } =20 +static int cros_typec_register_orientation_switch(struct cros_typec_port *= port, + struct fwnode_handle *fwnode) +{ + struct typec_switch_desc orientation_switch_desc =3D { + .fwnode =3D fwnode, + .drvdata =3D port, + .name =3D fwnode_get_name(fwnode), + .set =3D cros_typec_dp_port_orientation_set, + }; + + port->orientation_switch =3D typec_switch_register(port->sdata->dev, &ori= entation_switch_desc); + + return PTR_ERR_OR_ZERO(port->orientation_switch); +} + static int cros_typec_register_retimer(struct cros_typec_port *port, struc= t fwnode_handle *fwnode) { struct typec_retimer_desc retimer_desc =3D { @@ -328,17 +360,35 @@ static int dp_lane_to_typec_lane(unsigned int dp_lane) return -EINVAL; } =20 -static int typec_to_dp_lane(unsigned int typec_lane) +static int typec_to_dp_lane(unsigned int typec_lane, + enum typec_orientation orientation) { - switch (typec_lane) { - case 0: - return 3; - case 1: - return 2; - case 2: - return 0; - case 3: - return 1; + switch (orientation) { + case TYPEC_ORIENTATION_NONE: + case TYPEC_ORIENTATION_NORMAL: + switch (typec_lane) { + case 0: + return 3; + case 1: + return 2; + case 2: + return 0; + case 3: + return 1; + } + break; + case TYPEC_ORIENTATION_REVERSE: + switch (typec_lane) { + case 0: + return 0; + case 1: + return 1; + case 2: + return 3; + case 3: + return 2; + } + break; } =20 return -EINVAL; @@ -381,7 +431,7 @@ static int cros_typec_dp_bridge_atomic_check(struct drm= _bridge *bridge, typec_lane =3D port->lane_mapping[typec_lane]; =20 /* Map logical type-c lane to logical DP lane */ - in_lanes[i].logical =3D typec_to_dp_lane(typec_lane); + in_lanes[i].logical =3D typec_to_dp_lane(typec_lane, port->orientation); } =20 return 0; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id fn7-20020a056a002fc700b006e0651ec052sm1650575pfb.32.2024.02.09.23.10.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:07 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 17/22] platform/chrome: cros_typec_switch: Handle lack of HPD information Date: Fri, 9 Feb 2024 23:09:28 -0800 Message-ID: <20240210070934.2549994-18-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some EC firmwares on Trogdor/Strongbad boards don't properly indicate the state of DP HPD on a type-c port. Instead, the EC only indicates that DP mode is entered or exited for a type-c port. To make matters worse, on these firmwares the DP signal is muxed between two USB type-c connectors, so we can't use the HPD state to figure out which type-c port is actually displaying DP. Read the state of the EC's analog mux from the hpd notification callback to figure out which type-c port is displaying DP. This circumvents the entire host command/message interface, because it doesn't work all the time. Only do this when we have the mux-gpios property in DT, indicating that we have to read the EC gpio state to figure this out. For now we only support a single gpio "bit", so there can only be two USB type-c ports. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 33 ++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index c22c2531327a..edd628eab7da 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -26,6 +27,7 @@ struct cros_typec_dp_bridge { /* TODO: Add mutex lock to protect active_port with respect to drm/typec = framework calls */ struct cros_typec_port *active_port; + struct gpio_desc *mux_gpio; struct cros_typec_switch_data *sdata; size_t max_lanes; bool hpd_enabled; @@ -453,6 +455,29 @@ static void cros_typec_dp_bridge_hpd_disable(struct dr= m_bridge *bridge) typec_dp_bridge->hpd_enabled =3D false; } =20 +static void cros_typec_dp_bridge_hpd_notify(struct drm_bridge *bridge, + enum drm_connector_status status) +{ + struct cros_typec_dp_bridge *typec_dp_bridge; + struct cros_typec_switch_data *sdata; + struct gpio_desc *mux_gpio; + int mux_val; + + typec_dp_bridge =3D bridge_to_cros_typec_dp_bridge(bridge); + mux_gpio =3D typec_dp_bridge->mux_gpio; + + /* + * Some ECs don't notify AP when HPD goes high or low so we have to + * read the EC GPIO that controls the mux to figure out which type-c + * port is connected to DP. + */ + if (mux_gpio) { + sdata =3D typec_dp_bridge->sdata; + mux_val =3D gpiod_get_value_cansleep(mux_gpio); + typec_dp_bridge->active_port =3D sdata->ports[mux_val]; + } +} + static const struct drm_bridge_funcs cros_typec_dp_bridge_funcs =3D { .attach =3D cros_typec_dp_bridge_attach, .atomic_check =3D cros_typec_dp_bridge_atomic_check, @@ -461,6 +486,7 @@ static const struct drm_bridge_funcs cros_typec_dp_brid= ge_funcs =3D { .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, .hpd_enable =3D cros_typec_dp_bridge_hpd_enable, .hpd_disable =3D cros_typec_dp_bridge_hpd_disable, + .hpd_notify =3D cros_typec_dp_bridge_hpd_notify, }; =20 static int cros_typec_register_dp_bridge(struct cros_typec_switch_data *sd= ata, @@ -478,6 +504,10 @@ static int cros_typec_register_dp_bridge(struct cros_t= ypec_switch_data *sdata, typec_dp_bridge->sdata =3D sdata; sdata->typec_dp_bridge =3D typec_dp_bridge; =20 + typec_dp_bridge->mux_gpio =3D devm_gpiod_get_optional(dev, "mux", 0); + if (IS_ERR(typec_dp_bridge->mux_gpio)) + return PTR_ERR(typec_dp_bridge->mux_gpio); + num_lanes =3D fwnode_property_count_u32(fwnode, "data-lanes"); if (num_lanes < 0) num_lanes =3D 4; @@ -488,7 +518,8 @@ static int cros_typec_register_dp_bridge(struct cros_ty= pec_switch_data *sdata, bridge->funcs =3D &cros_typec_dp_bridge_funcs; bridge->of_node =3D dev->of_node; bridge->type =3D DRM_MODE_CONNECTOR_DisplayPort; - bridge->ops |=3D DRM_BRIDGE_OP_HPD; + if (!fwnode_property_present(dev_fwnode(dev), "no-hpd")) + bridge->ops |=3D DRM_BRIDGE_OP_HPD; =20 return devm_drm_bridge_add(dev, bridge); } --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB14F3C468 for ; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id bx34-20020a056a02052200b005d8b69f882esm2566257pgb.38.2024.02.09.23.10.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:09 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Benson Leung , Guenter Roeck Subject: [PATCH 18/22] dt-bindings: chrome: Add binding for ChromeOS Pogo pin connector Date: Fri, 9 Feb 2024 23:09:29 -0800 Message-ID: <20240210070934.2549994-19-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe the set of pins used to connect the detachable keyboard on detachable ChromeOS devices. The set of pins is called the "pogo pins". It's basically USB 2.0 with an extra pin for base detection. We expect to find a keyboard on the other side of this connector with a specific vid/pid, so describe that as a child device at the port of the usb device connected upstream. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Benson Leung Cc: Guenter Roeck Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- .../chrome/google,pogo-pin-connector.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/chrome/google,pogo-pi= n-connector.yaml diff --git a/Documentation/devicetree/bindings/chrome/google,pogo-pin-conne= ctor.yaml b/Documentation/devicetree/bindings/chrome/google,pogo-pin-connec= tor.yaml new file mode 100644 index 000000000000..5ba68fd95fcd --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,pogo-pin-connector.ya= ml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,pogo-pin-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Pogo Pin Connector + +maintainers: + - Stephen Boyd + +properties: + compatible: + const: google,pogo-pin-connector + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to USB2 port providing USB signals + required: + - endpoint + +patternProperties: + "^keyboard@[0-9a-f]{1,2}$": + description: The detachable keyboard + type: object + $ref: /schemas/usb/usb-device.yaml + +required: + - compatible + - '#address-cells' + - '#size-cells' + - port + +additionalProperties: false + +examples: + - | + connector { + compatible =3D "google,pogo-pin-connector"; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id d4-20020a170903230400b001d9469967e8sm2495954plh.122.2024.02.09.23.10.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:11 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 19/22] arm64: dts: qcom: sc7180: quackingstick: Disable instead of delete usb_c1 Date: Fri, 9 Feb 2024 23:09:30 -0800 Message-ID: <20240210070934.2549994-20-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's simpler to reason about things if we disable nodes instead of deleting them. Disable the second usb type-c connector node on quackingstick instead of deleting it so that we can reason about ports more easily. Cc: Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- .../arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 5f06842c683b..b7de9fd3fa20 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -10,9 +10,6 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" =20 -/* This board only has 1 USB Type-C port. */ -/delete-node/ &usb_c1; - / { ppvar_lcd: ppvar-lcd-regulator { compatible =3D "regulator-fixed"; @@ -136,6 +133,11 @@ pp3300_disp_on: &pp3300_dx_edp { gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; }; =20 +/* This board only has 1 USB Type-C port. */ +&usb_c1 { + status =3D "disabled"; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id gm15-20020a17090b100f00b00296f780de33sm2898701pjb.36.2024.02.09.23.10.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:12 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 20/22] arm64: dts: qcom: sc7180: pazquel: Add missing comment header Date: Fri, 9 Feb 2024 23:09:31 -0800 Message-ID: <20240210070934.2549994-21-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We put a header before modifying pinctrl nodes defined in sc7180-trogdor.dtsi in every other file. Add one here so we know that this section is for pinctrl modifications. Cc: Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 8823edbb4d6e..73aa75621721 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -83,6 +83,8 @@ &pp3300_dx_edp { gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; }; =20 +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + &en_pp3300_dx_edp { pins =3D "gpio67"; }; --=20 https://chromeos.dev From nobody Sun Feb 8 13:45:53 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 606CC3D0CF for ; Sat, 10 Feb 2024 07:10:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707549018; cv=none; b=u7aNLU92FgYqBvI4qkUe/LPIS+ynmi5XgwXjAOWZAucOeKNrUDZmu8XbkvGqLoM54zKMsBP/g2vK1AC06mkALzoArIUhGuTyzNRC/mTBrQFPF6BVfdbuvCEmSW2nAm6QlLMjw74C5cUo9z1zNBad8PzqhQIG6ED23jOlKc8Cgl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707549018; c=relaxed/simple; bh=Gr/cjYsEPFS9YtkIRTTBs4NFAZVd1rZbQ149cefKuGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P5hufHILYFbYj0AcwxDna5L1K2x7s8OTvmcu3dPplFjv9sOT57OLpkiBJtB8oIpQ4YGG4ybAxBc2sKXhUr4zF3AakkpW/BrrkdHqFXjhTw1MmktQBPVP3bBkcYsUOUaJMbcFRj/DCs/0G0QwDiSnmliwLhgOF9BSXPPDuG7Xdek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=BaKaH5If; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BaKaH5If" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1d751bc0c15so16127765ad.2 for ; Fri, 09 Feb 2024 23:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1707549015; x=1708153815; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uRdeafd1oFQ133DVCweG1iG5WfY6aqYTpGOenc4j5OI=; b=BaKaH5IfZrHA1ZsmjwfFs6OC5FoDrnN1/2GFDQwhPW0jwF8YCVQODsATXJpkd0eEHN 5iHEuOnxr5NJq2YLoWom6ADvAUM1yKLgkcUe/0BeqfVZidQjfyYLE5FEWBlrEpGK32e1 qGxnhE0qeyM3RaXLG9QkwxxhtZGI186YmjBIM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707549015; x=1708153815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uRdeafd1oFQ133DVCweG1iG5WfY6aqYTpGOenc4j5OI=; b=Nxh6WI2iUGLHeFUS0gQoEjLYUHjUquj1PsqVvfRER2e0SF22VcU9NqQK1hMBQbpxkc kuRdAGEUG8tRor0+0jYtTUIRwH6Qdra4oehSfEtTol8c/mhFXYBSbQksjAC+gHLypG/l fxLa+eT3ZtaEQTCAwdZ89NRg7an6z1SoYjkPBypu84mxzkFtXoMjZlFT+AxlfkidZMoc iBfwqB8/tCETQvyfZX/AzNjcPHoUACebz+ifeh9VP3d4NhCPOheCAYzBnQT8yiK4n70J 9aFaoxBvK+IbAcyCTC0vEkCl9/6KVOGBy9JU3gMB7flIvnyyZ62rMDkLnOaQEVhPyH8J M3Gg== X-Gm-Message-State: AOJu0YyqjxH620Wdlrjz/GJE0bACtmsyi5wNARHUdHK3IReAQUa2intl IrumRttdHal33RLtTYs2JSuo1f74tkThy+i2WnC7MOqsHBh9QRlwSakbelmAjg== X-Google-Smtp-Source: AGHT+IEPebBATSj4xLUJJxKqaWO05lkMH0b2sVPfG4NHB+qrjNTT6Gm4CBU6EDUiPGoN1DCdFsgbxg== X-Received: by 2002:a17:903:1c3:b0:1d9:f5ef:a053 with SMTP id e3-20020a17090301c300b001d9f5efa053mr2125350plh.28.1707549015013; Fri, 09 Feb 2024 23:10:15 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWhvoFacBD758Jr2FAazJV9jtMATSRjM6lLTU+VryD1+MXyMlRL1JUn+pSH1X3C2lhy6Ff4fxx2yZCB8vupGbS6DRn0OfEczHy8cpXMWP5fxR/OSAFV60tnXCLb0nPrl8cPmN5ZFz8p2O0kuh3r1DcBwKJI2BXXA/VcLhQZ+u2ULK18qkk8AHHshWI2iNFS8e3ifKj3IU3kff15f0vfC16jg/drG/ON3QVqEHoemowPSD/o2ewg2OPp3QxenNh1y7nM8UC2oVTGjlvpGLJujkSOC0FKmI0pxQa0MpMBDQdTCdM1wFmfdYjHqSZ9Ry4XiEGfy9lJv12hUCNJfVI+GinDIzp+27LGI1EGGxHrcKOz5GVgvhT4FUWpxcpIwwYJCgKxjC1w67ZNCt+Tm/oq1bIzCnIRS0EP6tz6XOVtej26z1pYNfusp2NMDmPQqVL2w4JSyRqSTruv4QuqKd9q9dgz0TPest5ECnp3ZVb2/pMKUFav+pWx2UnG6en1gbZ/9avZaMYMGBoiog58yw== Received: from localhost (175.199.125.34.bc.googleusercontent.com. [34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id h9-20020a170902f2c900b001d921bcc621sm2478586plc.243.2024.02.09.23.10.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:14 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 21/22] arm64: dts: qcom: sc7180-trogdor: Make clamshell/detachable fragments Date: Fri, 9 Feb 2024 23:09:32 -0800 Message-ID: <20240210070934.2549994-22-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At a high-level, detachable Trogdors (sometimes known as Strongbads) don't have a cros_ec keyboard, while all clamshell Trogdors (only known as Trogdors) always have a cros_ec keyboard. Looking closer though, all clamshells have a USB type-A connector and a hardwired USB camera. And all detachables replace the USB camera with a MIPI based one and swap the USB type-a connector for the detachable keyboard pogo pins. Split the detachable and clamshell bits into different files so we can describe these differences in one place instead of in each board that includes sc7180-trogdor.dtsi. For now this is just the keyboard part, but eventually this will include the type-a port and the pogo pins. Cc: Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- .../boot/dts/qcom/sc7180-trogdor-clamshell.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 5 +---- .../boot/dts/qcom/sc7180-trogdor-detachable.dtsi | 12 ++++++++++++ .../arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 7 +------ .../boot/dts/qcom/sc7180-trogdor-kingoftown.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 2 +- .../boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 7 +------ arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 2 +- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 5 +---- 11 files changed, 30 insertions(+), 26 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi b/arch/= arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi new file mode 100644 index 000000000000..bcf3df463f80 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts framgent for clamshells + * + * Copyright 2024 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 7765c8f64905..6e6a4643c4dd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -7,6 +7,7 @@ =20 #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-detachable.dtsi" =20 /* Deleted nodes from sc7180-trogdor.dtsi */ =20 @@ -80,10 +81,6 @@ &camcc { }; =20 &cros_ec { - keyboard-controller { - compatible =3D "google,cros-ec-keyb-switches"; - }; - cros_ec_proximity: proximity { compatible =3D "google,cros-ec-mkbp-proximity"; label =3D "proximity-wifi"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi b/arch= /arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi new file mode 100644 index 000000000000..ab0f30288871 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts framgent for detachables + * + * Copyright 2024 Google LLC. + */ + +&cros_ec { + keyboard-controller { + compatible =3D "google,cros-ec-keyb-switches"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/a= rm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 2ba3bbf3b9ad..a86a6c5c3f67 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -8,6 +8,7 @@ /* This file must be included after sc7180-trogdor.dtsi */ =20 #include "sc7180-trogdor-rt5682i-sku.dtsi" +#include "sc7180-trogdor-detachable.dtsi" =20 / { /* BOARD-SPECIFIC TOP LEVEL NODES */ @@ -135,12 +136,6 @@ &camcc { status =3D "okay"; }; =20 -&cros_ec { - keyboard-controller { - compatible =3D "google,cros-ec-keyb-switches"; - }; -}; - &panel { compatible =3D "samsung,atna33xc20"; enable-gpios =3D <&tlmm 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/= arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index d6db7d83adcf..655bea928e52 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -9,7 +9,7 @@ =20 #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" #include "sc7180-trogdor-rt5682s-sku.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm6= 4/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index e9f213d27711..c3fd6760de7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,8 +5,7 @@ * Copyright 2020 Google LLC. */ =20 -/* This file must be included after sc7180-trogdor.dtsi */ -#include +#include "sc7180-trogdor-clamshell.dtsi" =20 &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 73aa75621721..60ccd3abddfc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -6,7 +6,7 @@ */ =20 /* This file must be included after sc7180-trogdor.dtsi */ -#include +#include "sc7180-trogdor-clamshell.dtsi" =20 &ap_sar_sensor { compatible =3D "semtech,sx9324"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 0be62331f982..43b2583f0f26 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -7,7 +7,7 @@ =20 #include "sc7180-trogdor.dtsi" /* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index b7de9fd3fa20..00229b1515e6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -9,6 +9,7 @@ =20 #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" +#include "sc7180-trogdor-detachable.dtsi" =20 / { ppvar_lcd: ppvar-lcd-regulator { @@ -44,12 +45,6 @@ &camcc { status =3D "okay"; }; =20 -&cros_ec { - keyboard-controller { - compatible =3D "google,cros-ec-keyb-switches"; - }; -}; - &gpio_keys { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/bo= ot/dts/qcom/sc7180-trogdor-r1.dts index c9667751a990..4b43a9b273c0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -9,7 +9,7 @@ =20 #include "sc7180-trogdor.dtsi" /* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arc= h/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 305ad127246e..1d9fc61b6550 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -8,6 +8,7 @@ /dts-v1/; =20 #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-detachable.dtsi" =20 / { avdd_lcd: avdd-lcd-regulator { @@ -104,10 +105,6 @@ &cros_ec { base_detection: cbas { compatible =3D "google,cros-cbas"; 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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id jc9-20020a17090325c900b001d9f4c562b2sm2504374plb.23.2024.02.09.23.10.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:16 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 22/22] arm64: dts: qcom: sc7180-trogdor: Wire up USB and DP to usb-c-connectors Date: Fri, 9 Feb 2024 23:09:33 -0800 Message-ID: <20240210070934.2549994-23-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fully describe the USB type-c and DP topology on sc7180 Trogdor devices. Most Trogdor devices have two USB type-c ports (i.e. usb-c-connector nodes), but quackingstick only has one. Also, clamshell devices such as Lazor have a USB webcam connected to the USB hub, while detachable devices such as Wormdingler don't have a webcam, or a USB type-a connector. Instead they have the pogo pins for the detachable keyboard. Fully describing the topology like this will let us expose information about what devices are connected to which physical USB connector (type-A or type-C) and which port is connected to an external display for DP. Cc: Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- .../dts/qcom/sc7180-trogdor-clamshell.dtsi | 21 +++ .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 47 +++++ .../dts/qcom/sc7180-trogdor-detachable.dtsi | 13 ++ .../dts/qcom/sc7180-trogdor-homestar.dtsi | 47 +++++ .../dts/qcom/sc7180-trogdor-kingoftown.dts | 55 ++++++ .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 55 ++++++ .../boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 55 ++++++ .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 44 +++++ .../qcom/sc7180-trogdor-quackingstick.dtsi | 31 ++++ .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 47 +++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 175 ++++++++++++++++++ 11 files changed, 590 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi b/arch/= arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi index bcf3df463f80..96137202fc64 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi @@ -7,3 +7,24 @@ =20 /* This file must be included after sc7180-trogdor.dtsi */ #include + +/ { + usb-a-connector { + compatible =3D "usb-a-connector"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_a0_hs: endpoint@0 { + reg =3D <0>; + /* Remote endpoint filled in by board */ + }; + + usb_a0_ss: endpoint@1 { + reg =3D <1>; + /* Remote endpoint filled in by board */ + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 6e6a4643c4dd..4cf5b1e20b27 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -135,6 +135,17 @@ skin-temp-thermistor@1 { }; }; =20 +&pogo_pins { + keyboard@4 { + compatible =3D "usb18d1,504c"; + reg =3D <4>; + }; +}; + +&pogo_pins_in { + remote-endpoint =3D <&usb_hub_dfp4_hs>; +}; + &pp1800_uf_cam { status =3D "okay"; }; @@ -176,6 +187,42 @@ &sound_multimedia0_codec { sound-dai =3D <&adau7002>; }; =20 +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp1_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp1_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_hub_dfp1_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp1_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + +&usb_hub_dfp4_hs { + remote-endpoint =3D <&pogo_pins_in>; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ =20 &en_pp3300_dx_edp { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi b/arch= /arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi index ab0f30288871..b24a0213a477 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi @@ -5,6 +5,19 @@ * Copyright 2024 Google LLC. */ =20 +/ { + pogo_pins: pogo-pin-connector { + compatible =3D "google,pogo-pin-connector"; + #address-cells =3D <1>; + #size-cells =3D <0>; + /* Detachable keyboard populated for each board */ + port { + pogo_pins_in: endpoint { + }; + }; + }; +}; + &cros_ec { keyboard-controller { compatible =3D "google,cros-ec-keyb-switches"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/a= rm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index a86a6c5c3f67..9e32c984ab32 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -162,6 +162,17 @@ skin-temp-thermistor@1 { }; }; =20 +&pogo_pins { + keyboard@3 { + compatible =3D "usb18d1,5052"; + reg =3D <3>; + }; +}; + +&pogo_pins_in { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + &pp1800_uf_cam { status =3D "okay"; }; @@ -190,6 +201,42 @@ &sound_multimedia1_codec { sound-dai =3D <&max98360a>, <&max98360a_1>, <&max98360a_2>, <&max98360a_3= > ; }; =20 +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp4_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp4_ss>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&pogo_pins_in>; +}; + +&usb_hub_dfp4_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp4_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + &wifi { qcom,ath10k-calibration-variant =3D "GO_HOMESTAR"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/= arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index 655bea928e52..476c0a2f30da 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -78,6 +78,61 @@ &pp3300_dx_edp { gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; }; =20 +&usb_a0_hs { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + +&usb_a0_ss { + remote-endpoint =3D <&usb_hub_dfp3_ss>; +}; + +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp1_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp1_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_hub_2_x { + camera@4 { + compatible =3D "usb4f2,b75a"; + reg =3D <4>; + }; +}; + +&usb_hub_dfp1_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp1_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&usb_a0_hs>; +}; + +&usb_hub_dfp3_ss { + remote-endpoint =3D <&usb_a0_ss>; +}; + &wifi { qcom,ath10k-calibration-variant =3D "GO_KINGOFTOWN"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm6= 4/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index c3fd6760de7a..2603607ebd80 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -68,6 +68,61 @@ &trackpad { interrupts =3D <58 IRQ_TYPE_EDGE_FALLING>; }; =20 +&usb_hub_2_x { + camera@1 { + compatible =3D "usb408,a092"; + reg =3D <1>; + }; +}; + +&usb_a0_hs { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + +&usb_a0_ss { + remote-endpoint =3D <&usb_hub_dfp3_ss>; +}; + +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp4_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp4_ss>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&usb_a0_hs>; +}; + +&usb_hub_dfp3_ss { + remote-endpoint =3D <&usb_a0_ss>; +}; + +&usb_hub_dfp4_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp4_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + &wifi { qcom,ath10k-calibration-variant =3D "GO_LAZOR"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 60ccd3abddfc..dee06c64b59a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -83,6 +83,61 @@ &pp3300_dx_edp { gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; }; =20 +&usb_a0_hs { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + +&usb_a0_ss { + remote-endpoint =3D <&usb_hub_dfp3_ss>; +}; + +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp1_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp1_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_hub_2_x { + camera@4 { + compatible =3D "usb5c8,b03"; + reg =3D <4>; + }; +}; + +&usb_hub_dfp1_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp1_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&usb_a0_hs>; +}; + +&usb_hub_dfp3_ss { + remote-endpoint =3D <&usb_a0_ss>; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ =20 &en_pp3300_dx_edp { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 43b2583f0f26..88ffa2331cd2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -180,10 +180,54 @@ &sound { dmic-gpios =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; }; =20 +&usb_a0_hs { + remote-endpoint =3D <&usb_hub_dfp4_hs>; +}; + +&usb_a0_ss { + remote-endpoint =3D <&usb_hub_dfp4_ss>; +}; + +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp3_ss>; +}; + &usb_c1 { status =3D "disabled"; }; =20 +&usb_hub_2_x { + camera@1 { + compatible =3D "usb4f2,b718"; + reg =3D <1>; + }; + + camera@2 { + compatible =3D "usb13d3,56e9"; + reg =3D <2>; + }; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp3_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp4_hs { + remote-endpoint =3D <&usb_a0_hs>; +}; + +&usb_hub_dfp4_ss { + remote-endpoint =3D <&usb_a0_ss>; +}; + &wifi { qcom,ath10k-calibration-variant =3D "GO_POMPOM"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 00229b1515e6..d0d9871b74cb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -104,6 +104,17 @@ &sdhc_2 { status =3D "okay"; }; =20 +&pogo_pins { + keyboard@1 { + compatible =3D "usb18d1,505b"; + reg =3D <1>; + }; +}; + +&pogo_pins_in { + remote-endpoint =3D <&usb_hub_dfp1_hs>; +}; + &pp1800_uf_cam { status =3D "okay"; }; @@ -128,11 +139,31 @@ pp3300_disp_on: &pp3300_dx_edp { gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; }; =20 +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + /* This board only has 1 USB Type-C port. */ &usb_c1 { status =3D "disabled"; }; =20 +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp1_hs { + remote-endpoint =3D <&pogo_pins_in>; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ =20 /* diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arc= h/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 1d9fc61b6550..409d332fbc13 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -180,6 +180,17 @@ skin-temp-thermistor@1 { }; }; =20 +&pogo_pins { + keyboard@3 { + compatible =3D "usb18d1,5057"; + reg =3D <3>; + }; +}; + +&pogo_pins_in { + remote-endpoint =3D <&usb_hub_dfp3_hs>; +}; + &pp1800_uf_cam { status =3D "okay"; }; @@ -196,6 +207,42 @@ &pp2800_wf_cam { status =3D "okay"; }; =20 +&usb_c0_hs { + remote-endpoint =3D <&usb_hub_dfp2_hs>; +}; + +&usb_c0_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp2_ss>; +}; + +&usb_c1_hs { + remote-endpoint =3D <&usb_hub_dfp4_hs>; +}; + +&usb_c1_ss_rxtx { + remote-endpoint =3D <&usb_hub_dfp3_ss>; +}; + +&usb_hub_dfp2_hs { + remote-endpoint =3D <&usb_c0_hs>; +}; + +&usb_hub_dfp2_ss { + remote-endpoint =3D <&usb_c0_ss_rxtx>; +}; + +&usb_hub_dfp4_hs { + remote-endpoint =3D <&usb_c1_hs>; +}; + +&usb_hub_dfp3_ss { + remote-endpoint =3D <&usb_c1_ss_rxtx>; +}; + +&usb_hub_dfp3_hs { + remote-endpoint =3D <&pogo_pins_in>; +}; + &wifi { qcom,ath10k-calibration-variant =3D "GO_WORMDINGLER"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index 46aaeba28604..ee08a4ecade9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -650,6 +650,12 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 + cros_ec_gpio: gpio { + compatible =3D "google,cros-ec-gpio"; + #gpio-cells =3D <2>; + gpio-controller; + }; + cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; @@ -662,6 +668,65 @@ i2c_tunnel: i2c-tunnel { #size-cells =3D <0>; }; =20 + typec-switch { + compatible =3D "google,cros-ec-typec-switch"; + no-hpd; + mode-switch; + mux-gpios =3D <&cros_ec_gpio 42 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp_ml0_ml1: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mdss_dp_out>; + data-lanes =3D <0 1>; + }; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_c0_ss_rxtx: endpoint@0 { + reg =3D <0>; + /* Endpoint filled in by board */ + }; + + usb_c1_ss_rxtx: endpoint@1 { + reg =3D <1>; + /* Endpoint filled in by board */ + }; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cros_typec_c0_ss: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_c0_ss>; + data-lanes =3D <0 1 2 3>; + }; + + cros_typec_c1_ss: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&usb_c1_ss>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + }; + typec { compatible =3D "google,cros-ec-typec"; #address-cells =3D <1>; @@ -674,6 +739,25 @@ usb_c0: connector@0 { power-role =3D "dual"; data-role =3D "host"; try-power-role =3D "source"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_c0_hs: endpoint { + /* Endpoint filled in by board */ + }; + }; + + port@1 { + reg =3D <1>; + usb_c0_ss: endpoint { + remote-endpoint =3D <&cros_typec_c0_ss>; + }; + }; + }; }; =20 usb_c1: connector@1 { @@ -683,6 +767,25 @@ usb_c1: connector@1 { power-role =3D "dual"; data-role =3D "host"; try-power-role =3D "source"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_c1_hs: endpoint { + /* Endpoint filled in by board */ + }; + }; + + port@1 { + reg =3D <1>; + usb_c1_ss: endpoint { + remote-endpoint =3D <&cros_typec_c1_ss>; + }; + }; + }; }; }; }; @@ -794,6 +897,7 @@ &mdss_dp { &mdss_dp_out { data-lanes =3D <0 1>; link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint =3D <&dp_ml0_ml1>; }; =20 &mdss_dsi0 { @@ -965,6 +1069,41 @@ usb_hub_2_x: hub@1 { reg =3D <1>; vdd-supply =3D <&pp3300_hub>; peer-hub =3D <&usb_hub_3_x>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_hub_2_x_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + usb_hub_dfp1_hs: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + port@2 { + reg =3D <2>; + usb_hub_dfp2_hs: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + + port@3 { + reg =3D <3>; + usb_hub_dfp3_hs: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + + port@4 { + reg =3D <4>; + usb_hub_dfp4_hs: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + }; }; =20 /* 3.x hub on port 2 */ @@ -973,6 +1112,42 @@ usb_hub_3_x: hub@2 { reg =3D <2>; vdd-supply =3D <&pp3300_hub>; peer-hub =3D <&usb_hub_2_x>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_hub_3_x_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + usb_hub_dfp1_ss: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + + port@2 { + reg =3D <2>; + usb_hub_dfp2_ss: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + + port@3 { + reg =3D <3>; + usb_hub_dfp3_ss: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + + port@4 { + reg =3D <4>; + usb_hub_dfp4_ss: endpoint { + /* Remote endpoint filled in by board */ + }; + }; + }; }; }; =20 --=20 https://chromeos.dev