From nobody Tue Feb 10 05:10:20 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D51A58288F; Fri, 9 Feb 2024 18:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707502719; cv=none; b=pH8MWyx/pqd1rNwaYeO/8jL6g7PjMnSVOFi+8R9G/7USeKsCTZBvTF25YaiEwjO9+LVLD4aRIYN8yAwOivj6rva5t+Zl8KUue/fZWdON4pF2JoNRwKaKm+Van2VRo88sWzjylS33dAPBfz965g2vCyX2Fq9eBRw8r5mjQF/9Sys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707502719; c=relaxed/simple; bh=NhEJU4fPbw7evyuXsafxiqtsg7ouIz0AOGaTUJeDeEY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BnYWdNDo5w5sTdOh3fLvBOzhNqXKj3t+QMQq+CHQQmZXDflnhkhfpu41bm9lsTj46koXE2uwKv382lWoieHXECjoL8N+r/MIEcae07JRYI/GN67TU5eTBTFNfLGbR4bZ8B/tHsvJAGv2zo1R97kGwwv7eOjGiQtKAky71kh9pko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ZOF8EMNs; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ZOF8EMNs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1707502713; bh=NhEJU4fPbw7evyuXsafxiqtsg7ouIz0AOGaTUJeDeEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZOF8EMNsCyA0ZeBtf5aRGjnmINmWWoe7johz+TNkiVCvCRJgQurna/b1Ym8Iygfs7 LAtr+q/xp3D7SvQt0ndjs//PsUHeYa05JDO4jMN8QxW1+9qv2XPvnerxClKVudL8C8 6rIz/TYPOhi12x0MRLlIxct8I5wk7J9qCTTf5ziCBzyONDrjnlVeKjIA6BJQiL3M4B 9DmWrVf3qyQHG/Fxy4Ba1izowcg6CvPPGgvFgVJ5hcxRbfKbNeSXfnxyPRtZChlx0q TViIuhRYRY02EB1cd9gcmLUCyNIEN/hHMM8Mo820qguA9tNddVeSURgkpZJTZc0rzE FILCrd3tAmwFQ== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 7A65437820B6; Fri, 9 Feb 2024 18:18:33 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 97F554800D4; Fri, 9 Feb 2024 19:18:32 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v1 06/10] arm64: dts: rockchip: add USBDP phys on rk3588 Date: Fri, 9 Feb 2024 19:17:22 +0100 Message-ID: <20240209181831.104687-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209181831.104687-1-sebastian.reichel@collabora.com> References: <20240209181831.104687-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add both USB3-Displayport PHYs to RK3588 SoC DT. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++ 2 files changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 5519c1430cb7..c26288ec75ce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -17,6 +17,37 @@ pipe_phy1_grf: syscon@fd5c0000 { reg =3D <0x0 0xfd5c0000 0x0 0x100>; }; =20 + usbdpphy1_grf: syscon@fd5cc000 { + compatible =3D "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg =3D <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg =3D <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy1: usb2-phy@4000 { + compatible =3D "rockchip,rk3588-usb2phy"; + reg =3D <0x4000 0x10>; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names =3D "phyclk"; + clock-output-names =3D "usb480m_phy1"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy1_otg: otg-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + }; + i2s8_8ch: i2s@fddc8000 { compatible =3D "rockchip,rk3588-i2s-tdm"; reg =3D <0x0 0xfddc8000 0x0 0x1000>; @@ -310,6 +341,37 @@ sata-port@0 { }; }; =20 + usbdp_phy1: phy@fed90000 { + compatible =3D "rockchip,rk3588-usbdp-phy"; + reg =3D <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf =3D <&usb2phy1_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy1_grf>; + rockchip,vo-grf =3D <&vo0_grf>; + clocks =3D <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status =3D "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + usbdp_phy1_u3: usb3-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + combphy1_ps: phy@fee10000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 36b1b7acfe6a..553e1883cfe4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -536,6 +536,37 @@ pipe_phy2_grf: syscon@fd5c4000 { reg =3D <0x0 0xfd5c4000 0x0 0x100>; }; =20 + usbdpphy0_grf: syscon@fd5c8000 { + compatible =3D "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg =3D <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg =3D <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy0: usb2-phy@0 { + compatible =3D "rockchip,rk3588-usb2phy"; + reg =3D <0x0 0x10>; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names =3D "phyclk"; + clock-output-names =3D "usb480m_phy0"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy0_otg: otg-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg =3D <0x0 0xfd5d8000 0x0 0x4000>; @@ -561,6 +592,17 @@ u2phy2_host: host-port { }; }; =20 + vo0_grf: syscon@fd5a6000 { + compatible =3D "rockchip,rk3588-vo-grf", "syscon"; + reg =3D <0x0 0xfd5a6000 0x0 0x2000>; + clocks =3D <&cru PCLK_VO0GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible =3D "rockchip,rk3588-usb-grf", "syscon"; + reg =3D <0x0 0xfd5ac000 0x0 0x4000>; + }; + usb2phy3_grf: syscon@fd5dc000 { compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg =3D <0x0 0xfd5dc000 0x0 0x4000>; @@ -2360,6 +2402,37 @@ dmac2: dma-controller@fed10000 { #dma-cells =3D <1>; }; =20 + usbdp_phy0: phy@fed80000 { + compatible =3D "rockchip,rk3588-usbdp-phy"; + reg =3D <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf =3D <&usb2phy0_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy0_grf>; + rockchip,vo-grf =3D <&vo0_grf>; + clocks =3D <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status =3D "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + usbdp_phy0_u3: usb3-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + combphy0_ps: phy@fee00000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee00000 0x0 0x100>; --=20 2.43.0