From nobody Sat Feb 7 21:15:21 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19496D1CB; Fri, 9 Feb 2024 15:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491336; cv=none; b=YPQobm2WQD95zVsvyJyaw21EQcyzg9CB1ZM+vM6DbP23hdx/o5Qn43HHsuUq3zz4musutwbWJsbF+6hEIlG2pEo6DhZ6WBzvGsTBoXKukloHcErJGS++fdpi2Li0JMKXHSQkdOv9f5FAmCJ+UqU/B8Ce5s7CzjdlctRPJHctgRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491336; c=relaxed/simple; bh=mn0xWgi/6UQLUMoJ5s/lxkh6G+bbnSgewb4JFdRi4Ec=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ef6JMRFKX/q4vz43DHAzIHt9eYA4ZrKIqmCgja4YnO9SvVlUfm6Pt6so3XGVCKNmbMVDgF9lW75LlCKvZrT1kp42rTbHyO42MlBonLu0rN5rk4AhiYVI9dFwaMMHstqHFc4mHeGpwSNu31BrYKUgaLYB5hFFNrkHOL/ca65iXiE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=DXyJXkFn; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DXyJXkFn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1707491334; x=1739027334; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mn0xWgi/6UQLUMoJ5s/lxkh6G+bbnSgewb4JFdRi4Ec=; b=DXyJXkFn1N0nkE8RQSLBrOxuVjEn6aIzS4/qwRIqTMuAnKcgAIG2/lOP 6/hhHCmSv5tC9HIATevznMKXM1GGmYFO2iDRRiLkxU0xtX8vUQPNh6pO7 GnF7suYCzSGmKoClMCRZHAn/DoCRudRV3YQvOZpTZUvyMXCi4MKExyK3b 4jQQoNK2Kgo60yxx6OUiz5iluDrtdUsYcMl0NJ5ycd6AYdgDOGNRMEfdc mq02UvS8GVXZ8XC9kqIJ3LXXNDSZo5m3JMPn6UO6SxODLo6fp4PMFMABd svin/0GKyGaA0D9AQnGOShQHbuimNeN7b4P5Su/b9n8mYGz2exp2+VadV A==; X-CSE-ConnectionGUID: mfk2QRC8TEy2GEu9hHFtmA== X-CSE-MsgGUID: cTinoXJuRiu/M5E1R7jgSQ== X-IronPort-AV: E=Sophos;i="6.05,257,1701154800"; d="scan'208";a="16538527" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Feb 2024 08:08:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 9 Feb 2024 08:08:25 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:12 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Rob Herring Subject: [PATCH v4 1/4] dt-bindings: display: bridge: add sam9x75-lvds binding Date: Fri, 9 Feb 2024 20:37:54 +0530 Message-ID: <20240209150757.66914-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on some Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by: Dharma Balasubiramani Reviewed-by: Rob Herring --- Changelog v3 -> v4 - Rephrase the commit subject. v2 -> v3 - No changes. v1 -> v2 - Remove '|' in description, as there is no formatting to preserve. - Remove 'gclk' from clock-names as there is only one clock(pclk). - Remove the unused headers and include only used ones. - Change the compatible name specific to SoC (sam9x75) instead of entire se= ries. - Change file name to match the compatible name. --- .../bridge/microchip,sam9x75-lvds.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microc= hip,sam9x75-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam= 9x75-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip= ,sam9x75-lvds.yaml new file mode 100644 index 000000000000..862ef441ac9f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lv= ds.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X75 LVDS Controller + +maintainers: + - Dharma Balasubiramani + +description: + The Low Voltage Differential Signaling Controller (LVDSC) manages data + format conversion from the LCD Controller internal DPI bus to OpenLDI + LVDS output signals. LVDSC functions include bit mapping, balanced mode + management, and serializer. + +properties: + compatible: + const: microchip,sam9x75-lvds + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + + clock-names: + items: + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + lvds-controller@f8060000 { + compatible =3D "microchip,sam9x75-lvds"; + reg =3D <0xf8060000 0x100>; + interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names =3D "pclk"; + }; --=20 2.25.1 From nobody Sat Feb 7 21:15:22 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A39946A00B; Fri, 9 Feb 2024 15:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491324; cv=none; b=EtDSFBgcZuVIsyuzUYwY4Fb8T6AClRrSaw6WYO7l/HuwyNx4bUgdDiOWXrX5Rq9JXviTE4M3OQJ+dpWU/8Rhy3dcVUK6QusbpvmZa5WrxkjsUySrdXT3IatCc0QFEVIZwbX+EMbQ7Zlgqef77oMSci1gQddOy8sYNyLUPF4ZUH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491324; c=relaxed/simple; bh=+WdTbJtndChJa5h/hbvdTUzYQT/r/rhk5D4eo+1EJjQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GWYaAZYChWJ1VIeRXfvCj3nz4ECXOUG9vVWlCLa/eAQLOG4mYMM+RqDlO95+62jMf/M0TeLSOgc0LT1XwXUHhbtYqUiqedbw4if6uOar6UxDbCK/MD59NqAisz9wucUfZ9VHTl4sRSmNz58/O5EJJAoLbyNamYrI57urVs6w4cQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ku2iSXtK; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ku2iSXtK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1707491323; x=1739027323; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=+WdTbJtndChJa5h/hbvdTUzYQT/r/rhk5D4eo+1EJjQ=; b=ku2iSXtK/1XL01l+mI4dZ11A24iNpkrW1acefaScAGHviZlrQU/iP8so AweVkUxjeFwCZt0qEzg26PsAYk7U0cjZbehD8Lei+7Ng5qledYa6ob4QU OqDum+L9j+EZES429ETpy+dFNE6EMhwihUmhGgrR4AzegyfrJLq6s0fEv SLGDsIOx0M4XIJ5D8yBK7nmEDit1myqWi24WAXzrthZz4byjRqYb5eXI4 r98cHdr5EVyRYoSL3yyHVyCDjO+b6vm3pvQuRAnpF+HHNgccmH545iXKe 8vzrrZcmQlieIXorjWASlV7ZqX5rijlTNCPt0lVj5c69ncTjJdnAJffFw g==; X-CSE-ConnectionGUID: KIIHkk3fQjqBsya5fSn4qQ== X-CSE-MsgGUID: ew0NFIJwTY2lZdpqcCi2mA== X-IronPort-AV: E=Sophos;i="6.05,257,1701154800"; d="scan'208";a="16014542" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Feb 2024 08:08:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 9 Feb 2024 08:08:37 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:25 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 2/4] drm/bridge: add lvds controller support for sam9x7 Date: Fri, 9 Feb 2024 20:37:55 +0530 Message-ID: <20240209150757.66914-3-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new LVDS controller driver for sam9x7 which does the following: - Prepares and enables the LVDS Peripheral clock - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself to the global bridge list. - Identifies its output endpoint as panel and adds it to the encoder display pipeline - Enables the LVDS serializer Signed-off-by: Manikandan Muralidharan Signed-off-by: Dharma Balasubiramani --- Changelog v3 -> v4 - No changes. v2 ->v3 - Correct Typo error "serializer". - Consolidate get() and prepare() functions and use devm_clk_get_prepared(). - Remove unused variable 'ret' in probe(). - Use devm_pm_runtime_enable() and drop the mchp_lvds_remove(). v1 -> v2 - Drop 'res' variable and combine two lines into one. - Handle deferred probe properly, use dev_err_probe(). - Don't print anything on deferred probe. Dropped print. - Remove the MODULE_ALIAS and add MODULE_DEVICE_TABLE(). - symbol 'mchp_lvds_driver' was not declared. It should be static. --- drivers/gpu/drm/bridge/Kconfig | 7 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e6a4e2044c0..74ca0edb4e0d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -173,6 +173,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. =20 +config DRM_MICROCHIP_LVDS_SERIALIZER + tristate "Microchip LVDS serializer support" + depends on OF + depends on DRM_ATMEL_HLCDC + help + Support for Microchip's LVDS serializer. + config DRM_NWL_MIPI_DSI tristate "Northwest Logic MIPI DSI Host controller" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 2b892b7ed59e..e3804e93d324 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) +=3D lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) +=3D lontium-lt9611uxc.o obj-$(CONFIG_DRM_LVDS_CODEC) +=3D lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) +=3D megachips-stdpxxxx-= ge-b850v3-fw.o +obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) +=3D microchip-lvds.o obj-$(CONFIG_DRM_NXP_PTN3460) +=3D nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) +=3D parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8640) +=3D parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c new file mode 100644 index 000000000000..d3fd9d722e36 --- /dev/null +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + * Author: Dharma Balasubiramani + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define LVDS_POLL_TIMEOUT_MS 1000 + +/* LVDSC register offsets */ +#define LVDSC_CR 0x00 +#define LVDSC_CFGR 0x04 +#define LVDSC_SR 0x0C +#define LVDSC_WPMR 0xE4 + +/* Bitfields in LVDSC_CR (Control Register) */ +#define LVDSC_CR_SER_EN BIT(0) + +/* Bitfields in LVDSC_CFGR (Configuration Register) */ +#define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_DEN_POL_HIGH 0 +#define LVDSC_CFGR_DC_UNBALANCED 0 +#define LVDSC_CFGR_MAPPING_JEIDA BIT(6) + +/*Bitfields in LVDSC_SR */ +#define LVDSC_SR_CS BIT(0) + +/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */ +#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8) +#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644 + +struct mchp_lvds { + struct device *dev; + void __iomem *regs; + struct clk *pclk; + int format; /* vesa or jeida format */ + struct drm_panel *panel; + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; +}; + +static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) +{ + return container_of(bridge, struct mchp_lvds, bridge); +} + +static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) +{ + return readl_relaxed(lvds->regs + offset); +} + +static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) +{ + writel_relaxed(val, lvds->regs + offset); +} + +static void lvds_serialiser_on(struct mchp_lvds *lvds) +{ + unsigned long timeout =3D jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS= ); + + /* The LVDSC registers can only be written if WPEN is cleared */ + lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & + LVDSC_WPMR_WPKEY_MASK)); + + /* Wait for the status of configuration registers to be changed */ + while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { + if (time_after(jiffies, timeout)) { + dev_err(lvds->dev, "%s: timeout error\n", __func__); + return; + } + usleep_range(1000, 2000); + } + + /* Configure the LVDSC */ + lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | + LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | + LVDSC_CFGR_PIXSIZE_24BITS)); + + /* Enable the LVDS serializer */ + lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); +} + +static int mchp_lvds_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + + bridge->encoder->encoder_type =3D DRM_MODE_ENCODER_LVDS; + + return drm_bridge_attach(bridge->encoder, lvds->panel_bridge, + bridge, flags); +} + +static void mchp_lvds_enable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + int ret; + + ret =3D clk_enable(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return; + } + + ret =3D pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); + return; + } + + lvds_serialiser_on(lvds); +} + +static void mchp_lvds_disable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + + pm_runtime_put(lvds->dev); + clk_disable(lvds->pclk); +} + +static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { + .attach =3D mchp_lvds_attach, + .enable =3D mchp_lvds_enable, + .disable =3D mchp_lvds_disable, +}; + +static int mchp_lvds_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mchp_lvds *lvds; + struct device_node *port; + + if (!dev->of_node) + return -ENODEV; + + lvds =3D devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); + if (!lvds) + return -ENOMEM; + + lvds->dev =3D dev; + + lvds->regs =3D devm_ioremap_resource(lvds->dev, + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + if (IS_ERR(lvds->regs)) + return PTR_ERR(lvds->regs); + + lvds->pclk =3D devm_clk_get_prepared(lvds->dev, "pclk"); + if (IS_ERR(lvds->pclk)) + return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk), + "could not get pclk_lvds prepared\n"); + + port =3D of_graph_get_remote_node(dev->of_node, 1, 0); + if (!port) { + DRM_DEV_ERROR(dev, + "can't find port point, please init lvds panel port!\n"); + return -EINVAL; + } + + lvds->panel =3D of_drm_find_panel(port); + of_node_put(port); + + if (IS_ERR(lvds->panel)) + return -EPROBE_DEFER; + + lvds->panel_bridge =3D devm_drm_panel_bridge_add(dev, lvds->panel); + + if (IS_ERR(lvds->panel_bridge)) + return PTR_ERR(lvds->panel_bridge); + + lvds->bridge.of_node =3D dev->of_node; + lvds->bridge.type =3D DRM_MODE_CONNECTOR_LVDS; + lvds->bridge.funcs =3D &mchp_lvds_bridge_funcs; + + dev_set_drvdata(dev, lvds); + devm_pm_runtime_enable(dev); + + drm_bridge_add(&lvds->bridge); + + return 0; +} + +static const struct of_device_id mchp_lvds_dt_ids[] =3D { + { + .compatible =3D "microchip,sam9x75-lvds", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mchp_lvds_dt_ids); + +static struct platform_driver mchp_lvds_driver =3D { + .probe =3D mchp_lvds_probe, + .driver =3D { + .name =3D "microchip-lvds", + .of_match_table =3D mchp_lvds_dt_ids, + }, +}; +module_platform_driver(mchp_lvds_driver); + +MODULE_AUTHOR("Manikandan Muralidharan "); +MODULE_AUTHOR("Dharma Balasubiramani "); +MODULE_DESCRIPTION("Low Voltage Differential Signaling Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Sat Feb 7 21:15:22 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FAB2364D6; Fri, 9 Feb 2024 15:09:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491369; cv=none; b=jeHyWo/Aaj469Ye9epYTmqzijTjmFuabsznbiLWXlUN/P/A6M2SvJauV9mfd7v4I50he+IVHtvR4k3igfcELG5R38pnOI1yR8uSpO9i9dKmy3hYMpRkIwtgF13ocB6wgqrjFqoMeslWNwd97AwIbC7qkNMjulRSXMvBgYJWw90o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491369; c=relaxed/simple; bh=dWx046Tkcu2y3E2CdwqYqH3QkLRo4gCPm3p/Aq7/rvY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=d9vpfo+YUAmLZDD5tNXAoOK6Kx7iQL0y0/RXbVhAfAn+VNNSLYl7MPhZNOUspe66g0aNW0aPxpTtEp2RYkKg0BbD3Evjpd0fKgAifEzhFurg4LcMUTSI3kjYWlSbJYvgi1blwXWAvFhuvQ4V5PcCU3RQ0fNIhmT7hJNaXuKbIHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=yM82d/pG; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="yM82d/pG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1707491366; x=1739027366; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=dWx046Tkcu2y3E2CdwqYqH3QkLRo4gCPm3p/Aq7/rvY=; b=yM82d/pG7B5It+OgyttNQb57obDLC5J7YDbjqPraffz/7/6royQoBqnO FF25EMl/+Q7KHNzeC9csPhhPbyACYsCKbNc7w7hEd9Cr2wFb9iCBsn+Jr XP21D47QwGVzXlgwPlLvp68MKFJpWyeB1PLTOjjr0mLviogbVPBphJJMY nmo9BlrFPdm4TOk/sPP1e1RNezu+5mM2F25vYbkk3knkj51vvEGSjj4Dc k4vfBwkWkUawo0dQhwvltAnEF6abIR1soTFIxfGF+Yj3ze7x4Q5uj6RX5 oiJi5Jnxwa3oaSh4LhuSgNwDwYJqjR+WP9M88BC+I/rcn4a4ogGC9Fqqa g==; X-CSE-ConnectionGUID: /ftgHdBDRUKkBO7najs1cw== X-CSE-MsgGUID: VSn3vkQASAS92qqfg+3cTQ== X-IronPort-AV: E=Sophos;i="6.05,257,1701154800"; d="scan'208";a="17424562" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Feb 2024 08:09:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 9 Feb 2024 08:08:49 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:37 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 3/4] MAINTAINERS: add SAM9X7 SoC's LVDS controller Date: Fri, 9 Feb 2024 20:37:56 +0530 Message-ID: <20240209150757.66914-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by: Dharma Balasubiramani Reviewed-by: Neil Armstrong Acked-by: Nicolas Ferre --- Changelog v3 ->v4 - No changes. v2 -> v3 - Move the entry before "MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER". v1 -> v2 - No Changes. --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7c4cf8201e0..ce592b6cf375 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14216,6 +14216,14 @@ S: Supported F: Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml F: drivers/pwm/pwm-atmel.c =20 +MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER +M: Manikandan Muralidharan +M: Dharma Balasubiramani +L: dri-devel@lists.freedesktop.org +S: Supported +F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.= yaml +F: drivers/gpu/drm/bridge/microchip-lvds.c + MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER M: Eugen Hristev L: linux-iio@vger.kernel.org --=20 2.25.1 From nobody Sat Feb 7 21:15:22 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CF5B69958; Fri, 9 Feb 2024 15:09:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491368; cv=none; b=kph1ocEV9P9QNWLsjZMuZ+fFhnymLGu7LRvDYvDVU95dGXmX5mGfRY6kK2r5qeIRdJthQYDzIm3g2aV4Uc3ig52RxC5dqjJ/IlEjbbyDDTzWfaUtpPHkEqakIk1E8aqe8FsTMkzWkS3wLFk42viZ65TFeBXfdg/gie62h+v7QaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707491368; c=relaxed/simple; bh=PM51gHeCFEK5iONhCM2ibXVO8eHJ0sHQL+dlsYPqUVM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hqjsQaH68Va+4ISuciBNQNbH7JkSjR3RSYsMXS39ZLvNI91H9VxBTWXfXS06n1LCqP3/DJpdaxTrbtX92Rlk6l2tMX9XxOEbJ0yyQRP6fuVk3sxEpKTI9TZcQ/9odp380iKXSPoclR4sLvsDwQcVj+c9rEJH/vrbrEFpEGiLzdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=W00OKl0h; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="W00OKl0h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1707491366; x=1739027366; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=PM51gHeCFEK5iONhCM2ibXVO8eHJ0sHQL+dlsYPqUVM=; b=W00OKl0hiof77ncQqc2L04np3bJ1h2hjEqvEFIkxJIa//pabSLSeofZ7 hSNzFcf3G+lCg8h91eBINpkkzcJGKuFpuBlasFXBUhj7SMchRQ+hKi8Gk MIaLTutFq8CcgkTjLY1JNzb27jb8CPMEXe+xeoHcLEk3b8a0gADysKu8n U5yD1S1v3wU66UxC7ajGroywjxvDcJcA47cwwbrqUHBhvvuRMiM2IjJQA eQcT3t0ZHpkOlnoQ2nmDNOCXHqr69yLok4MFUWFgqWNnYF9eBeK/K53h/ UT3ZOJ/9kjSYuIWKTu8x2iift84fJEr/JJx5rQ3nFK3sLfaWY+YVgdpm3 A==; X-CSE-ConnectionGUID: /ftgHdBDRUKkBO7najs1cw== X-CSE-MsgGUID: bbYucXZHQiexd9EbIAja6g== X-IronPort-AV: E=Sophos;i="6.05,257,1701154800"; d="scan'208";a="17424564" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Feb 2024 08:09:25 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 9 Feb 2024 08:09:01 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:49 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 4/4] ARM: configs: at91: Enable LVDS serializer support Date: Fri, 9 Feb 2024 20:37:57 +0530 Message-ID: <20240209150757.66914-5-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable LVDS serializer support for display pipeline. Signed-off-by: Dharma Balasubiramani Acked-by: Hari Prasath Gujulan Elango Acked-by: Nicolas Ferre --- Changelog v3 -> v4 - No Changes. v2 -> v3 - No Changes. --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 71b5acc78187..6a7714beb099 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -143,6 +143,7 @@ CONFIG_VIDEO_OV2640=3Dm CONFIG_VIDEO_OV7740=3Dm CONFIG_DRM=3Dy CONFIG_DRM_ATMEL_HLCDC=3Dy +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=3Dy CONFIG_DRM_PANEL_SIMPLE=3Dy CONFIG_DRM_PANEL_EDP=3Dy CONFIG_FB_ATMEL=3Dy --=20 2.25.1