From nobody Sat Feb 7 15:22:09 2026 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04DE7374C6 for ; Fri, 9 Feb 2024 12:51:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707483102; cv=none; b=kwy97F4zfTX2Bkd/MWMnh1t8ugp5ygISyJMvsuwyRw/GaQ17yW1CitqX6dUTeGXJlIe0rN84z7qefy/xdgKpJQ4FfbRxoV2edE1uw/FLpJH5oNQLHVvVdDb2IdqoCO/lK+Tew4/1YxV1AU2u+9qRnYeIwBoBorhK04mc9xRWrjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707483102; c=relaxed/simple; bh=KY7GS4ZatUP/HU9tFlS/Oxj4tOpPTr7mIbh5hd6OGyo=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=rjln+GV31REUS2+sxw243gTw+/PLZZtOFwL+hHcpFCtuNTpbwSilUtSuzoVvLIVBlNqsQTAArafCayJ4hpwciVQETQFjGyF3EPvvz1I/j9l6qffm1xyNeE923O94ZjH/YwvZThTADLhkZNNuHbx0k1jBt9OaXl3DG+VWi2IhfkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--ericchancf.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=cduXupIC; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--ericchancf.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="cduXupIC" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-dc6dbdcfd39so1781392276.2 for ; Fri, 09 Feb 2024 04:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707483100; x=1708087900; darn=vger.kernel.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=k0mIF1IZyHiAXR1QozG/XlWcQLhCvpdfF1T0p9TCdYE=; b=cduXupICaN/6PCExGwsBuylkiGisiMmFxgSUd/xOVmfDa6r6Cwgcg+UZpcurECZO0j E2WWyfnaV5Kld2PsJTirMX1xFsZlMsBgCB+d17LeyiPujIIpB7jylf+pkpRHoUr9CRvc k1tSSNnWEPwTAYa/J/riRtvDuV8FNp29BOWsrbcRWrsXG4qyoIwkJ6QNjqA8GIywhBiY o8/iN7GgvE1BQh4dkHT31Tf+LeEsue1/5YuVIFM7PIhCvF5jYpGSVuHIkynPL3ZDV13L +KAgBkh9PyorsUnQY2BVmeSCu7lK0AfSZ908elajj7EkRWVBKHbWIxuiA+ktZtGaB6LU 2n4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707483100; x=1708087900; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=k0mIF1IZyHiAXR1QozG/XlWcQLhCvpdfF1T0p9TCdYE=; b=HpVnD/gXZOpE6NwyGYAGeDLBXM4eQcQbnH5uMapwa1wbRiYl7Oip7pz0ilUxs0SfxG rlKAIgBVxPGa3WVMpXkbARoIIDGxHHeEy7+YiplsIIhuzEKzt+ewkqYiyJrKpYyAe1/U jERGLkddfbeKIDN/agZriXSzigkQgYrKpyYVZPOLHdHXaQpjkmbB9UOgEbzsPHw5x3lu eqYTAvUqFAOOuPClIm/z3auJgv4dDfmwWXgE6ICENbOjx8y7buguWQXJ0AZnsvbA23FM QiTG+gx86NZtNTuEDUv36R6o+tLGiuw2Hh1GttM6vY8y9geZvxKull3J7J9V0W/t429J 7FZA== X-Gm-Message-State: AOJu0YyQkmxERAczPMk2Bkc81H+lcimrmmQOw4nkiAvVI/gPI9M1b5yQ Pedj4pAUwB7Swcg/jBqcc/1QFg08xxkNxLTGhuZ8yhtIuB/MxcixDLLeVbFnCb9Mndti2HHkDu+ QB5u4Ok3v4LSLWqM2Ng== X-Google-Smtp-Source: AGHT+IFTVTfekngAHQxuJCo+qerwumtA+dN8zAP79e4o0CDw8JI2RcaUY8bNHoFwPZ7RcNu8Eb2B3joWzc+x7zVt X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1022:b0:dc2:550b:a4f4 with SMTP id x2-20020a056902102200b00dc2550ba4f4mr317038ybt.1.1707483099951; Fri, 09 Feb 2024 04:51:39 -0800 (PST) Date: Fri, 9 Feb 2024 12:50:48 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240209125048.4078639-1-ericchancf@google.com> Subject: [PATCH] riscv/fence: Consolidate fence definitions and define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Disparate fence implementations are consolidated into fence.h. Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. A first consequence is that __{mb,rmb,wmb} map to a compiler barrier on !SMP (while their definition remains unchanged on SMP). Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, The fence instruction can be eliminated When SMP is not in use. Also clean up the warning with scripts/checkpatch.pl. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 24 ++++++++++-------------- arch/riscv/include/asm/barrier.h | 21 ++++++++++----------- arch/riscv/include/asm/cmpxchg.h | 5 ++--- arch/riscv/include/asm/fence.h | 11 +++++++++-- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 39 insertions(+), 37 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomi= c.h index f5dfef6c2153..19050d13b6c1 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,13 +17,9 @@ #endif =20 #include -#include =20 -#define __atomic_acquire_fence() \ - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") - -#define __atomic_release_fence() \ - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); +#define __atomic_acquire_fence() RISCV_FENCE(r, rw) +#define __atomic_release_fence() RISCV_FENCE(rw, r) =20 static __always_inline int arch_atomic_read(const atomic_t *v) { @@ -207,7 +203,7 @@ static __always_inline int arch_atomic_fetch_add_unless= (atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +224,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unle= ss(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +244,7 @@ static __always_inline bool arch_atomic_inc_unless_nega= tive(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +264,7 @@ static __always_inline bool arch_atomic_dec_unless_posi= tive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +284,7 @@ static __always_inline int arch_atomic_dec_if_positive(= atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +306,7 @@ static __always_inline bool arch_atomic64_inc_unless_ne= gative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +327,7 @@ static __always_inline bool arch_atomic64_dec_unless_po= sitive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +348,7 @@ static __always_inline s64 arch_atomic64_dec_if_positiv= e(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barr= ier.h index 110752594228..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,28 +11,27 @@ #define _ASM_RISCV_BARRIER_H =20 #ifndef __ASSEMBLY__ +#include =20 #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) =20 -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") =20 /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) =20 /* These barriers do not need to enforce ordering on devices, just memory.= */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) =20 #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) =20 @@ -40,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 =3D READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) =20 @@ -69,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessar= y on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) =20 #include =20 diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 2f4726d3cfcc..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ =20 #include =20 -#include #include =20 #define __xchg_relaxed(ptr, new, size) \ @@ -313,7 +312,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +324,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..3e6ba47cf61a 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,12 +1,19 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H =20 +#define RISCV_FENCE_ASM(p, s) \ + "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + (__asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory")) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, w) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif =20 #endif /* _ASM_RISCV_FENCE_H */ diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) =20 /* * Accesses from a single hart to a single I/O address must be ordered. T= his diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H =20 #include +#include #include =20 /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iom= em *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); = }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() =20 #define readb(c) ({ u8 __v; __io_br(); __v =3D readb_cpu(c); __io_ar(__v)= ; __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiow= b.h index 0b2333e71fdc..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have comple= ted * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o, w) =20 #include #include --=20 2.43.0.687.g38aa6559b0-goog