From nobody Sat Feb 7 23:11:05 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9A776BB57; Thu, 8 Feb 2024 08:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381818; cv=none; b=lK0XzisAzCE1gBBJjJZ/pd9S7QuPBqDbCAWlKnarM9K+nhKKryt4qoCrNZs4mcTdGVKUQavHdgzAta7MvHT/hE2R9YaHncj3BnhJHdkNuGJMky5bObn51PsRPDoV+ii6ax8K/PernOhY/uuEgc+HSDE5ElVVuopyiAr8UYWx+0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381818; c=relaxed/simple; bh=jRCTiqMoOM2vBas9oi0LctCdNgqdqnnIfm+t3mOLsPQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FkkJC7Yw6lzpSA2YmO9dcfrrpQ/qQod0Jf6ofEi+Ia77p2qPdT4ETFXWSvVVKFqM/fDYim5ZZ/cFiHDvndPDXiH+ntbr+7x5pSJRMpwc+sDDjAsMkM5lGXmi2YK4p/Z4g6WGfEMae9ug+0XzmScjZz25e2/K/6cy17f+nZjPEb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=GghG1HcG; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GghG1HcG" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188h4pT020564; Thu, 8 Feb 2024 02:43:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381784; bh=MBTaZvVU6myFQ58971FQ6KtPWCe15bi6ZmCInBGSJjs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GghG1HcGBnyc1FcmzLuqM5w/qgZtjHPiX82fNo6FI1xK0sinvJlC7GyV3SHyhMVJi VfYgL/JD+J642RuCa0by2tl2D4QdCo2Ck2DNlp2Ns4qzC6IRtQmOLagfBZga3XvTf9 Xyk0tbB5fC2Vnoyr9XBgB/tDmqvkCUM8NFk+X2GE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188h4SY031265 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:04 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:03 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:03 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshL097884; Thu, 8 Feb 2024 02:42:59 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:46 +0530 Message-ID: <20240208084254.295289-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 361365bb5523..5631735c9b7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MC= ASP2_AXR1.I2C3_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status =3D "okay"; --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ACE86A8A9; Thu, 8 Feb 2024 08:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381811; cv=none; b=GSrDquuCm6ReosBwzlY7ElS85236ioKKEl6gb67q9lpvcD9XfBZ2EAQKinQ08oX309UosZ6kuf101ne1eniwfz0Bb1Syz+QTZ47fLu7vETaZ+FNTaKWj35Mry8x21DxlR5fv2DNEvKeVwjh7cWTq+VYuNpIlopCbKz5ReDAxQFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381811; c=relaxed/simple; bh=+aNi52R66tEkJ5qtEomMdixTK7yA8vNGdrZlpkthNQg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YpNY5FxHsspcKJEw/WjlGZVuNW87l/rllbFtEOOdnDAHQoSBJJ+2jfzSQgJlfVMUQYYfGbhx9irEik+Rxfsa3M7M3is+9vqhl7bOgZbG9D7g3h7O+12+Uu2AxcY930/9FDNoa3XOyGFaopIMnYwM6f8C8hpNIlONbAZpHfzrTxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ODsLE5yD; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ODsLE5yD" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188h8Sf105044; Thu, 8 Feb 2024 02:43:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381788; bh=Ja71EasRRzr/RjhKuh+9EXL1qoKYEN0T/N6Ly83yc8U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ODsLE5yD2VIloyK3sD5T26gzJLjxC6TloC3BUGjtdWsU0+mirkwFUVYDruOnTJsin +eCVDRshGosOfqgXtPG4bcgsRxOGm2925Y7EAgGKmuHXp+Sep06kDBAgpMS3UcHqT5 nQA/KLHbf4ZOgC1/xOj+sxfkntKNFWji6tQ81WxI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188h8Pc031335 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:08 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:07 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:07 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshM097884; Thu, 8 Feb 2024 02:43:04 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:47 +0530 Message-ID: <20240208084254.295289-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 57e7cb8ea2b8..bb2558b68381 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -297,6 +297,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -761,6 +768,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A89036E2A4; Thu, 8 Feb 2024 08:43:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381828; cv=none; b=fsQ17ekV7fIC7oc5cP2XInPuNzfPNjCQMSrf3t3dmOS98c9GilqvmB8BOoKR07m8BtoGeP8/OJCZedsJ9nonmoR+koogX3PaMMpFCw22G8002G7o1E8AEFLf8r/OumYYPT4aFFDYU5mT3ItocnUysdnFdkh4VsnPil1mkWU5HBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381828; c=relaxed/simple; bh=4/7LooQWnhdKVtfbE7HqNZ6kk0Pd7g2CQiJtb6HGBoY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZtGUV72/j8keNbvOBE/X58Ybguh6NvljsDgcm48jnI4rEpsrDc9mbY2aXT2TVaRLk/HtOX6J2GlJDYNmbz5F0VCmfqRzheTft/4VOLahBqVawTe8mE7Yx7xuTI5HHnQemzokf6qJCmxsnBwyde6Jsm3Cf5jmrxWcvO6eP4FEcBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Vz7PWxx5; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Vz7PWxx5" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188hCcC050138; Thu, 8 Feb 2024 02:43:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381792; bh=4A4Z/qpcZA8AC33ULipWc2n/UZEdk4NC/YctUo/j1+g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vz7PWxx5vUoA9RiXWXMxTxYpqtbIhciTtJxK3Vad21cpOsOriearAlhANuQ5vFvZn 5Cls+0lkNq++L7TmANlLycHsDZLBmto8k1n+w6NgWi8GErbAc4/m8pxnUcqaLPOUIB OrWxMMEZpSWARiZTIj9IyIzZLAOQVI5DVqLNKZGc= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188hCPR025665 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:12 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:12 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:12 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshN097884; Thu, 8 Feb 2024 02:43:08 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:48 +0530 Message-ID: <20240208084254.295289-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index f48155dd16a3..d743f023cdd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; }; =20 &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + status =3D "okay"; + + exp3: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_i2c4 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0244F6BB30; Thu, 8 Feb 2024 08:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381815; cv=none; b=QZ+Wx0rTGG+/+XPvZxEUd5IeVtRuHF5e4vCw9OUY+MLwfLvwTeNHvw/GmxArjneikTpT3nO/y+iuJ6dcnaQ/TdpbIAGQKNdBaTTAEsUZU+7MI7LQ/MjWgpsW+2pg1JTBWvAj2zY2+kymy00DK3an1B/AmOZ4bjLNbNkx//cGlRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381815; c=relaxed/simple; bh=088r6S7/R9BOBDXxhqCmLynpzfajZ/iQ4e9x2jKogY0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=E1J8OklLvdxfkeICqdOAPWaNGYo0l4EKpUrKOuATCz2EViJUKWVLyNdCNR2+aXYZDCgLvR+NAeKkzp0sNltbfddpY4NPy6phua8pEyzJnkdlt/HavmS4J5xVmKOPESFYzp1T/V9BRo1qd0rXDDge+y8SZKDdwgZor/cI11maNm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jGlVQg1v; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jGlVQg1v" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188hGTr016775; Thu, 8 Feb 2024 02:43:16 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381796; bh=XYSJWaZbQUZ4rWgrWFja9l/jgfj6GB45OK068onqk5E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jGlVQg1v3bKJk1qbcc5Dcj13G7fDavgueyx4KFdUym+zWL5jfRLPd4Al8AEqBg58G vfMqgYsVramSSZidlZGoN7RiQRbsfTjrKKaOydEuU1XicvS7TVxkMkzvBEBmcug7tA 6p/99iGr/PAhKQYm4upt5CII4kowiSCxZeKUi9UI= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188hGBj043561 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:16 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:16 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:16 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshO097884; Thu, 8 Feb 2024 02:43:12 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:49 +0530 Message-ID: <20240208084254.295289-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 5f0a43a69333..46cf90bb3eb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -322,6 +322,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; + }; =20 &main_pmx0 { @@ -341,6 +349,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_S= CL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SD= A */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -775,6 +790,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp2: gpio@21 { + compatible =3D "ti,tca6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF6A76A8A0; Thu, 8 Feb 2024 08:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381811; cv=none; b=FC7pbct0mkd/xFC/jd304vyD0Of4qNCy4ZADH6RbkQO4v94ZszFKMgqSqOOeEaEUt2xr4yPgvjQdvCpF1LXrSR0N933FheN5zgdb1rXiC9bWaMlIsPjjEbcvQyzx5W4vSWH6FdlRkvRnQV8+3hI1efRE86IbriqS9pudyWO2YWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381811; c=relaxed/simple; bh=Bfg1oBdtSZWyL8lcck/OpMk2x5IZYqY6A91ia++vhW4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FThoh4EJq0MDGqBM54+jUT9natStXBQCoOq8dZI6KSKAnzWGaIcIwN/XRDwqEPUgMJZVHXjZQHY7NcChQrfB36W7VKGU79O0YNOBEn+4zT7kNLMi3ddErKrnJY61eD4phs5LE102ABT37VOAtjYZG/f5ljHD4ERWq5sLTwUHwWU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=H4jkpW+T; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="H4jkpW+T" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188hKt6105070; Thu, 8 Feb 2024 02:43:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381800; bh=CM6cjKv4l0J1fKXCqPw6lqdbgZjYConNlvuzN5ok03E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H4jkpW+TRMDQ/usc+d0k4BNCzGJRX/FGnzMJZ1ivhIt/PzKtspOZdmeGfKVY63MjY BLBZdA3HNDNTqaMiQsmobHTL5QEICfpySH/LEEcKn9CYicMdWiQPaBQOD6XkVjCG24 9nCj6KahJlxCiXnlpY+Yvlyyp/CSqnqSQo5GSBPo= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188hKk0031524 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:20 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:20 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:20 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshP097884; Thu, 8 Feb 2024 02:43:16 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Thu, 8 Feb 2024 14:12:50 +0530 Message-ID: <20240208084254.295289-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 6950b1ff124f..5dbc85bc5038 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_csi_mux_sel_pins_default>; + }; }; =20 &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB= 1_DRVVBUS */ >; }; =20 + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins =3D < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg =3D <0x70>; =20 /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0>; }; =20 /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <1>; --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C50516BB3D; Thu, 8 Feb 2024 08:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381818; cv=none; b=NdcPPNYxAeHlxD5MnyBWPH4B17Ep7jh+9O7YdhVZmZndr4x+mQFNBMyWYM4Q93f1uYNMD22eyv2BKVaI7QvGyxlqfvb4gfoVKziBY9XlYWzILUPVJEoAlCKKkQha0kUoJFDOfWtp8PXzcO5owuBIF3QTjxcXyPgEL3hG9eI8Coo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381818; c=relaxed/simple; bh=VAzmBh9X4jfrZpIF8Qmh/RJ8gtJ19fAAHYFCU+8g058=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GgvHWNYJvO5behEgncnt+J8ABSowhMIDRjB2OYhqg9hqIhYPxWU7JXaJtSdVjTdC8D0gPwean9MZAqhB2LTeicSsXt6nBFp+EfucQS4Yc03T2SB2tT2AH3CsEGU3pkFx8fcXWAOL/sve5g7QmFVbdY5AGd8W3sDeHTil9g5+OBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xUC+M93Z; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xUC+M93Z" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4188hPRB016790; Thu, 8 Feb 2024 02:43:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707381805; bh=7NqTnmRuEDsngPYCgeUqJWoO/hJRFSV+RfPuV9yubqw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xUC+M93ZGEviw0PXr+kbExntV+HAz9mkW+3RSTEjhPzjvlPU6crPup0O2c/reM/z+ ukV/ki1bEF9KRDUzFMm1a5qhVJH89W4NVZSH5dihKe8RolcRF8hl09Sh7Djf4zCNFr 8gZVDKUmxxjcd1VjDapdIp/6LEwAQzgMfJmL2i/Q= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4188hPTG018598 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Feb 2024 02:43:25 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Feb 2024 02:43:24 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Feb 2024 02:43:24 -0600 Received: from uda0490681.. ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshQ097884; Thu, 8 Feb 2024 02:43:21 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:51 +0530 Message-ID: <20240208084254.295289-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 062a6fca5a31..8df1eed80996 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask =3D <0x0000001f>; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_udmap 0x4940>; + dma-names =3D "rx0"; + reg =3D <0x0 0x4500000 0x0 0x1000>; + power-domains =3D <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4504000 0x0 0x1000>; + clocks =3D <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_udmap 0x4960>; + dma-names =3D "rx0"; + reg =3D <0x0 0x4510000 0x0 0x1000>; + power-domains =3D <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4514000 0x0 0x1000>; + clocks =3D <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4580000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4590000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible =3D "ti,j721e-wiz-16g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A339E6A8D1; Thu, 8 Feb 2024 08:43:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707381827; cv=none; b=BPbwHwOfvuRt7WmKXYwqIKAhhuuoZWe4mAMU29OluBOH8mfO6R+L2CdKfvWVoMGEvWB9hxtVe4KPubmdXAY4EQDw0ZtsRXulDzE28sSqZrN8tSjjGFKMsJNgLDU6H7Ojc7f/pRO6KhBbDxfFpqdKd7LDofrGsHP+JhBA4fjdrWQ= ARC-Message-Signature: i=1; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshR097884; Thu, 8 Feb 2024 02:43:25 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:52 +0530 Message-ID: <20240208084254.295289-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index dcaa4da0d678..a401e84a2eb2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <225>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04500000 0x00 0x1000>; + power-domains =3D <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x1000>; + clocks =3D <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + power-domains =3D <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x1000>; + clocks =3D <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible =3D "ti,j721s2-wiz-10g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA4ED6DCE5; Thu, 8 Feb 2024 08:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshS097884; Thu, 8 Feb 2024 02:43:29 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:53 +0530 Message-ID: <20240208084254.295289-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 3cb964982792..e3820ee52dbb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status =3D "disabled"; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04500000 0x00 0x00001000>; + power-domains =3D <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x00001000>; + clocks =3D <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + power-domains =3D <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x00001000>; + clocks =3D <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4980 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04520000 0x00 0x00001000>; + power-domains =3D <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04524000 0x00 0x00001000>; + clocks =3D <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy2>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi2_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi2_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi2_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi2_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy2: phy@45a0000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible =3D "ti,j721e-sdhci-8bit"; reg =3D <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <281>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { --=20 2.34.1 From nobody Sat Feb 7 23:11:05 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B7F6F064; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshT097884; Thu, 8 Feb 2024 02:43:33 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 9/9] arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 Date: Thu, 8 Feb 2024 14:12:54 +0530 Message-ID: <20240208084254.295289-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: * Rename overlays to indicate first platform (j721e-sk) supported and dual camera. * Add missed build test, fix missing newline. arch/arm64/boot/dts/ti/Makefile | 13 ++ .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 125 ++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 4a570dffb638..e019efd3ce94 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219.dtbo =20 # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb @@ -106,8 +107,14 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am68-sk-base-board-csi2-dual-imx219-dtbs :=3D k3-am68-sk-base-board.dtb= \ + k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-csi2-dual-imx219-dtbs :=3D k3-am69-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -122,7 +129,10 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ + k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb =20 # Enable support for device-tree overlays @@ -132,5 +142,8 @@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-am68-sk-base-board +=3D -@ +DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ +DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arc= h/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 000000000000..65d7cefb6063 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; + +&csi_mux { + idle-state =3D <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_0: imx219_0@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_1: imx219_1@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; --=20 2.34.1