From nobody Mon Feb 9 00:53:53 2026 Received: from relay.smtp-ext.broadcom.com (unknown [192.19.166.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C8AF12C53C for ; Wed, 7 Feb 2024 20:24:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.166.228 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707337450; cv=none; b=EsqJMllxC1eqz2jrfLpuS72XNRR6rP5Eb+iPJ76iocSrTW6HB1C3WKTN9ZalpzhbPKJ2759SnW4XH4P0ILRmJr2jbSEtJlId9BJeKfT3zgjI5IiQ3fXbISHJcsoJervmMQtTE1taJ3mMmNo8mY/nYnjUoX6xVFI0IYqIpNM7ZPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707337450; c=relaxed/simple; bh=1Yh76Q4bafQj8j8zmFp3LQ71wEoIHitjS2PH4qKEFkw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JfHtdIthiwQpbTRkQooVrwbmmcdzV+1G3s5lXpW7CSo3mLSogPrAlgg/q5YCsF7jCY8qOGzodOFSo/RQKFYsPHFgzWaXKY9WXWVAG51V4zwBFTAMuU6Jn+YeGGUBwBNbq4Bg0YS86l8PcD2VKwrWnkTP7MF0HduCR3JwzlWRrkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=mh5eTHW3; arc=none smtp.client-ip=192.19.166.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="mh5eTHW3" Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id DCBC9C0094CA; Wed, 7 Feb 2024 12:24:07 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com DCBC9C0094CA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1707337447; bh=1Yh76Q4bafQj8j8zmFp3LQ71wEoIHitjS2PH4qKEFkw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mh5eTHW3ecA8+Yd5hfuEAI6bzxkyankIbx4jjFcQK5LNCrnYe8YT5HgfHSByl+OMW Mp5X/1wxKS8XM0lm4MxP1zUwOTvZidsNnkB7frF+6AMMmquNlUHUixMkQG7g48gmMa JsPb7d+uovlY1Q9FMVvmDNaIDFxEzDT8Y2mSBMTE= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.173.232.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPSA id 6B45618041CAC4; Wed, 7 Feb 2024 12:24:06 -0800 (PST) From: William Zhang To: Linux MTD List , Linux ARM List , Broadcom Kernel List Cc: f.fainelli@gmail.com, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, anand.gore@broadcom.com, dregan@mail.com, kamal.dasu@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, William Zhang , David Regan , Miquel Raynal , linux-kernel@vger.kernel.org, Vignesh Raghavendra , Brian Norris , Richard Weinberger Subject: [PATCH v5 09/12] mtd: rawnand: brcmnand: Add support for getting ecc setting from strap Date: Wed, 7 Feb 2024 12:22:54 -0800 Message-Id: <20240207202257.271784-10-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240207202257.271784-1-william.zhang@broadcom.com> References: <20240207202257.271784-1-william.zhang@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BCMBCA broadband SoC based board design does not specify ecc setting in dts but rather use the SoC NAND strap info to obtain the ecc strength and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for this purpose and update driver to support this option. The generic nand ecc settings still take precedence over this flag. For example, if nand-ecc-strength is set in the dts, the driver ignores the strap setting and falls back to original behavior. This makes sure that the existing BCMBCA board dts still works the old way even the strap flag is set in the BCMBCA chip dtsi. Signed-off-by: William Zhang Reviewed-by: David Regan --- Changes in v5: None Changes in v4: - Update the comments for ecc setting selection Changes in v3: None Changes in v2: - Minor cosmetic fixes drivers/mtd/nand/raw/brcmnand/brcmnand.c | 83 ++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/ra= w/brcmnand/brcmnand.c index 73fdf7ce21aa..efeee9e80213 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1038,6 +1038,19 @@ static inline int brcmnand_sector_1k_shift(struct br= cmnand_controller *ctrl) return -1; } =20 +static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) +{ + struct brcmnand_controller *ctrl =3D host->ctrl; + int shift =3D brcmnand_sector_1k_shift(ctrl); + u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs, + BRCMNAND_CS_ACC_CONTROL); + + if (shift < 0) + return 0; + + return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; +} + static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int va= l) { struct brcmnand_controller *ctrl =3D host->ctrl; @@ -1055,6 +1068,38 @@ static void brcmnand_set_sector_size_1k(struct brcmn= and_host *host, int val) nand_writereg(ctrl, acc_control_offs, tmp); } =20 +static int brcmnand_get_spare_size(struct brcmnand_host *host) +{ + struct brcmnand_controller *ctrl =3D host->ctrl; + u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs, + BRCMNAND_CS_ACC_CONTROL); + u32 acc =3D nand_readreg(ctrl, acc_control_offs); + + return (acc & brcmnand_spare_area_mask(ctrl)); +} + +static int brcmnand_get_ecc_strength(struct brcmnand_host *host) +{ + struct brcmnand_controller *ctrl =3D host->ctrl; + u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs, + BRCMNAND_CS_ACC_CONTROL); + int sector_size_1k =3D brcmnand_get_sector_size_1k(host); + int spare_area_size, ecc_level, ecc_strength; + u32 acc; + + spare_area_size =3D brcmnand_get_spare_size(host); + acc =3D nand_readreg(ctrl, acc_control_offs); + ecc_level =3D (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_sh= ift; + if (sector_size_1k) + ecc_strength =3D ecc_level * 2; + else if (spare_area_size =3D=3D 16 && ecc_level =3D=3D 15) + ecc_strength =3D 1; /* hamming */ + else + ecc_strength =3D ecc_level; + + return ecc_strength; +} + /*********************************************************************** * CS_NAND_SELECT ***********************************************************************/ @@ -2622,19 +2667,43 @@ static int brcmnand_setup_dev(struct brcmnand_host = *host) nanddev_get_memorg(&chip->base); struct brcmnand_controller *ctrl =3D host->ctrl; struct brcmnand_cfg *cfg =3D &host->hwcfg; - char msg[128]; + struct device_node *np =3D nand_get_flash_node(chip); u32 offs, tmp, oob_sector; - int ret; + int ret, sector_size_1k =3D 0; + bool use_strap =3D false; + char msg[128]; =20 memset(cfg, 0, sizeof(*cfg)); + use_strap =3D of_property_read_bool(np, "brcm,nand-ecc-use-strap"); =20 - ret =3D of_property_read_u32(nand_get_flash_node(chip), - "brcm,nand-oob-sector-size", + /* + * Set ECC size and strength based on hw configuration from strap + * if brcm,nand-ecc-use-strap is set. However if nand-ecc-strength + * is set, its value will be used and ignore the strap setting. + */ + if (chip->ecc.strength) + use_strap =3D 0; + + if (use_strap) { + chip->ecc.strength =3D brcmnand_get_ecc_strength(host); + sector_size_1k =3D brcmnand_get_sector_size_1k(host); + if (chip->ecc.size =3D=3D 0) { + if (sector_size_1k < 0) + chip->ecc.size =3D 512; + else + chip->ecc.size =3D 512 << sector_size_1k; + } + } + + ret =3D of_property_read_u32(np, "brcm,nand-oob-sector-size", &oob_sector); if (ret) { - /* Use detected size */ - cfg->spare_area_size =3D mtd->oobsize / - (mtd->writesize >> FC_SHIFT); + if (use_strap) + cfg->spare_area_size =3D brcmnand_get_spare_size(host); + else + /* Use detected size */ + cfg->spare_area_size =3D mtd->oobsize / + (mtd->writesize >> FC_SHIFT); } else { cfg->spare_area_size =3D oob_sector; } --=20 2.37.3